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| author | Eric Norum <WENorum@lbl.gov> | 2005-01-31 19:03:41 +0000 |
|---|---|---|
| committer | Eric Norum <WENorum@lbl.gov> | 2005-01-31 19:03:41 +0000 |
| commit | 518edef387ec306d7c7a3eda153d8625e54a4324 (patch) | |
| tree | 485c6da5a84de4fa020723552a4f54f5af5ff79b /c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c | |
| parent | Add ColdFire cache information. (diff) | |
| download | rtems-518edef387ec306d7c7a3eda153d8625e54a4324.tar.bz2 | |
Processor doesn't snoop FEC DMA so we must invalidate the cache appropriately.
Diffstat (limited to '')
| -rw-r--r-- | c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c index 2b050a0276..c179b61497 100644 --- a/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c @@ -109,7 +109,11 @@ void _CPU_cache_invalidate_entire_instruction(void) void _CPU_cache_invalidate_1_instruction_line(const void *addr) { - asm volatile ("cpushl %%ic,(%0)" :: "a" (addr)); + /* + * Top half of cache is I-space + */ + addr = (void *)((int)addr | 0x400); + asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); } void _CPU_cache_enable_data(void) @@ -127,6 +131,7 @@ void _CPU_cache_disable_data(void) rtems_interrupt_level level; rtems_interrupt_disable(level); + rtems_interrupt_disable(level); cacr_mode |= MCF5XXX_CACR_DISD; m68k_set_cacr(cacr_mode); rtems_interrupt_enable(level); @@ -139,7 +144,11 @@ void _CPU_cache_invalidate_entire_data(void) void _CPU_cache_invalidate_1_data_line(const void *addr) { - asm volatile ("cpushl %%dc,(%0)" :: "a" (addr)); + /* + * Bottom half of cache is D-space + */ + addr = (void *)((int)addr & ~0x400); + asm volatile ("cpushl %%bc,(%0)" :: "a" (addr)); } /* |