bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

6 files changed, 4 insertions, 347 deletions

diff --git a/c/src/lib/libbsp/m68k/mvme167/Makefile.am b/c/src/lib/libbsp/m68k/mvme167/Makefile.am
index 0fee829838..7cca60608f 100644
--- a/c/src/lib/libbsp/m68k/mvme167/Makefile.am
+++ b/c/src/lib/libbsp/m68k/mvme167/Makefile.am
@@ -3,7 +3,7 @@ ACLOCAL_AMFLAGS = -I ../../../../aclocal
 include $(top_srcdir)/../../../../automake/compile.am
 include $(top_srcdir)/../../bsp.am
 
-dist_project_lib_DATA = startup/bsp_specs
+dist_project_lib_DATA = ../../../../../../bsps/m68k/mvme167/start/bsp_specs
 
 noinst_PROGRAMS =
 
@@ -18,11 +18,11 @@ project_lib_LIBRARIES = librtemsbsp.a
 librtemsbsp_a_SOURCES =
 
 # startup
-librtemsbsp_a_SOURCES += startup/bspclean.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/m68k/mvme167/start/bspclean.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspgetworkarea-default.c
-librtemsbsp_a_SOURCES += startup/bspstart.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/m68k/mvme167/start/bspstart.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/dev/getentropy/getentropy-cpucounter.c
-librtemsbsp_a_SOURCES += startup/page_table.c
+librtemsbsp_a_SOURCES += ../../../../../../bsps/m68k/mvme167/start/page_table.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/sbrk.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/setvec.c
 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspreset-empty.c
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/bsp_specs b/c/src/lib/libbsp/m68k/mvme167/startup/bsp_specs
deleted file mode 100644
index 87638cc027..0000000000
--- a/c/src/lib/libbsp/m68k/mvme167/startup/bsp_specs
+++ /dev/null
@@ -1,9 +0,0 @@
-%rename endfile old_endfile
-%rename startfile old_startfile
-
-*startfile:
-%{!qrtems: %(old_startfile)} \
-%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
-
-*endfile:
-%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/bspclean.c b/c/src/lib/libbsp/m68k/mvme167/startup/bspclean.c
deleted file mode 100644
index 2dd980fdb4..0000000000
--- a/c/src/lib/libbsp/m68k/mvme167/startup/bspclean.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/** 
- *  @file
- *
- *  These routines return control to 167Bug after a normal exit from the
- *  application.
- */
-
-/*
- *  COPYRIGHT (c) 1989-2012.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- *  Modifications of respective RTEMS files:
- *  Copyright (c) 1998, National Research Council of Canada
- */
-
-#include <bsp.h>
-#include <bsp/bootcard.h>
-#include <page_table.h>
-
-extern void start( void );
-extern void page_table_teardown( void );
-
-/**
- *  @brief bsp_return_to_monitor_trap
- *
- *  Switch the VBR back to ROM and make a .RETURN syscall to return control to
- *  167 Bug. If 167Bug ever returns, restart the application.
- */
-static void bsp_return_to_monitor_trap( void )
-{
-  register volatile void *start_addr;
-
-  page_table_teardown();
-
-  lcsr->intr_ena = 0;               /* disable interrupts */
-  m68k_set_vbr(0xFFE00000);         /* restore 167Bug vectors */
-  __asm__ volatile( "trap   #15\n\t"    /* trap to 167Bug */
-                ".short 0x63" );    /* return to 167Bug (.RETURN) */
-
-  /* restart program */
-  start_addr = start;
-  __asm__ volatile( "jmp %0@" : "=a" (start_addr) : "0" (start_addr) );
-}
-
-/*
- *  This code was copied from other MC680x0 MVME BSPs.
- *  Our guess is that someone was concerned about the CPU no longer being in
- *  supervisor mode when they got here. This function forces the CPU back to
- *  supervisor mode so the VBR may be changed. It places the address of the
- *  function that makes a 167Bug .RETURN syscall in the trap 13 entry in the
- *  exception vector, and then issues a trap 13 call. It is also possible that
- *  the code was copied from some other OS that does run tasks in user mode.
- *  In any case, it appears to be a bit of paranoia, and could lead to
- *  problems if 167Bug is invoked before we get to switch the VBR back to
- *  167Bug because trap 13 is documented as being reserved for the internal
- *  use of the debugger.
- */
-void bsp_fatal_extension(
-  rtems_fatal_source source,
-  bool always_set_to_false,
-  rtems_fatal_code error
-)
-{
-   M68Kvec[ 45 ] = bsp_return_to_monitor_trap;
-   __asm__ volatile( "trap #13" );
-}
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme167/startup/bspstart.c
deleted file mode 100644
index 7ff6d2b118..0000000000
--- a/c/src/lib/libbsp/m68k/mvme167/startup/bspstart.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/**
- *  @file
- *
- *  Board-specific initialization code. Called from the generic boot_card()
- *  function defined in rtems/c/src/lib/libbsp/shared/main.c. That function
- *  does some of the board independent initialization. It is called from the
- *  generic MC680x0 entry point _start() defined in
- *  rtems/c/src/lib/start/m68k/start.s
- *
- *  _start() has set up a stack, has zeroed the .bss section, has turned off
- *  interrupts, and placed the processor in the supervisor mode. boot_card()
- *  has left the processor in that state when bsp_start() was called.
- *
- *  RUNS WITH ADDRESS TRANSLATION AND CACHING TURNED OFF!
- *  ASSUMES THAT THE VIRTUAL ADDRESSES WILL BE IDENTICAL TO THE PHYSICAL
- *  ADDRESSES. Software-controlled address translation would be required
- *  otherwise.
- *
- *  ASSUMES THAT 167BUG IS PRESENT TO CATCH ANY EXCEPTIONS DURING
- *  INITIALIZATION.
- */
-
-/*
- *  COPYRIGHT (c) 1989-2012.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- *
- *  Modifications of respective RTEMS files:
- *  Copyright (c) 1998, National Research Council of Canada
- */
-
-#include <bsp.h>
-#include <bsp/bootcard.h>
-#include <page_table.h>
-
-void M68KFPSPInstallExceptionHandlers (void);
-
-void bsp_start( void )
-{
-  void **rom_monitor_vector_table;
-  int index;
-
-  /*
-   *  167Bug Vectors are at 0xFFE00000
-   */
-  rom_monitor_vector_table = (void **)0xFFE00000;
-  m68k_set_vbr( rom_monitor_vector_table );
-
-  /*
-   *  Copy 167Bug Bus Error handler into our exception vector. All 167Bug
-   *  exception vectors are the same and point to the generalized exception
-   *  handler. The bus error handler is the one that Motorola says to copy
-   *  (p. 2-13, Debugging Package for Motorola 68K CISC CPUs User's Manual
-   *  68KBUG/D1A3, October 1993).
-   */
-  for ( index=2 ; index<=255 ; index++ )
-    M68Kvec[ index ] = rom_monitor_vector_table[ 2 ];
-
-  /* Any exceptions during initialization should be trapped by 167Bug */
-  m68k_set_vbr( &M68Kvec );
-
-  /* Install the 68040 FPSP here */
-  M68KFPSPInstallExceptionHandlers();
-
-  /*
-   *  You may wish to make the VME arbitration round-robin here, currently
-   *  we leave it as it is.
-   */
-
-  /* Set the Interrupt Base Vectors */
-  lcsr->vector_base = (VBR0 << 28) | (VBR1 << 24);
-
-  /*
-   *  Initialize address translation
-   */
-  page_table_init();
-}
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/linkcmds b/c/src/lib/libbsp/m68k/mvme167/startup/linkcmds
deleted file mode 100644
index dc50449b29..0000000000
--- a/c/src/lib/libbsp/m68k/mvme167/startup/linkcmds
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  This file contains directives for the GNU linker which are specific
- *  to the Motorola MVME167 board.
- *
- *  Copyright (c) 1999, National Research Council of Canada.
- *  Some of this material was copied from binutils-2.9.4 linker scripts,
- *  and is therefore likely to be copyrighted by the Free Software
- *  Foundation, even though explicit copyright notices did not appear in
- *  those files.
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.org/license/LICENSE.
- */
-
-RamBase = DEFINED(RamBase) ? RamBase : 0x00800000;
-RamSize = DEFINED(RamSize) ? RamSize : 4M;
-
-MEMORY
-{
-  /*  The location of RAM is the address space is configurable.
-      This is where we put one board. The base address should be
-      passed as a parameter when building multiprocessor images
-      where each board resides at a different address. */
-  ram  : org = RamBase, l = RamSize
-  rom  : org = 0xFF800000, l = 4M
-  sram : org = 0xFFE00000, l = 128K
-}
-
-REGION_ALIAS ("REGION_TEXT", ram);
-REGION_ALIAS ("REGION_TEXT_LOAD", ram);
-REGION_ALIAS ("REGION_DATA", ram);
-REGION_ALIAS ("REGION_DATA_LOAD", ram);
-
-INCLUDE linkcmds.base
diff --git a/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c b/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c
deleted file mode 100644
index da50e511b0..0000000000
--- a/c/src/lib/libbsp/m68k/mvme167/startup/page_table.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*  page_table.c
- *
- *  The code submitted by Eric Vaitl <vaitl@viasat.com> for the MVME162 appears
- *  to be for a uniprocessor implementation. The function that sets up the
- *  page tables, page_table_init(), is not data driven. For all processors, it
- *  sets up page tables to map virtual addresses from 0x20000 to 0x3FFFFF to
- *  physical addresses 0x20000 to 0x3FFFFF. This presumably maps a subset of
- *  a local 4 MB space, which is probably the amount of RAM on Eric Vailt's
- *  MVME162.
- *
- *  It is possible to set up the various bus bridges in the MVME167s to create
- *  a flat physical address space across multiple boards, i.e., it is possible
- *  for each MVME167 in a multiprocessor system to access a given memory
- *  location using the same physical address, whether that location is in local
- *  or VME space. Addres translation can be set up so that each virtual address
- *  maps to its corresponding physical address, e.g. virtual address 0x12345678
- *  is mapped to physical address 0x12345678. With this mapping, the MMU is
- *  only used to control the caching modes for the various regions of memory.
- *  Mapping the virtual addresses to their corresponding physical address makes
- *  it unnecessary to map addresses under software control during the
- *  initialization of RTEMS, before address translation is turned on.
- *
- *  With the above approach, address translation may be set up either with the
- *  transparent address translation registers, or with page tables. If page
- *  tables are used, a more efficient use of page table space can be achieved
- *  by sharing the page tables between processors. The entire page table tree
- *  can be shared, or each processor can hold a private copy of the top nodes
- *  which point to leaf nodes stored on individual processors.
- *
- *  In this port, only the transparent address translation registers are used.
- *  We map the entire virtual range from 0x0 to 0x7FFFFFFF to the identical
- *  physical range 0x0 to 0x7FFFFFFF. We rely on the hardware to signal bus
- *  errors if we address non-existent memory within this range. Our two
- *  MVME167s are configured to exist at physical addresses 0x00800000 to
- *  0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. If jumper J1-4 is
- *  installed, memory and cache control can be done by providing parameters
- *  in NVRAM and jumpers J1-[5-7] are ignored. See the README for details.
- *  If J1-4 is removed, behaviour defaults to the following. We map the space
- *  from 0x0 to 0x7FFFFFFF as copyback, unless jumper J1-5 is removed, in which
- *  case we map as writethrough. If jumper J1-7 is removed, the data cache is
- *  NOT enabled. If jumper J1-6 is removed, the instruction cache is not enabled.
- *
- *  Copyright (c) 1998, National Research Council of Canada
- */
-
-#include <bsp.h>
-#include <page_table.h>                 /* Nothing in here for us */
-
-/*
- *  page_table_init
- *
- *  Map the virtual range 0x00000000--0x7FFFFFFF to the physical range
- *  0x00000000--0x7FFFFFFF. Rely on the hardware to raise exceptions when
- *  addressing non-existent memory. Use only the transparent translation
- *  registers (for now).
- *
- *  On all processors, the local virtual address range 0xFF000000--0xFFFFFFFF
- *  is mapped to the physical address range 0xFF000000--0xFFFFFFFF as
- *  caching disabled, serialized access.
- *
- *  Output parameters: NONE
- *
- *  Return values: NONE
- */
-void page_table_init( void )
-{
-  unsigned char j1;               /* State of J1 jumpers */
-  register unsigned long dtt0;    /* Content of dtt0 */
-  register unsigned long cacr;    /* Content of cacr */
-
-  /*
-   *  Logical base addr = 0x00    map starting at 0x00000000
-   *  Logical address mask = 0x7F map up to 0x7FFFFFFF
-   *  E = 0b1                     enable address translation
-   *  S-Field = 0b1X              ignore FC2 when matching
-   *  U1, U0 = 0b00               user page attributes not used
-   *  CM = 0b01                   cachable, copyback
-   *  W = 0b0                     read/write access allowed
-   */
-  dtt0 = 0x007FC020;
-
-  cacr = 0x00000000;              /* Data and instruction cache off */
-
-  /* Read the J1 header */
-  j1 = (unsigned char)(lcsr->vector_base & 0xFF);
-
-  if ( !(j1 & 0x10) ) {
-  	/* Jumper J1-4 is on, configure from NVRAM */
-
-  	if ( nvram->cache_mode & 0x01 )
-  		cacr |= 0x80000000;
-
-  	if ( nvram->cache_mode & 0x02 )
-  		cacr |= 0x00008000;
-
-  	if ( nvram->cache_mode )
-  		dtt0 = ((nvram->cache_mode & 0x0C) << 3) | (dtt0 & 0xFFFFFF9F);
-  }
-	else {
-		/* Configure according to other jumper settings */
-
-	  if ( !(j1 & 0x80) )
-  	  /* Jumper J1-7 if on, enable data caching */
-   		cacr |= 0x80000000;
-
-	  if ( !(j1 & 0x40) )
-	    /* Jumper J1-6 if on, enable instruction caching */
-	    cacr |= 0x00008000;
-
-	  if ( j1 & 0x20 )
-	    /* Jumper J1-5 is off, enable writethrough caching */
-	    dtt0 &= 0xFFFFFF9F;
-	}
-
-  /* do it ! */
-  __asm__ volatile("movec %0, %%tc\n\t"    /* turn off paged address translation */
-               "movec %0, %%cacr\n\t"  /* disable both caches */
-               "cinva %%bc\n\t"        /* clear both caches */
-               "movec %1,%%dtt0\n\t"   /* block address translation on */
-               "movec %1,%%itt0\n\t"
-               "movec %2,%%dtt1\n\t"
-               "movec %2,%%itt1\n\t"
-               "movec %3,%%cacr"       /* data cache on */
-	  :: "d" (0), "d" (dtt0), "d" (0xFF00C040), "d" (cacr));
-}
-
-/*
- *  page_table_teardown
- *
- *  Turn off paging. Turn off the cache. Flush the cache. Tear down
- *  the transparent translations.
- *
- *  Input parameters: NONE
- *
- *  Output parameters: NONE
- *
- *  Return values: NONE
- */
-void page_table_teardown( void )
-{
-  __asm__ volatile ("movec %0,%%tc\n\t"
-                "movec %0,%%cacr\n\t"
-                "cpusha %%bc\n\t"
-                "movec %0,%%dtt0\n\t"
-                "movec %0,%%itt0\n\t"
-                "movec %0,%%dtt1\n\t"
-                "movec %0,%%itt1"
-    :: "d" (0) );
-}