m68k/mrm332: changes required to get the mrm332 bsp working again.

Changed console driver to use interrupts instead of polling.
Change to avoid overwriting CPU32Bug interrupt vector when setting up the Sci interrupt handler.
Fixed type for boolean flag in bsp.h.
Changed mrm332.h to use 25Mhz clock.
Fixes to mrm332.cfg to use correct mcpu32 value for RTEMS_CPU_MODEL instead of m68332 which is no longer supported.
Added -mcpu=cpu32 to compiler options.
Removed broken ROM linker script and replaced broken RAM linker script with working ROM linker script.
Removed no longer required file except_vect_332_ROM.S.
Enabled 0xbeefbeef magic string in start.S to allow MRM version of CPU32Bug to auto run RTEMS.
Removed old code from start.S
Changed compiler optimization flag to optimize for size.

1 files changed, 17 insertions, 108 deletions

diff --git a/c/src/lib/libbsp/m68k/mrm332/start/start.S b/c/src/lib/libbsp/m68k/mrm332/start/start.S
index e8f75140ff..5e2bbebc8e 100644
--- a/c/src/lib/libbsp/m68k/mrm332/start/start.S
+++ b/c/src/lib/libbsp/m68k/mrm332/start/start.S
@@ -22,7 +22,7 @@ BEGIN_CODE
 
   /* Put the header necessary for the modified CPU32bug to automatically
      start up rtems: */
-#if 0
+#if 1
 .long 0xbeefbeef ;
 #endif
 .long 0 ;
@@ -31,11 +31,16 @@ BEGIN_CODE
 .global start
 	start:
 
-	oriw   #0x0700,sr
-	movel  #end, d0
-	addl   #_StackSize,d0
+	oriw   #0x0700,sr 			/* Mask off interupts */
+
+	// Set VBR to CPU32Bug vector table address
+	movel	#0x0,d0				/* Use the initial vectors until we get going */
+	movecl	d0,vbr
+
+	movel  #end, d0				/* Next 3 instructions set stack pointer    */
+	addl   #_StackSize,d0       /* sp = end + _StackSize from linker script */
 	movel  d0,sp
-	movel  d0,a6
+	movel  d0,a6			
 
   /* include in ram_init.S */
   /*
@@ -46,6 +51,13 @@ BEGIN_CODE
 
   /* Module Configuration Register */
   /*    see section(s) 3.1.3-3.1.6 of the SIM Reference Manual */
+  /* SIMCR etc and SAM macro all defined in sim.h found at     */
+  /* /cpukit/score/cpu/m68k/rtems/m68k/sim.h				   */
+  /* The code below does the following:						   */
+  /*	- Sets Freeze Software Enable						   */
+  /*	- Turns off Show Cycle Enable						   */
+  /* 	- Sets the location of SIM module mapping			   */
+  /* 	- Sets the SIM Interrupt Arbitration Field			   */
 	lea	SIMCR, a0
 	movew	#FRZSW,d0
 	oriw	#SAM(0,8,SHEN),d0
@@ -57,106 +69,3 @@ BEGIN_CODE
 
 END_CODE
 
-#if 0
-
-  /* Synthesizer Control Register */
-  /*    see section(s) 4.8 */
-  /* end include in ram_init.S */
-  *SYNCR = (unsigned short int)
-    ( SAM(MRM_W,15,VCO) | SAM(0x0,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
-  while (! (*SYNCR & SLOCK));	/* protect from clock overshoot */
-  /* include in ram_init.S */
-  *SYNCR = (unsigned short int)
-    ( SAM(MRM_W,15,VCO) | SAM(MRM_X,14,PRESCALE) | SAM(MRM_Y,8,COUNTER) );
-
-  /* System Protection Control Register */
-  /*    !!! can only write to once after reset !!! */
-  /*    see section 3.8.4 of the SIM Reference Manual */
-  *SYPCR = (unsigned char)( HME | BME );
-
-  /* Periodic Interrupr Control Register */
-  /*    see section 3.8.2 of the SIM Reference Manual */
-  *PICR = (unsigned short int)
-    ( SAM(0,8,PIRQL) | SAM(MRM_PIV,0,PIV) );
-  /*     ^^^ zero disables interrupt, don't enable here or ram_init will
-	 be wrong. It's enabled below. */
-
-  /* Periodic Interrupt Timer Register */
-  /*    see section 3.8.3 of the SIM Reference Manual */
-  *PITR = (unsigned short int)( SAM(0x09,0,PITM) );
-  /*    1.098mS interrupt, assuming 32.768 KHz input clock */
-
-  /* Port C Data */
-  /*    load values before enabled */
-  *PORTC = (unsigned char) 0x0;
-
-  /* Port E and F Data Register */
-  /*    see section 9 of the SIM Reference Manual */
-  *PORTE0 = (unsigned char) 0;
-  *PORTF0 = (unsigned char) 0;
-
-  /* Port E and F Data Direction Register */
-  /*    see section 9 of the SIM Reference Manual */
-  *DDRE = (unsigned char) 0xff;
-  *DDRF = (unsigned char) 0xfd;
-
-  /* Port E and F Pin Assignment Register */
-  /*    see section 9 of the SIM Reference Manual */
-  *PEPAR = (unsigned char) 0;
-  *PFPAR = (unsigned char) 0;
-
-  /* end of SIM initalization code */
-  /* end include in ram_init.S */
-
-  /*
-   * Initialize RAM by copying the .data section out of ROM (if
-   * needed) and "zero-ing" the .bss section.
-   */
-  {
-    register char *src = _etext;
-    register char *dst = _copy_start;
-
-    if (_copy_data_from_rom)
-      /* ROM has data at end of text; copy it. */
-      while (dst < _edata)
-	*dst++ = *src++;
-
-    /* Zero bss */
-    for (dst = _clear_start; dst< end; dst++)
-      {
-	*dst = 0;
-      }
-  }
-
-  /*
-   * Initialize vector table.
-   */
-  {
-    rtems_isr_entry *monitors_vector_table;
-
-    m68k_get_vbr(monitors_vector_table);
-
-    M68Kvec[  4 ] = monitors_vector_table[  4 ];   /* breakpoints vector */
-    M68Kvec[  9 ] = monitors_vector_table[  9 ];   /* trace vector */
-    M68Kvec[ 31 ] = monitors_vector_table[ 31 ];   /* level 7 interrupt */
-    M68Kvec[ 47 ] = monitors_vector_table[ 47 ];   /* system call vector */
-    M68Kvec[ 66 ] = monitors_vector_table[ 66 ];   /* user defined */
-
-    m68k_set_vbr(&M68Kvec);
-  }
-
-  /*
-   * Initalize the board.
-   */
-  Spurious_Initialize();
-  console_init();
-
-  /*
-   * Execute main with arguments argc and agrv.
-   */
-  boot_card((void*)0);
-  reboot();
-
-}
-
-#endif