Whitespace removal.

1 files changed, 137 insertions, 137 deletions

diff --git a/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c b/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
index 337ef2561d..d265ca95ac 100644
--- a/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
+++ b/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
@@ -2,22 +2,22 @@
 /*********************************************************************
 * Initialisation Code for ColdFire MCF5329 Processor                 *
 **********************************************************************
- Generated by ColdFire Initialisation Utility 2.10.8 
- Wed Jul 02 14:26:25 2008 
-   
- MicroAPL Ltd makes no warranties in respect of the suitability 
- of this code for any particular purpose, and accepts 
- no liability for any loss arising out of its use. The person or  
- persons making use of this file must make the final evaluation 
- as to its suitability and correctness for a particular application. 
+ Generated by ColdFire Initialisation Utility 2.10.8
+ Wed Jul 02 14:26:25 2008
+
+ MicroAPL Ltd makes no warranties in respect of the suitability
+ of this code for any particular purpose, and accepts
+ no liability for any loss arising out of its use. The person or
+ persons making use of this file must make the final evaluation
+ as to its suitability and correctness for a particular application.
 
  $Id$
-   
+
 */
 
-/* External reference frequency is 16.0000 MHz 
- Internal bus clock frequency = 80.00 MHz 
- Processor core frequency = 240.00 MHz 
+/* External reference frequency is 16.0000 MHz
+ Internal bus clock frequency = 80.00 MHz
+ Processor core frequency = 240.00 MHz
 */
 
 #include <bsp.h>
@@ -49,7 +49,7 @@ static void init_real_time_clock(void);
 static void init_watchdog_timers(void);
 static void init_edma(void);
 static void init_pin_assignments(void);
-extern void init_sdram_controller(void) 
+extern void init_sdram_controller(void)
   __attribute__ ((section(".ram_code")));
 static void init_interrupt_controller(void);
 
@@ -127,22 +127,22 @@ static void disable_cache(void)
 **********************************************************************/
 void init_clock_config(void)
 {
-  /* Clock module uses normal PLL mode with 16.0000 MHz external reference 
-     Bus clock frequency = 80.00 MHz 
-     Processor clock frequency = 3 x bus clock = 240.00 MHz 
-     Dithering disabled 
+  /* Clock module uses normal PLL mode with 16.0000 MHz external reference
+     Bus clock frequency = 80.00 MHz
+     Processor clock frequency = 3 x bus clock = 240.00 MHz
+     Dithering disabled
    */
 
-  /* Check to see if the SDRAM has already been initialized 
-     by a run control tool. If it has, put SDRAM into self-refresh mode before 
-     initializing the PLL 
+  /* Check to see if the SDRAM has already been initialized
+     by a run control tool. If it has, put SDRAM into self-refresh mode before
+     initializing the PLL
    */
   if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
     MCF_SDRAMC_SDCR &= ~MCF_SDRAMC_SDCR_CKE;
 
-  /* Temporarily switch to LIMP mode 
-     NOTE: Ensure that this code is not executing from SDRAM, since the  
-     SDRAM Controller is disabled in LIMP mode  
+  /* Temporarily switch to LIMP mode
+     NOTE: Ensure that this code is not executing from SDRAM, since the
+     SDRAM Controller is disabled in LIMP mode
    */
   MCF_CCM_CDR = (MCF_CCM_CDR & 0xf0ff) | MCF_CCM_CDR_LPDIV(0x2);
   MCF_CCM_MISCCR |= MCF_CCM_MISCCR_LIMP;
@@ -157,11 +157,11 @@ void init_clock_config(void)
   MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_LIMP;
   while ((MCF_CCM_MISCCR & MCF_CCM_MISCCR_PLL_LOCK) == 0) ;
 
-  /* From the Device Errata: 
+  /* From the Device Errata:
 
-     "After exiting LIMP mode, the value of 0x40000000 should be written 
-     to address 0xFC0B8080 before attempting to initialize the SDRAMC 
-     or exit the SDRAM from self-refresh mode." 
+     "After exiting LIMP mode, the value of 0x40000000 should be written
+     to address 0xFC0B8080 before attempting to initialize the SDRAMC
+     or exit the SDRAM from self-refresh mode."
    */
   *(vuint32 *) 0xfc0b8080 = 0x40000000;
 
@@ -175,8 +175,8 @@ void init_clock_config(void)
 **********************************************************************/
 static void init_cache(void)
 {
-  /* ACR0: Cache accesses to 32 MB memory region at address $40000000 
-     CACR: Don't cache accesses to the rest of memory 
+  /* ACR0: Cache accesses to 32 MB memory region at address $40000000
+     CACR: Don't cache accesses to the rest of memory
    */
   /*
    * Cache is enabled in bspstart.c
@@ -184,7 +184,7 @@ static void init_cache(void)
 #if 0
   asm("move.l   #0xa0000600,%d0");
   asm("movec    %d0,%CACR");
-#endif  
+#endif
   asm("move.l   #0x4001c020,%d0");
   asm("movec    %d0,%ACR0");
   asm("move.l   #0x00000000,%d0");
@@ -196,32 +196,32 @@ static void init_cache(void)
 **********************************************************************/
 static void init_crossbar(void)
 {
-  /* XBS settings for FlexBus/SDRAM Controller slave:  
-     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core 
+  /* XBS settings for FlexBus/SDRAM Controller slave:
+     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core
    */
   MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
     MCF_XBS_PRS_M5(0x4) |
     MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
   MCF_XBS_CRS1 = 0;
 
-  /* XBS settings for SRAM Backdoor slave:  
-     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+  /* XBS settings for SRAM Backdoor slave:
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    */
   MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
     MCF_XBS_PRS_M5(0x4) |
     MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
   MCF_XBS_CRS4 = 0;
 
-  /* XBS settings for Cryptography Modules slave:  
-     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+  /* XBS settings for Cryptography Modules slave:
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    */
   MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
     MCF_XBS_PRS_M5(0x4) |
     MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
   MCF_XBS_CRS6 = 0;
 
-  /* XBS settings for On-chip Peripherals slave:  
-     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+  /* XBS settings for On-chip Peripherals slave:
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core
    */
   MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
     MCF_XBS_PRS_M5(0x4) |
@@ -249,11 +249,11 @@ void init_chip_selects(void)
   /* Chip Select 5 disabled (CSMR5[V] = 0) */
   MCF_FBCS5_CSMR = 0;
 
-  /* Chip Select 0: 2 MB of Flash at base address $00000000 
-     Port size = 16 bits 
-     Assert chip select on first rising clock edge after address is asserted 
-     Generate internal transfer acknowledge after 7 wait states 
-     Address is held for 1 clock at end of read and write cycles 
+  /* Chip Select 0: 2 MB of Flash at base address $00000000
+     Port size = 16 bits
+     Assert chip select on first rising clock edge after address is asserted
+     Generate internal transfer acknowledge after 7 wait states
+     Address is held for 1 clock at end of read and write cycles
    */
   MCF_FBCS0_CSAR = 0;
   MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
@@ -293,40 +293,40 @@ static void init_flexcan(void)
 **********************************************************************/
 void init_sdram_controller(void)
 {
-  /* Check to see if the SDRAM has already been initialized 
-     by a run control tool and skip if so 
+  /* Check to see if the SDRAM has already been initialized
+     by a run control tool and skip if so
    */
   if (MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF)
     return;
 
-  /* Ensure that there is a delay from processor reset of the time recommended in 
-     the SDRAM data sheet (typically 100-200 microseconds) until the following  
-     code so that the SDRAM is ready for commands... 
+  /* Ensure that there is a delay from processor reset of the time recommended in
+     the SDRAM data sheet (typically 100-200 microseconds) until the following
+     code so that the SDRAM is ready for commands...
    */
 
-  /* SDRAM controller configured for Double-data rate (DDR) SDRAM 
-     Bus width = 16 bits 
-     SDRAM specification: 
-     SDRAM clock frequency = 80.00 MHz 
-     CASL = 2.5 
-     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds 
-     Write recovery time, tWR = 15.0 nanoseconds 
-     Precharge comand to ACTV command, tRP = 20.0 nanoseconds 
-     Auto refresh command period, tRFC = 75.0 nanoseconds 
-     Average periodic refresh interval, tREFI = 7.8 microseconds 
+  /* SDRAM controller configured for Double-data rate (DDR) SDRAM
+     Bus width = 16 bits
+     SDRAM specification:
+     SDRAM clock frequency = 80.00 MHz
+     CASL = 2.5
+     ACTV-to-read/write delay, tRCD = 20.0 nanoseconds
+     Write recovery time, tWR = 15.0 nanoseconds
+     Precharge comand to ACTV command, tRP = 20.0 nanoseconds
+     Auto refresh command period, tRFC = 75.0 nanoseconds
+     Average periodic refresh interval, tREFI = 7.8 microseconds
    */
 
-  /* Memory block 0 enabled - 32 MBytes at address $40000000 
-     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks) 
+  /* Memory block 0 enabled - 32 MBytes at address $40000000
+     Block consists of 1 device x 256 MBits (13 rows x 9 columns x 4 banks)
    */
   MCF_SDRAMC_SDCS0 = MCF_SDRAMC_SDCS_BASE(0x400) | MCF_SDRAMC_SDCS_CSSZ(0x18);
 
   /* Memory block 1 disabled */
   MCF_SDRAMC_SDCS1 = 0;
 
-  /* Initialise SDCFG1 register with delay and timing values 
-     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2 
-     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3 
+  /* Initialise SDCFG1 register with delay and timing values
+     SRD2RWP = 4, SWT2RWP = 3, RD_LAT = 7, ACT2RW = 2
+     PRE2ACT = 2, REF2ACT = 6, WT_LAT = 3
    */
   MCF_SDRAMC_SDCFG1 = MCF_SDRAMC_SDCFG1_SRD2RW(0x4) |
     MCF_SDRAMC_SDCFG1_SWT2RD(0x3) |
@@ -335,8 +335,8 @@ void init_sdram_controller(void)
     MCF_SDRAMC_SDCFG1_PRE2ACT(0x2) |
     MCF_SDRAMC_SDCFG1_REF2ACT(0x6) | MCF_SDRAMC_SDCFG1_WTLAT(0x3);
 
-  /* Initialise SDCFG2 register with delay and timing values 
-     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7 
+  /* Initialise SDCFG2 register with delay and timing values
+     BRD2RP = 5, BWT2RWP = 6, BRD2W = 6, BL = 7
    */
   MCF_SDRAMC_SDCFG2 = MCF_SDRAMC_SDCFG2_BRD2PRE(0x5) |
     MCF_SDRAMC_SDCFG2_BWT2RW(0x6) |
@@ -361,8 +361,8 @@ void init_sdram_controller(void)
   /* Issue a second Precharge All command */
   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IPALL;
 
-  /* Refresh sequence... 
-     (check the number of refreshes required by the SDRAM manufacturer) 
+  /* Refresh sequence...
+     (check the number of refreshes required by the SDRAM manufacturer)
    */
   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
   MCF_SDRAMC_SDCR |= MCF_SDRAMC_SDCR_IREF;
@@ -436,9 +436,9 @@ static void init_real_time_clock(void)
 **********************************************************************/
 static void init_watchdog_timers(void)
 {
-  /* Watchdog Timer disabled (WCR[EN]=0) 
-     NOTE: WCR and WMR cannot be written again until after the  
-     processor is reset. 
+  /* Watchdog Timer disabled (WCR[EN]=0)
+     NOTE: WCR and WMR cannot be written again until after the
+     processor is reset.
    */
   MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
   MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
@@ -563,34 +563,34 @@ static void init_interrupt_controller(void)
 **********************************************************************/
 static void init_pin_assignments(void)
 {
-  /* Pin assignments for port BUSCTL 
-     Pin BUSCTL3 : External bus output enable, /OE 
-     Pin BUSCTL2 : External bus transfer acknowledge, /TA 
-     Pin BUSCTL1 : External bus read/write, R/W 
-     Pin BUSCTL0 : External bus transfer start, /TS 
+  /* Pin assignments for port BUSCTL
+     Pin BUSCTL3 : External bus output enable, /OE
+     Pin BUSCTL2 : External bus transfer acknowledge, /TA
+     Pin BUSCTL1 : External bus read/write, R/W
+     Pin BUSCTL0 : External bus transfer start, /TS
    */
   MCF_GPIO_PDDR_BUSCTL = 0;
   MCF_GPIO_PAR_BUSCTL = MCF_GPIO_PAR_BUSCTL_PAR_OE |
     MCF_GPIO_PAR_BUSCTL_PAR_TA |
     MCF_GPIO_PAR_BUSCTL_PAR_RWB | MCF_GPIO_PAR_BUSCTL_PAR_TS(0x3);
 
-  /* Pin assignments for port BE 
-     Pin BE3 : External bus byte enable BW/BWE3 
-     Pin BE2 : External bus byte enable BW/BWE2 
-     Pin BE1 : External bus byte enable BW/BWE1 
-     Pin BE0 : External bus byte enable BW/BWE0 
+  /* Pin assignments for port BE
+     Pin BE3 : External bus byte enable BW/BWE3
+     Pin BE2 : External bus byte enable BW/BWE2
+     Pin BE1 : External bus byte enable BW/BWE1
+     Pin BE0 : External bus byte enable BW/BWE0
    */
   MCF_GPIO_PDDR_BE = 0;
   MCF_GPIO_PAR_BE = MCF_GPIO_PAR_BE_PAR_BE3 |
     MCF_GPIO_PAR_BE_PAR_BE2 |
     MCF_GPIO_PAR_BE_PAR_BE1 | MCF_GPIO_PAR_BE_PAR_BE0;
 
-  /* Pin assignments for port CS 
-     Pin CS5 : Flex bus chip select /FB_CS5 
-     Pin CS4 : Flex bus chip select /FB_CS4 
-     Pin CS3 : Flex bus chip select /FB_CS3 
-     Pin CS2 : Flex bus chip select /FB_CS2 
-     Pin CS1 : Flex bus chip select /FB_CS1 
+  /* Pin assignments for port CS
+     Pin CS5 : Flex bus chip select /FB_CS5
+     Pin CS4 : Flex bus chip select /FB_CS4
+     Pin CS3 : Flex bus chip select /FB_CS3
+     Pin CS2 : Flex bus chip select /FB_CS2
+     Pin CS1 : Flex bus chip select /FB_CS1
    */
   MCF_GPIO_PDDR_CS = 0;
   MCF_GPIO_PAR_CS = MCF_GPIO_PAR_CS_PAR_CS5 |
@@ -598,106 +598,106 @@ static void init_pin_assignments(void)
     MCF_GPIO_PAR_CS_PAR_CS3 |
     MCF_GPIO_PAR_CS_PAR_CS2 | MCF_GPIO_PAR_CS_PAR_CS1;
 
-  /* Pin assignments for port FECI2C 
-     Pin FECI2C3 : FEC management data clock, FEC_MDC 
-     Pin FECI2C2 : FEC management data, FEC_MDIO 
-     Pin FECI2C1 : GPIO input 
-     Pin FECI2C0 : GPIO input 
+  /* Pin assignments for port FECI2C
+     Pin FECI2C3 : FEC management data clock, FEC_MDC
+     Pin FECI2C2 : FEC management data, FEC_MDIO
+     Pin FECI2C1 : GPIO input
+     Pin FECI2C0 : GPIO input
    */
   MCF_GPIO_PDDR_FECI2C = 0;
   MCF_GPIO_PAR_FECI2C = MCF_GPIO_PAR_FECI2C_PAR_MDC(0x3) |
     MCF_GPIO_PAR_FECI2C_PAR_MDIO(0x3);
 
-  /* Pin assignments for ports FECH and FECL 
-     Pin FECH7 : FEC transmit clock, FEC_TXCLK 
-     Pin FECH6 : FEC transmit enable, FEC_TXEN 
-     Pin FECH5 : FEC transmit data 0, FEC_TXD0 
-     Pin FECH4 : FEC collision, FEC_COL 
-     Pin FECH3 : FEC receive clock, FEC_RXCLK 
-     Pin FECH2 : FEC receive data valid, FEC_RXDV 
-     Pin FECH1 : FEC receive data 0, FEC_RXD0 
-     Pin FECH0 : FEC carrier receive sense, FEC_CRS 
-     Pin FECL7 : FEC transmit data 3, FEC_TXD3 
-     Pin FECL6 : FEC transmit data 2, FEC_TXD2 
-     Pin FECL5 : FEC transmit data 1, FEC_TXD1 
-     Pin FECL4 : FEC transmit error, FEC_TXER 
-     Pin FECL3 : FEC receive data 3, FEX_RXD3 
-     Pin FECL2 : FEC receive data 2, FEX_RXD2 
-     Pin FECL1 : FEC receive data 1, FEX_RXD1 
-     Pin FECL0 : FEC receive error, FEC_RXER 
+  /* Pin assignments for ports FECH and FECL
+     Pin FECH7 : FEC transmit clock, FEC_TXCLK
+     Pin FECH6 : FEC transmit enable, FEC_TXEN
+     Pin FECH5 : FEC transmit data 0, FEC_TXD0
+     Pin FECH4 : FEC collision, FEC_COL
+     Pin FECH3 : FEC receive clock, FEC_RXCLK
+     Pin FECH2 : FEC receive data valid, FEC_RXDV
+     Pin FECH1 : FEC receive data 0, FEC_RXD0
+     Pin FECH0 : FEC carrier receive sense, FEC_CRS
+     Pin FECL7 : FEC transmit data 3, FEC_TXD3
+     Pin FECL6 : FEC transmit data 2, FEC_TXD2
+     Pin FECL5 : FEC transmit data 1, FEC_TXD1
+     Pin FECL4 : FEC transmit error, FEC_TXER
+     Pin FECL3 : FEC receive data 3, FEX_RXD3
+     Pin FECL2 : FEC receive data 2, FEX_RXD2
+     Pin FECL1 : FEC receive data 1, FEX_RXD1
+     Pin FECL0 : FEC receive error, FEC_RXER
    */
   MCF_GPIO_PDDR_FECH = 0;
   MCF_GPIO_PDDR_FECL = 0;
   MCF_GPIO_PAR_FEC = MCF_GPIO_PAR_FEC_PAR_FEC_7W(0x3) |
     MCF_GPIO_PAR_FEC_PAR_FEC_MII(0x3);
 
-  /* Pin assignments for port IRQ 
-     Pins are all used for EdgePort GPIO/IRQ 
+  /* Pin assignments for port IRQ
+     Pins are all used for EdgePort GPIO/IRQ
    */
   MCF_GPIO_PAR_IRQ = 0;
 
-  /* Pin assignments for port LCDDATAH 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port LCDDATAH
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_LCDDATAH = 0;
   MCF_GPIO_PAR_LCDDATA = 0;
 
-  /* Pin assignments for port LCDDATAM 
-     Port LCDDATAM pins are all GPIO inputs 
+  /* Pin assignments for port LCDDATAM
+     Port LCDDATAM pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_LCDDATAM = 0;
 
-  /* Pin assignments for port LCDDATAL 
-     Port LCDDATAL pins are all GPIO inputs 
+  /* Pin assignments for port LCDDATAL
+     Port LCDDATAL pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_LCDDATAL = 0;
 
-  /* Pin assignments for port LCDCTLH 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port LCDCTLH
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_LCDCTLH = 0;
   MCF_GPIO_PAR_LCDCTL = 0;
 
-  /* Pin assignments for port LCDCTLL 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port LCDCTLL
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_LCDCTLL = 0;
 
-  /* Pin assignments for port PWM 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port PWM
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_PWM = 0;
   MCF_GPIO_PAR_PWM = 0;
 
-  /* Pin assignments for port QSPI 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port QSPI
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_QSPI = 0;
   MCF_GPIO_PAR_QSPI = 0;
 
-  /* Pin assignments for port SSI 
-     Pins are all GPIO inputs 
+  /* Pin assignments for port SSI
+     Pins are all GPIO inputs
    */
   MCF_GPIO_PDDR_SSI = 0;
   MCF_GPIO_PAR_SSI = 0;
 
-  /* Pin assignments for port TIMER 
-     Pins are all GPIO outputs 
+  /* Pin assignments for port TIMER
+     Pins are all GPIO outputs
    */
   MCF_GPIO_PDDR_TIMER = MCF_GPIO_PDDR_TIMER_PDDR_TIMER3 |
     MCF_GPIO_PDDR_TIMER_PDDR_TIMER2 |
     MCF_GPIO_PDDR_TIMER_PDDR_TIMER1 | MCF_GPIO_PDDR_TIMER_PDDR_TIMER0;
   MCF_GPIO_PAR_TIMER = 0;
 
-  /* Pin assignments for port UART 
-     Pin UART7 : UART 1 clear-to-send, /U1CTS 
-     Pin UART6 : UART 1 request-to-send, /U1RTS 
-     Pin UART5 : UART 1 transmit data, U1TXD 
-     Pin UART4 : UART 1 receive data, U1RXD 
-     Pin UART3 : UART 0 clear-to-send, /U0CTS 
-     Pin UART2 : UART 0 request-to-send, /U0RTS 
-     Pin UART1 : UART 0 transmit data, U0TXD 
-     Pin UART0 : UART 0 receive data, U0RXD 
+  /* Pin assignments for port UART
+     Pin UART7 : UART 1 clear-to-send, /U1CTS
+     Pin UART6 : UART 1 request-to-send, /U1RTS
+     Pin UART5 : UART 1 transmit data, U1TXD
+     Pin UART4 : UART 1 receive data, U1RXD
+     Pin UART3 : UART 0 clear-to-send, /U0CTS
+     Pin UART2 : UART 0 request-to-send, /U0RTS
+     Pin UART1 : UART 0 transmit data, U0TXD
+     Pin UART0 : UART 0 receive data, U0RXD
    */
   MCF_GPIO_PDDR_UART = 0;
   MCF_GPIO_PAR_UART = MCF_GPIO_PAR_UART_PAR_UCTS1(0x3) |