2008-07-04 Matthew Riek <matthew.riek@ibiscomputer.com.au>

	* Makefile.am, README, include/coverhd.h, network/network.c,
	startup/bspstart.c, startup/cfinit.c, startup/linkcmdsflash: Add
	cache support for 5329. Fix bug in network driver. Enable the cache
	in copyback and write-through so we can assume that in BSP.

1 files changed, 281 insertions, 5 deletions

diff --git a/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c b/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
index c133bc4bf0..f6d0ba4553 100644
--- a/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
+++ b/c/src/lib/libbsp/m68k/mcf5329/startup/cfinit.c
@@ -3,15 +3,16 @@
 * Initialisation Code for ColdFire MCF5329 Processor                 *
 **********************************************************************
  Generated by ColdFire Initialisation Utility 2.10.8 
- Mon Jun 16 10:41:41 2008 
+ Wed Jul 02 14:26:25 2008 
    
  MicroAPL Ltd makes no warranties in respect of the suitability 
  of this code for any particular purpose, and accepts 
  no liability for any loss arising out of its use. The person or  
  persons making use of this file must make the final evaluation 
  as to its suitability and correctness for a particular application. 
-   
+
  $Id$
+   
 */
 
 /* External reference frequency is 16.0000 MHz 
@@ -37,19 +38,27 @@ static void disable_interrupts(void);
 static void disable_watchdog_timer(void);
 static void disable_cache(void);
 extern void init_clock_config(void) __attribute__ ((section(".ram_code")));
+static void init_vbr(void);
+static void init_cache(void);
+static void init_crossbar(void);
 extern void init_chip_selects(void) __attribute__ ((section(".ram_code")));
+static void init_eport(void);
+static void init_flexcan(void);
+static void init_dma_timers(void);
+static void init_interrupt_timers(void);
 static void init_real_time_clock(void);
 static void init_watchdog_timers(void);
+static void init_edma(void);
 static void init_pin_assignments(void);
-extern void init_sdram_controller(void)
+extern void init_sdram_controller(void) 
   __attribute__ ((section(".ram_code")));
+static void init_interrupt_controller(void);
 
 /*********************************************************************
 * init_main - Main entry point for initialisation code               *
 **********************************************************************/
 void init_main(void)
 {
-  /* Mask all interrupts */
   init_clock_config();
 
   /* Disable interrupts, watchdog timer, cache */
@@ -58,13 +67,23 @@ void init_main(void)
   disable_cache();
 
   /* Initialise individual modules */
+  init_cache();
+  init_crossbar();
   init_chip_selects();
+  init_eport();
+  init_flexcan();
+  init_dma_timers();
+  init_interrupt_timers();
   init_real_time_clock();
   init_watchdog_timers();
+  init_edma();
   init_pin_assignments();
 
   /* Initialise SDRAM controller (must be done after pin assignments) */
   init_sdram_controller();
+
+  /* Initialise interrupt controller */
+  init_interrupt_controller();
 }
 
 /*********************************************************************
@@ -107,7 +126,6 @@ static void disable_cache(void)
 /*********************************************************************
 * init_clock_config - Clock Module                                   *
 **********************************************************************/
-
 void init_clock_config(void)
 {
   /* Clock module uses normal PLL mode with 16.0000 MHz external reference 
@@ -154,22 +172,124 @@ void init_clock_config(void)
 }
 
 /*********************************************************************
+* init_cache - Unified (Instruction and Data) Cache                  *
+**********************************************************************/
+static void init_cache(void)
+{
+  /* ACR0: Cache accesses to 32 MB memory region at address $40000000 
+     CACR: Don't cache accesses to the rest of memory 
+   */
+  /*
+   * Cache is enabled in bspstart.c
+   */
+#if 0
+  asm("move.l   #0xa0000600,%d0");
+  asm("movec    %d0,%CACR");
+#endif  
+  asm("move.l   #0x4001c020,%d0");
+  asm("movec    %d0,%ACR0");
+  asm("move.l   #0x00000000,%d0");
+  asm("movec    %d0,%ACR1");
+}
+
+/*********************************************************************
+* init_crossbar - Cross-Bar Switch (XBS) Module                      *
+**********************************************************************/
+static void init_crossbar(void)
+{
+  /* XBS settings for FlexBus/SDRAM Controller slave:  
+     Fixed priority (Core, LCD, eDMA, FEC, USB Host, USB OTG), park on ColdFire Core 
+   */
+  MCF_XBS_PRS1 = MCF_XBS_PRS_M6(0x5) |
+    MCF_XBS_PRS_M5(0x4) |
+    MCF_XBS_PRS_M4(0x1) | MCF_XBS_PRS_M2(0x3) | MCF_XBS_PRS_M1(0x2);
+  MCF_XBS_CRS1 = 0;
+
+  /* XBS settings for SRAM Backdoor slave:  
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+   */
+  MCF_XBS_PRS4 = MCF_XBS_PRS_M6(0x5) |
+    MCF_XBS_PRS_M5(0x4) |
+    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
+  MCF_XBS_CRS4 = 0;
+
+  /* XBS settings for Cryptography Modules slave:  
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+   */
+  MCF_XBS_PRS6 = MCF_XBS_PRS_M6(0x5) |
+    MCF_XBS_PRS_M5(0x4) |
+    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
+  MCF_XBS_CRS6 = 0;
+
+  /* XBS settings for On-chip Peripherals slave:  
+     Fixed priority (Core, eDMA, FEC, LCD, USB Host, USB OTG), park on ColdFire Core 
+   */
+  MCF_XBS_PRS7 = MCF_XBS_PRS_M6(0x5) |
+    MCF_XBS_PRS_M5(0x4) |
+    MCF_XBS_PRS_M4(0x3) | MCF_XBS_PRS_M2(0x2) | MCF_XBS_PRS_M1(0x1);
+  MCF_XBS_CRS7 = 0;
+}
+
+/*********************************************************************
 * init_chip_selects - Chip Select Module (FlexBus)                   *
 **********************************************************************/
 void init_chip_selects(void)
 {
+  /* Chip Select 1 disabled (CSMR1[V] = 0) */
+  MCF_FBCS1_CSMR = 0;
+
+  /* Chip Select 2 disabled (CSMR2[V] = 0) */
+  MCF_FBCS2_CSMR = 0;
+
+  /* Chip Select 3 disabled (CSMR3[V] = 0) */
+  MCF_FBCS3_CSMR = 0;
+
+  /* Chip Select 4 disabled (CSMR4[V] = 0) */
+  MCF_FBCS4_CSMR = 0;
+
+  /* Chip Select 5 disabled (CSMR5[V] = 0) */
+  MCF_FBCS5_CSMR = 0;
+
   /* Chip Select 0: 2 MB of Flash at base address $00000000 
      Port size = 16 bits 
      Assert chip select on first rising clock edge after address is asserted 
      Generate internal transfer acknowledge after 7 wait states 
      Address is held for 1 clock at end of read and write cycles 
    */
+  MCF_FBCS0_CSAR = 0;
   MCF_FBCS0_CSCR = MCF_FBCS_CSCR_WS(0x7) |
     (0x1 << 9) | MCF_FBCS_CSCR_AA | MCF_FBCS_CSCR_PS(0x2) | MCF_FBCS_CSCR_BEM;
   MCF_FBCS0_CSMR = MCF_FBCS_CSMR_BAM(0x1f) | MCF_FBCS_CSMR_V;
 }
 
 /*********************************************************************
+* init_eport - Edge Port Module (EPORT)                              *
+**********************************************************************/
+static void init_eport(void)
+{
+  /* Pins 1-7 configured as GPIO inputs */
+  MCF_EPORT_EPPAR = 0;
+  MCF_EPORT_EPDDR = 0;
+  MCF_EPORT_EPIER = 0;
+}
+
+/*********************************************************************
+* init_flexcan - FlexCAN Module                                      *
+**********************************************************************/
+static void init_flexcan(void)
+{
+  /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
+  MCF_CAN_IMASK = 0;
+  MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
+  MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
+  MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
+  MCF_CAN_CANCTRL = 0;
+  MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
+    MCF_CAN_CANMCR_FRZ |
+    MCF_CAN_CANMCR_HALT | MCF_CAN_CANMCR_SUPV | MCF_CAN_CANMCR_MAXMB(0xf);
+}
+
+/*********************************************************************
 * init_sdram_controller - SDRAM Controller                           *
 **********************************************************************/
 void init_sdram_controller(void)
@@ -260,6 +380,50 @@ void init_sdram_controller(void)
 }
 
 /*********************************************************************
+* init_dma_timers - DMA Timers                                       *
+**********************************************************************/
+static void init_dma_timers(void)
+{
+  /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
+  MCF_DTIM0_DTMR = 0;
+  MCF_DTIM0_DTXMR = 0;
+  MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+  /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
+  MCF_DTIM1_DTMR = 0;
+  MCF_DTIM1_DTXMR = 0;
+  MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+  /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
+  MCF_DTIM2_DTMR = 0;
+  MCF_DTIM2_DTXMR = 0;
+  MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+  /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
+  MCF_DTIM3_DTMR = 0;
+  MCF_DTIM3_DTXMR = 0;
+  MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+}
+
+/*********************************************************************
+* init_interrupt_timers - Programmable Interrupt Timers (PIT)        *
+**********************************************************************/
+static void init_interrupt_timers(void)
+{
+  /* PIT0 disabled (PCSR0[EN]=0) */
+  MCF_PIT0_PCSR = 0;
+
+  /* PIT1 disabled (PCSR1[EN]=0) */
+  MCF_PIT1_PCSR = 0;
+
+  /* PIT2 disabled (PCSR2[EN]=0) */
+  MCF_PIT2_PCSR = 0;
+
+  /* PIT3 disabled (PCSR3[EN]=0) */
+  MCF_PIT3_PCSR = 0;
+}
+
+/*********************************************************************
 * init_real_time_clock - Real-Time Clock (RTC)                       *
 **********************************************************************/
 static void init_real_time_clock(void)
@@ -278,12 +442,124 @@ static void init_watchdog_timers(void)
      processor is reset. 
    */
   MCF_WTM_WCR = MCF_WTM_WCR_WAIT | MCF_WTM_WCR_DOZE | MCF_WTM_WCR_HALTED;
+  MCF_WTM_WMR = MCF_WTM_WMR_WM(0xffff);
 
   /* Core watchdog timer disabled */
   MCF_SCM_CWCR = MCF_SCM_CWCR_CWT(0x8);
 }
 
 /*********************************************************************
+* init_edma - eDMA Controller                                        *
+**********************************************************************/
+static void init_edma(void)
+{
+  /* Associate eDMA channels 9-12 with SSI signals */
+  MCF_CCM_MISCCR &= ~MCF_CCM_MISCCR_TIM_DMA;
+
+  /* Configured for round-robin arbitration mode */
+  MCF_EDMA_CR = MCF_EDMA_CR_ERCA;
+
+  /* All error interrupts are disabled */
+  MCF_EDMA_EEI = 0;
+
+  /* All DMA requests from peripherals are masked */
+  MCF_EDMA_ERQ = 0;
+}
+
+/*********************************************************************
+* init_interrupt_controller - Interrupt Controller                   *
+**********************************************************************/
+static void init_interrupt_controller(void)
+{
+  /* No interrupt sources configured */
+  MCF_INTC1_ICR0 = 0;
+  MCF_INTC1_ICR1 = 0;
+  MCF_INTC1_ICR3 = 0;
+  MCF_INTC1_ICR4 = 0;
+  MCF_INTC1_ICR5 = 0;
+  MCF_INTC1_ICR6 = 0;
+  MCF_INTC1_ICR7 = 0;
+  MCF_INTC1_ICR8 = 0;
+  MCF_INTC1_ICR9 = 0;
+  MCF_INTC1_ICR10 = 0;
+  MCF_INTC1_ICR11 = 0;
+  MCF_INTC1_ICR12 = 0;
+  MCF_INTC1_ICR13 = 0;
+  MCF_INTC1_ICR14 = 0;
+  MCF_INTC1_ICR15 = 0;
+  MCF_INTC1_ICR16 = 0;
+  MCF_INTC1_ICR17 = 0;
+  MCF_INTC1_ICR18 = 0;
+  MCF_INTC1_ICR19 = 0;
+  MCF_INTC1_ICR40 = 0;
+  MCF_INTC1_ICR41 = 0;
+  MCF_INTC1_ICR42 = 0;
+  MCF_INTC1_ICR43 = 0;
+  MCF_INTC1_ICR44 = 0;
+  MCF_INTC1_ICR45 = 0;
+  MCF_INTC1_ICR46 = 0;
+  MCF_INTC1_ICR47 = 0;
+  MCF_INTC1_ICR48 = 0;
+  MCF_INTC1_ICR49 = 0;
+  MCF_INTC1_ICR50 = 0;
+  MCF_INTC1_ICR51 = 0;
+  MCF_INTC1_ICR52 = 0;
+  MCF_INTC1_ICR53 = 0;
+  MCF_INTC0_ICR1 = 0;
+  MCF_INTC0_ICR2 = 0;
+  MCF_INTC0_ICR3 = 0;
+  MCF_INTC0_ICR4 = 0;
+  MCF_INTC0_ICR5 = 0;
+  MCF_INTC0_ICR6 = 0;
+  MCF_INTC0_ICR7 = 0;
+  MCF_INTC0_ICR8 = 0;
+  MCF_INTC0_ICR9 = 0;
+  MCF_INTC0_ICR10 = 0;
+  MCF_INTC0_ICR11 = 0;
+  MCF_INTC0_ICR12 = 0;
+  MCF_INTC0_ICR13 = 0;
+  MCF_INTC0_ICR14 = 0;
+  MCF_INTC0_ICR15 = 0;
+  MCF_INTC0_ICR16 = 0;
+  MCF_INTC0_ICR17 = 0;
+  MCF_INTC0_ICR18 = 0;
+  MCF_INTC0_ICR19 = 0;
+  MCF_INTC0_ICR20 = 0;
+  MCF_INTC0_ICR21 = 0;
+  MCF_INTC0_ICR22 = 0;
+  MCF_INTC0_ICR23 = 0;
+  MCF_INTC0_ICR24 = 0;
+  MCF_INTC0_ICR25 = 0;
+  MCF_INTC0_ICR26 = 0;
+  MCF_INTC0_ICR27 = 0;
+  MCF_INTC0_ICR28 = 0;
+  MCF_INTC0_ICR30 = 0;
+  MCF_INTC0_ICR31 = 0;
+  MCF_INTC0_ICR32 = 0;
+  MCF_INTC0_ICR33 = 0;
+  MCF_INTC0_ICR34 = 0;
+  MCF_INTC0_ICR35 = 0;
+  MCF_INTC0_ICR36 = 0;
+  MCF_INTC0_ICR37 = 0;
+  MCF_INTC0_ICR38 = 0;
+  MCF_INTC0_ICR39 = 0;
+  MCF_INTC0_ICR40 = 0;
+  MCF_INTC0_ICR41 = 0;
+  MCF_INTC0_ICR42 = 0;
+  MCF_INTC0_ICR43 = 0;
+  MCF_INTC0_ICR44 = 0;
+  MCF_INTC0_ICR45 = 0;
+  MCF_INTC0_ICR46 = 0;
+  MCF_INTC0_ICR47 = 0;
+  MCF_INTC0_ICR48 = 0;
+  MCF_INTC0_ICR62 = 0;
+  MCF_INTC0_IMRH = 0xffffffff;
+  MCF_INTC0_IMRL = 0xffffffff;
+  MCF_INTC1_IMRH = 0xffffffff;
+  MCF_INTC1_IMRL = 0xffffffff;
+}
+
+/*********************************************************************
 * init_pin_assignments - Pin Assignment and General Purpose I/O      *
 **********************************************************************/
 static void init_pin_assignments(void)