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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-26 21:20:33 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2007-11-26 21:20:33 +0000 |
| commit | 1693c131a19f6c23ae95e33161119e48239dc165 (patch) | |
| tree | 84b6b5ef076a1e62d431b8c4e8b4a7e5609e433b /c/src/lib/libbsp/m68k/mcf5235 | |
| parent | 2007-11-26 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-1693c131a19f6c23ae95e33161119e48239dc165.tar.bz2 | |
2007-11-26 Joel Sherrill <joel.sherrill@oarcorp.com>
* startup/bspstart.c: Eliminate the interrupt_vector_table field in the
m68k CPU Table since it is never read.
Diffstat (limited to 'c/src/lib/libbsp/m68k/mcf5235')
| -rw-r--r-- | c/src/lib/libbsp/m68k/mcf5235/ChangeLog | 5 | ||||
| -rw-r--r-- | c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c | 42 |
2 files changed, 25 insertions, 22 deletions
diff --git a/c/src/lib/libbsp/m68k/mcf5235/ChangeLog b/c/src/lib/libbsp/m68k/mcf5235/ChangeLog index dd792956cb..17f1f61cde 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/ChangeLog +++ b/c/src/lib/libbsp/m68k/mcf5235/ChangeLog @@ -1,3 +1,8 @@ +2007-11-26 Joel Sherrill <joel.sherrill@oarcorp.com> + + * startup/bspstart.c: Eliminate the interrupt_vector_table field in the + m68k CPU Table since it is never read. + 2007-05-03 Joel Sherrill <joel@OARcorp.com> * startup/linkcmds: Handle .data.* sections diff --git a/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c b/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c index 5b826f737a..c6b223bf56 100644 --- a/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mcf5235/startup/bspstart.c @@ -185,33 +185,31 @@ void bsp_start( void ) Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ Cpu_table.postdriver_hook = bsp_postdriver_hook; Cpu_table.interrupt_stack_size = 4096; - Cpu_table.interrupt_vector_table = (m68k_isr *)0; /* vectors at start of RAM */ - /* - * Invalidate the cache and disable it - */ - m68k_set_acr0(0); - m68k_set_acr1(0); - m68k_set_cacr(MCF5XXX_CACR_CINV); - - /* - * Cache SDRAM - */ - m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | - MCF5XXX_ACR_AM(SDRAM_SIZE-1) | - MCF5XXX_ACR_EN | - MCF5XXX_ACR_BWE | - MCF5XXX_ACR_SM_IGNORE); + /* + * Invalidate the cache and disable it + */ + m68k_set_acr0(0); + m68k_set_acr1(0); + m68k_set_cacr(MCF5XXX_CACR_CINV); - /* - * Enable the cache - */ - m68k_set_cacr(cacr_mode); + /* + * Cache SDRAM + */ + m68k_set_acr0(MCF5XXX_ACR_AB(SDRAM_BASE) | + MCF5XXX_ACR_AM(SDRAM_SIZE-1) | + MCF5XXX_ACR_EN | + MCF5XXX_ACR_BWE | + MCF5XXX_ACR_SM_IGNORE); + /* + * Enable the cache + */ + m68k_set_cacr(cacr_mode); } uint32_t get_CPU_clock_speed(void) { - extern char _CPUClockSpeed[]; - return( (uint32_t)_CPUClockSpeed); + extern char _CPUClockSpeed[]; + return( (uint32_t)_CPUClockSpeed); } |