diff options
| author | Chris Johns <chrisj@rtems.org> | 2008-06-11 07:59:03 +0000 |
|---|---|---|
| committer | Chris Johns <chrisj@rtems.org> | 2008-06-11 07:59:03 +0000 |
| commit | 3aac2db317370181538abb2b3504a97d226dfe3f (patch) | |
| tree | 2820a4b2736b1b1890324aeadffb2d70cf822143 /c/src/lib/libbsp/m68k/mcf52235 | |
| parent | 2008-06-10 Joel Sherrill <joel.sherrill@oarcorp.com> (diff) | |
| download | rtems-3aac2db317370181538abb2b3504a97d226dfe3f.tar.bz2 | |
2008-06-10 Matthew Riek <matthew.riek@ibiscomputer.com.au>
* .cvsignore, ChangeLog, Makefile.am, README, bsp_specs,
clock/clock.c, configure.ac, console/console.c, gdb-init,
include/bsp.h, include/bspopts.h.in, include/coverhd.h,
include/tm27.h, preinstall.am, start/start.S, startup/bspclean.c,
startup/bspstart.c, startup/cfinit.c, startup/init52235.c,
startup/linkcmds, timer/timer.c: New.
Diffstat (limited to 'c/src/lib/libbsp/m68k/mcf52235')
21 files changed, 3034 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/m68k/mcf52235/.cvsignore b/c/src/lib/libbsp/m68k/mcf52235/.cvsignore new file mode 100644 index 0000000000..bfdfd995be --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/.cvsignore @@ -0,0 +1,14 @@ +aclocal.m4 +autom4te*.cache +config.cache +config.guess +config.log +config.status +config.sub +configure +depcomp +install-sh +Makefile +Makefile.in +missing +mkinstalldirs diff --git a/c/src/lib/libbsp/m68k/mcf52235/ChangeLog b/c/src/lib/libbsp/m68k/mcf52235/ChangeLog new file mode 100644 index 0000000000..9745b63614 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/ChangeLog @@ -0,0 +1,8 @@ +2008-06-10 Matthew Riek <matthew.riek@ibiscomputer.com.au> + + * .cvsignore, ChangeLog, Makefile.am, README, bsp_specs, + clock/clock.c, configure.ac, console/console.c, gdb-init, + include/bsp.h, include/bspopts.h.in, include/coverhd.h, + include/tm27.h, preinstall.am, start/start.S, startup/bspclean.c, + startup/bspstart.c, startup/cfinit.c, startup/init52235.c, + startup/linkcmds, timer/timer.c: New. diff --git a/c/src/lib/libbsp/m68k/mcf52235/Makefile.am b/c/src/lib/libbsp/m68k/mcf52235/Makefile.am new file mode 100644 index 0000000000..468ebbb2b9 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/Makefile.am @@ -0,0 +1,61 @@ +## +## $Id$ +## + +ACLOCAL_AMFLAGS = -I ../../../../aclocal + +include $(top_srcdir)/../../../../automake/compile.am +include $(top_srcdir)/../../bsp.am + +dist_project_lib_DATA = bsp_specs + +include_HEADERS = include/bsp.h +include_HEADERS += include/tm27.h + +nodist_include_HEADERS = include/bspopts.h +DISTCLEANFILES = include/bspopts.h +noinst_PROGRAMS = + +include_HEADERS += include/coverhd.h + +EXTRA_DIST = start/start.S +start.$(OBJEXT): start/start.S + $(CPPASCOMPILE) -o $@ -c $< +project_lib_DATA = start.$(OBJEXT) + +dist_project_lib_DATA += startup/linkcmds + +startup_SOURCES = startup/bspclean.c ../../shared/bsppredriverhook.c \ + ../../shared/bsplibc.c ../../shared/bsppost.c \ + ../../m68k/shared/m68kpretaskinghook.c \ + ../../m68k/shared/m68kbspgetworkarea.c \ + startup/init52235.c startup/bspstart.c startup/cfinit.c\ + ../../shared/bootcard.c \ + ../../shared/sbrk.c ../../m68k/shared/setvec.c \ + ../../shared/gnatinstallhandler.c +clock_SOURCES = clock/clock.c +console_SOURCES = console/console.c +timer_SOURCES = timer/timer.c + +#if HAS_NETWORKING +#network_CPPFLAGS = -D__INSIDE_RTEMS_BSD_TCPIP_STACK__ +#noinst_PROGRAMS += network.rel +#network_rel_SOURCES = network/network.c +#network_rel_CPPFLAGS = $(AM_CPPFLAGS) \ +# $(network_CPPFLAGS) +#network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) +#endif + +noinst_LIBRARIES = libbsp.a +libbsp_a_SOURCES = $(startup_SOURCES) $(clock_SOURCES) $(console_SOURCES) \ + $(timer_SOURCES) + +libbsp_a_LIBADD = \ + ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ + ../../../libcpu/@RTEMS_CPU@/shared/misc.rel +#if HAS_NETWORKING +#libbsp_a_LIBADD += network.rel +#endif + +include $(srcdir)/preinstall.am +include $(top_srcdir)/../../../../automake/local.am diff --git a/c/src/lib/libbsp/m68k/mcf52235/README b/c/src/lib/libbsp/m68k/mcf52235/README new file mode 100644 index 0000000000..b52aa5de91 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/README @@ -0,0 +1,56 @@ +# +# $Id: +# + +Description: Motorola MCF52235EVB +============ +CPU: MCF52235, 60MHz +SRAM: 32K +FLASH: 256K + +This is a Motorola evaluation board that uses the MCF52235 Coldfire CPU. +This board is running at 60MHz scaled from a 25MHz oscillator. + +NOTES: +====== + +Currently this BSP must be configured with most (all?) RTEMS features turned +off as RAM usage is too high. + +Configure as follows: +configure --target=m68k-rtems4.9 --enable-rtemsbsp=mcf52235 \ + --disable-networking --disable-posix --disable-itron --disable-cxx \ + --disable-tests + +TODO: +===== + +*) Work with TINY RTEMS to get the ram usage down. +*) Add drivers for I2C, ADC, FEC +*) Support for LWIP +*) Update the coverhd.h (calling overheads) page 21 of the BSP guide +*) Adjust initial stack so that it's space is not forever unusable after init +*) Fix up constants used by cfinit such as clockspeed, rambase, flashbase etc. + +============================================================================ + Interrupt map + ++-----+-----------------------------------------------------------------------+ +| | PRIORITY | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +|LEVEL| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 7 | | | | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 6 | | | | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 5 | | | | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 4 | FEC RX | FEC TX | | | | | | PIT | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 3 | UART 0 | UART 1 | UART 2 | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 2 | | | | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ +| 1 | | | | | | | | | ++-----+--------+--------+--------+--------+--------+--------+--------+--------+ diff --git a/c/src/lib/libbsp/m68k/mcf52235/bsp_specs b/c/src/lib/libbsp/m68k/mcf52235/bsp_specs new file mode 100644 index 0000000000..4a5560b651 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e start} + +*endfile: +%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s} diff --git a/c/src/lib/libbsp/m68k/mcf52235/clock/clock.c b/c/src/lib/libbsp/m68k/mcf52235/clock/clock.c new file mode 100644 index 0000000000..9e7b3dd346 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/clock/clock.c @@ -0,0 +1,96 @@ +/* + * Use the last periodic interval timer (PIT2) as the system clock. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> + +/* + * Use INTC0 base + */ +#define CLOCK_VECTOR (64+56) + +static uint32_t s_pcntrAtTick = 0; +static uint32_t s_nanoScale = 0; + +/* + * Provide nanosecond extension + */ +static uint32_t bsp_clock_nanoseconds_since_last_tick(void) +{ + uint32_t i = MCF_PIT1_PCNTR; + if(MCF_PIT1_PCSR & MCF_PIT_PCSR_PIF) + { + i = MCF_PIT1_PCNTR + MCF_PIT1_PMR; + } + return (i - s_pcntrAtTick) * s_nanoScale; +} + +#define Clock_driver_nanoseconds_since_last_tick bsp_clock_nanoseconds_since_last_tick + +/* + * Periodic interval timer interrupt handler + */ +#define Clock_driver_support_at_tick() \ + do { \ + s_pcntrAtTick = MCF_PIT1_PCNTR; \ + MCF_PIT1_PCSR |= MCF_PIT_PCSR_PIF; \ + } while (0) \ + +/* + * Attach clock interrupt handler + */ +#define Clock_driver_support_install_isr( _new, _old ) \ + do { \ + _old = (rtems_isr_entry)set_vector(_new, CLOCK_VECTOR, 1); \ + } while(0) + +/* + * Turn off the clock + */ +static void Clock_driver_support_shutdown_hardware() +{ + MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; +} + +/* + * Set up the clock hardware + * + * We need to have 1 interrupt every BSP_Configuration.microseconds_per_tick + */ +static void Clock_driver_support_initialize_hardware() +{ + int level; + uint32_t pmr; + uint32_t preScaleCode = 0; + uint32_t clk = bsp_get_CPU_clock_speed() >> 1; + uint32_t tps = 1000000 / Configuration.microseconds_per_tick; + while (preScaleCode < 15) { + pmr = (clk >> preScaleCode) / tps; + if(pmr < (1 << 15)) break; + preScaleCode++; + } + s_nanoScale = 1000000000 / (clk >> preScaleCode); + + MCF_INTC0_ICR56 = MCF_INTC_ICR_IL(PIT3_IRQ_LEVEL) | + MCF_INTC_ICR_IP(PIT3_IRQ_PRIORITY); + rtems_interrupt_disable( level ); + MCF_INTC0_IMRH &= ~MCF_INTC_IMRH_MASK56; + MCF_PIT1_PCSR &= ~MCF_PIT_PCSR_EN; + rtems_interrupt_enable( level ); + + MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | + MCF_PIT_PCSR_OVW | + MCF_PIT_PCSR_PIE | + MCF_PIT_PCSR_RLD; + MCF_PIT1_PMR = pmr; + MCF_PIT1_PCSR = MCF_PIT_PCSR_PRE(preScaleCode) | + MCF_PIT_PCSR_PIE | + MCF_PIT_PCSR_RLD | + MCF_PIT_PCSR_EN; + s_pcntrAtTick = MCF_PIT1_PCNTR; +} + +#include "../../../shared/clockdrv_shell.c" diff --git a/c/src/lib/libbsp/m68k/mcf52235/configure.ac b/c/src/lib/libbsp/m68k/mcf52235/configure.ac new file mode 100644 index 0000000000..3d888777c9 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/configure.ac @@ -0,0 +1,25 @@ +## Process this file with autoconf to produce a configure script. +## +## $Id$ + +AC_PREREQ(2.60) +AC_INIT([rtems-c-src-lib-libbsp-m68k-mcf52235],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.10]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_BSP_BOOTCARD_HANDLES_RAM_ALLOCATION + +#RTEMS_CHECK_NETWORKING +#AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") + +# Explicitly list all Makefiles here +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT diff --git a/c/src/lib/libbsp/m68k/mcf52235/console/console.c b/c/src/lib/libbsp/m68k/mcf52235/console/console.c new file mode 100644 index 0000000000..eee826847f --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/console/console.c @@ -0,0 +1,768 @@ + /* + * Multi UART console serial I/O. + * + * TO DO: Add DMA input/output + */ + +#include <stdio.h> +#include <fcntl.h> +#include <rtems/libio.h> +#include <rtems/termiostypes.h> +#include <termios.h> +#include <bsp.h> +#include <malloc.h> +#include <rtems/mw_uid.h> + +#include <rtems/bspIo.h> + +#define UART_INTC0_IRQ_VECTOR(x) (64+13+(x)) + +#define MCF_UART_USR_ERROR ( MCF_UART_USR_RB | \ + MCF_UART_USR_FE | \ + MCF_UART_USR_PE | \ + MCF_UART_USR_OE ) + +static int IntUartPollWrite(int minor, const char *buf, int len); +static int IntUartInterruptWrite (int minor, const char *buf, int len); + +static void +_BSP_null_char( char c ) +{ + int level; + + if (c == '\n') + _BSP_null_char('\r'); + rtems_interrupt_disable(level); + while ( (MCF_UART_USR(CONSOLE_PORT) & MCF_UART_USR_TXRDY) == 0 ) + continue; + MCF_UART_UTB(CONSOLE_PORT) = c; + while ( (MCF_UART_USR(CONSOLE_PORT) & MCF_UART_USR_TXRDY) == 0 ) + continue; + rtems_interrupt_enable(level); +} +BSP_output_char_function_type BSP_output_char = _BSP_null_char; + +#define MAX_UART_INFO 3 +#define RX_BUFFER_SIZE 512 + +struct IntUartInfoStruct +{ + int iomode; + volatile int uimr; + int baud; + int databits; + int parity; + int stopbits; + int hwflow; + int rx_in; + int rx_out; + char rx_buffer[RX_BUFFER_SIZE]; + void *ttyp; +}; + +struct IntUartInfoStruct IntUartInfo[MAX_UART_INFO]; + +/*************************************************************************** + Function : IntUartSet + + Description : This updates the hardware UART settings. + ***************************************************************************/ +static void +IntUartSet(int minor, int baud, int databits, int parity, int stopbits, int hwflow) +{ + int divisor; + uint32_t clock_speed; + uint8_t umr1 = 0; + uint8_t umr2 = 0; + struct IntUartInfoStruct *info = &IntUartInfo[minor]; + int level; + + rtems_interrupt_disable(level); + + + /* disable interrupts, clear RTS line, and disable the UARTS */ + MCF_UART_UIMR(minor) = 0; + MCF_UART_UOP0(minor) = 1; + MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_DISABLED | MCF_UART_UCR_RX_DISABLED); + + /* save the current values */ + info->uimr = 0; + info->baud = baud; + info->databits = databits; + info->parity = parity; + info->stopbits = stopbits; + info->hwflow = hwflow; + + clock_speed = bsp_get_CPU_clock_speed(); + /* determine the baud divisor value */ + // MRTODO + //divisor = ((clock_speed/2) / ( 32 * baud )); + divisor = ((clock_speed) / ( 32 * baud )); + if ( divisor < 2 ) + divisor = 2; + + /* check to see if doing hardware flow control */ + if ( hwflow ) + { + /* set hardware flow options */ + umr1 |= MCF_UART_UMR_RXRTS; + umr2 |= MCF_UART_UMR_TXCTS; + } + + /* determine the new umr values */ + umr1 |= (parity | databits); + umr2 |= (stopbits); + + /* reset the uart */ + MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_ERROR; + MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_RX; + MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_TX; + + /* reset the uart mode register and update values */ + MCF_UART_UCR(minor) = MCF_UART_UCR_RESET_MR; + MCF_UART_UMR(minor) = umr1; + MCF_UART_UMR(minor) = umr2; + + /* set the baud rate values */ + MCF_UART_UCSR(minor) = (MCF_UART_UCSR_RCS_SYS_CLK | MCF_UART_UCSR_TCS_SYS_CLK); + MCF_UART_UBG1(minor) = (divisor & 0xff00) >> 8; + MCF_UART_UBG2(minor) = (divisor & 0x00ff); + + /* enable the uart */ + MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_ENABLED | MCF_UART_UCR_RX_ENABLED); + + /* check to see if interrupts need to be enabled */ + if ( info->iomode != TERMIOS_POLLED ) + { + /* enable rx interrupts */ + info->uimr |= MCF_UART_UIMR_RXRDY_FU; + MCF_UART_UIMR(minor) = info->uimr; + } + + /* check to see if doing hardware flow control */ + if ( hwflow ) + { + /* assert the RTS line */ + MCF_UART_UOP1(minor) = 1; + } + + rtems_interrupt_enable(level); + +} + + +/*************************************************************************** + Function : IntUartSetAttributes + + Description : This provides the hardware-dependent portion of tcsetattr(). + value and sets it. At the moment this just sets the baud rate. + + Note: The highest baudrate is 115200 as this stays within + an error of +/- 5% at 25MHz processor clock + ***************************************************************************/ +static int +IntUartSetAttributes(int minor, const struct termios *t) +{ + /* set default index values */ + int baud = (int)19200; + int databits = (int)MCF_UART_UMR_BC_8; + int parity = (int)MCF_UART_UMR_PM_NONE; + int stopbits = (int)MCF_UART_UMR_SB_STOP_BITS_1; + int hwflow = (int)0; + struct IntUartInfoStruct *info = &IntUartInfo[minor]; + + /* check to see if input is valid */ + if ( t != (const struct termios *)0 ) + { + /* determine baud rate index */ + baud = termios_baud_to_number(t->c_cflag & CBAUD); + + /* determine data bits */ + switch ( t->c_cflag & CSIZE ) + { + case CS5: + databits = (int)MCF_UART_UMR_BC_5; + break; + case CS6: + databits = (int)MCF_UART_UMR_BC_6; + break; + case CS7: + databits = (int)MCF_UART_UMR_BC_7; + break; + case CS8: + databits = (int)MCF_UART_UMR_BC_8; + break; + } + + /* determine if parity is enabled */ + if ( t->c_cflag & PARENB ) + { + if ( t->c_cflag & PARODD ) + { + /* odd parity */ + parity = (int)MCF_UART_UMR_PM_ODD; + } + else + { + /* even parity */ + parity = (int)MCF_UART_UMR_PM_EVEN; + } + } + + /* determine stop bits */ + if ( t->c_cflag & CSTOPB ) + { + /* two stop bits */ + stopbits = (int)MCF_UART_UMR_SB_STOP_BITS_2; + } + + /* check to see if hardware flow control */ + if ( t->c_cflag & CRTSCTS ) + { + hwflow = 1; + } + } + + /* check to see if values have changed */ + if ( ( baud != info->baud ) || + ( databits != info->databits ) || + ( parity != info->parity ) || + ( stopbits != info->stopbits ) || + ( hwflow != info->hwflow ) ) + { + + /* call function to set values */ + IntUartSet(minor, baud, databits, parity, stopbits, hwflow); + } + + return( RTEMS_SUCCESSFUL ); + +} + +/*************************************************************************** + Function : IntUartInterruptHandler + + Description : This is the interrupt handler for the internal uart. It + determines which channel caused the interrupt before queueing any received + chars and dequeueing chars waiting for transmission. + ***************************************************************************/ +static rtems_isr +IntUartInterruptHandler(rtems_vector_number v) +{ + unsigned int chan = v - UART_INTC0_IRQ_VECTOR(0); + struct IntUartInfoStruct *info = &IntUartInfo[chan]; + + /* check to see if received data */ + if ( MCF_UART_UISR(chan) & MCF_UART_UISR_RXRDY_FU ) + { + /* read data and put into the receive buffer */ + while ( MCF_UART_USR(chan) & MCF_UART_USR_RXRDY ) + { + + if ( MCF_UART_USR(chan) & MCF_UART_USR_ERROR ) + { + /* clear the error */ + MCF_UART_UCR(chan) = MCF_UART_UCR_RESET_ERROR; + } + /* put data in rx buffer and check for errors */ + info->rx_buffer[info->rx_in] = MCF_UART_URB(chan); + + /* update buffer values */ + info->rx_in++; + + if ( info->rx_in >= RX_BUFFER_SIZE ) + { + info->rx_in = 0; + } + } + /* Make sure the port has been opened */ + if ( info->ttyp ) + { + + /* check to see if task driven */ + if ( info->iomode == TERMIOS_TASK_DRIVEN ) + { + /* notify rx task that rx buffer has data */ + rtems_termios_rxirq_occured(info->ttyp); + } + else + { + /* Push up the received data */ + rtems_termios_enqueue_raw_characters(info->ttyp, info->rx_buffer, info->rx_in); + info->rx_in = 0; + } + } + } + + /* check to see if data needs to be transmitted */ + if ( ( info->uimr & MCF_UART_UIMR_TXRDY ) && + ( MCF_UART_UISR(chan) & MCF_UART_UISR_TXRDY ) ) + { + + /* disable tx interrupts */ + info->uimr &= ~MCF_UART_UIMR_TXRDY; + MCF_UART_UIMR(chan) = info->uimr; + + /* tell upper level that character has been sent */ + if ( info->ttyp ) + rtems_termios_dequeue_characters(info->ttyp, 1); + } +} + + + +/*************************************************************************** + Function : IntUartInitialize + + Description : This initialises the internal uart hardware for all + internal uarts. If the internal uart is to be interrupt driven then the + interrupt vectors are hooked. + ***************************************************************************/ +static void +IntUartInitialize(void) +{ + unsigned int chan; + struct IntUartInfoStruct *info; + rtems_isr_entry old_handler; + int level; + + for ( chan = 0; chan < MAX_UART_INFO; chan++ ) + { + info = &IntUartInfo[chan]; + + info->ttyp = NULL; + info->rx_in = 0; + info->rx_out = 0; + info->baud = -1; + info->databits = -1; + info->parity = -1; + info->stopbits = -1; + info->hwflow = -1; + info->iomode = TERMIOS_POLLED; /*polled console io */ + + MCF_UART_UACR(chan) = 0; + MCF_UART_UIMR(chan) = 0; + if ( info->iomode != TERMIOS_POLLED ) + { + rtems_interrupt_catch (IntUartInterruptHandler, + UART_INTC0_IRQ_VECTOR(chan), + &old_handler); + } + + /* set uart default values */ + IntUartSetAttributes(chan, NULL); + + /* unmask interrupt */ + rtems_interrupt_disable(level); + switch(chan) { + case 0: + MCF_INTC0_ICR13 = MCF_INTC_ICR_IL(UART0_IRQ_LEVEL) | + MCF_INTC_ICR_IP(UART0_IRQ_PRIORITY); + MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK13 | + MCF_INTC_IMRL_MASKALL); + break; + + case 1: + MCF_INTC0_ICR14 = MCF_INTC_ICR_IL(UART1_IRQ_LEVEL) | + MCF_INTC_ICR_IP(UART1_IRQ_PRIORITY); + MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK14 | + MCF_INTC_IMRL_MASKALL); + break; + + case 2: + MCF_INTC0_ICR15 = MCF_INTC_ICR_IL(UART2_IRQ_LEVEL) | + MCF_INTC_ICR_IP(UART2_IRQ_PRIORITY); + MCF_INTC0_IMRL &= ~(MCF_INTC_IMRL_MASK15 | + MCF_INTC_IMRL_MASKALL); + break; + } + rtems_interrupt_enable(level); + + } /* of chan loop */ + + +} /* IntUartInitialise */ + + +/*************************************************************************** + Function : IntUartInterruptWrite + + Description : This writes a single character to the appropriate uart + channel. This is either called during an interrupt or in the user's task + to initiate a transmit sequence. Calling this routine enables Tx + interrupts. + ***************************************************************************/ +static int +IntUartInterruptWrite (int minor, const char *buf, int len) +{ + int level; + + rtems_interrupt_disable(level); + + /* write out character */ + MCF_UART_UTB(minor) = *buf; + + /* enable tx interrupt */ + IntUartInfo[minor].uimr |= MCF_UART_UIMR_TXRDY; + MCF_UART_UIMR(minor) = IntUartInfo[minor].uimr; + + rtems_interrupt_enable(level); + return( 0 ); +} + +/*************************************************************************** + Function : IntUartInterruptOpen + + Description : This enables interrupts when the tty is opened. + ***************************************************************************/ +static int +IntUartInterruptOpen(int major, int minor, void *arg) +{ + struct IntUartInfoStruct *info = &IntUartInfo[minor]; + + /* enable the uart */ + MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_ENABLED | MCF_UART_UCR_RX_ENABLED); + + /* check to see if interrupts need to be enabled */ + if ( info->iomode != TERMIOS_POLLED ) + { + /* enable rx interrupts */ + info->uimr |= MCF_UART_UIMR_RXRDY_FU; + MCF_UART_UIMR(minor) = info->uimr; + } + + /* check to see if doing hardware flow control */ + if ( info->hwflow ) + { + /* assert the RTS line */ + MCF_UART_UOP1(minor) = 1; + } + + return( 0 ); +} + + + +/*************************************************************************** + Function : IntUartInterruptClose + + Description : This disables interrupts when the tty is closed. + ***************************************************************************/ +static int +IntUartInterruptClose(int major, int minor, void *arg) +{ + struct IntUartInfoStruct *info = &IntUartInfo[minor]; + + /* disable the interrupts and the uart */ + MCF_UART_UIMR(minor) = 0; + MCF_UART_UCR(minor) = (MCF_UART_UCR_TX_DISABLED | MCF_UART_UCR_RX_DISABLED); + + /* reset values */ + info->ttyp = NULL; + info->uimr = 0; + info->rx_in = 0; + info->rx_out = 0; + + return( 0 ); +} + +/*************************************************************************** + Function : IntUartTaskRead + + Description : This reads all available characters from the internal uart + and places them into the termios buffer. The rx interrupts will be + re-enabled after all data has been read. + ***************************************************************************/ +static int +IntUartTaskRead(int minor) +{ + char buffer[RX_BUFFER_SIZE]; + int count; + int rx_in; + int index = 0; + struct IntUartInfoStruct *info = &IntUartInfo[minor]; + + /* determine number of values to copy out */ + rx_in = info->rx_in; + if ( info->rx_out <= rx_in ) + { + count = rx_in - info->rx_out; + } + else + { + count = (RX_BUFFER_SIZE - info->rx_out) + rx_in; + } + + /* copy data into local buffer from rx buffer */ + while ( ( index < count ) && ( index < RX_BUFFER_SIZE ) ) + { + /* copy data byte */ + buffer[index] = info->rx_buffer[info->rx_out]; + index++; + + /* increment rx buffer values */ + info->rx_out++; + if ( info->rx_out >= RX_BUFFER_SIZE ) + { + info->rx_out = 0; + } + } + + /* check to see if buffer is not empty */ + if ( count > 0 ) + { + /* set characters into termios buffer */ + rtems_termios_enqueue_raw_characters(info->ttyp, buffer, count); + } + + return( EOF ); +} + + + +/*************************************************************************** + Function : IntUartPollRead + + Description : This reads a character from the internal uart. It returns + to the caller without blocking if not character is waiting. + ***************************************************************************/ +static int +IntUartPollRead (int minor) +{ + if ( (MCF_UART_USR(minor) & MCF_UART_USR_RXRDY) == 0 ) + return(-1); + + return(MCF_UART_URB(minor)); +} + + +/*************************************************************************** + Function : IntUartPollWrite + + Description : This writes out each character in the buffer to the + appropriate internal uart channel waiting till each one is sucessfully + transmitted. + ***************************************************************************/ +static int +IntUartPollWrite (int minor, const char *buf, int len) +{ + /* loop over buffer */ + while ( len-- ) + { + /* block until we can transmit */ + while ( (MCF_UART_USR(minor) & MCF_UART_USR_TXRDY) == 0 ) + continue; + /* transmit data byte */ + MCF_UART_UTB(minor) = *buf++; + } + return(0); +} + + +/*************************************************************************** + Function : console_initialize + + Description : This initialises termios, both sets of uart hardware before + registering /dev/tty devices for each channel and the system /dev/console. + ***************************************************************************/ +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg ) +{ + rtems_status_code status; + + + /* Set up TERMIOS */ + rtems_termios_initialize (); + + /* set io modes for the different channels and initialize device */ + IntUartInfo[minor].iomode = TERMIOS_IRQ_DRIVEN; + IntUartInitialize(); + + /* Register the console port */ + status = rtems_io_register_name ("/dev/console", major, CONSOLE_PORT); + if ( status != RTEMS_SUCCESSFUL ) + { + rtems_fatal_error_occurred (status); + } + + /* Register the other port */ + if ( CONSOLE_PORT != 0 ) + { + status = rtems_io_register_name ("/dev/tty00", major, 0); + if ( status != RTEMS_SUCCESSFUL ) + { + rtems_fatal_error_occurred (status); + } + } + if ( CONSOLE_PORT != 1 ) + { + status = rtems_io_register_name ("/dev/tty01", major, 1); + if ( status != RTEMS_SUCCESSFUL ) + { + rtems_fatal_error_occurred (status); + } + } + + return(RTEMS_SUCCESSFUL); +} + +/*************************************************************************** + Function : console_open + + Description : This actually opens the device depending on the minor + number set during initialisation. The device specific access routines are + passed to termios when the devices is opened depending on whether it is + polled or not. + ***************************************************************************/ +rtems_device_driver console_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg) +{ + rtems_status_code status = RTEMS_INVALID_NUMBER; + rtems_libio_open_close_args_t *args = (rtems_libio_open_close_args_t *)arg; + struct IntUartInfoStruct *info; + + static const rtems_termios_callbacks IntUartPollCallbacks = { + NULL, /* firstOpen */ + NULL, /* lastClose */ + IntUartPollRead, /* pollRead */ + IntUartPollWrite, /* write */ + IntUartSetAttributes, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + TERMIOS_POLLED /* mode */ + }; + static const rtems_termios_callbacks IntUartIntrCallbacks = { + IntUartInterruptOpen, /* firstOpen */ + IntUartInterruptClose, /* lastClose */ + NULL, /* pollRead */ + IntUartInterruptWrite, /* write */ + IntUartSetAttributes, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + TERMIOS_IRQ_DRIVEN /* mode */ + }; + + static const rtems_termios_callbacks IntUartTaskCallbacks = { + IntUartInterruptOpen, /* firstOpen */ + IntUartInterruptClose, /* lastClose */ + IntUartTaskRead, /* pollRead */ + IntUartInterruptWrite, /* write */ + IntUartSetAttributes, /* setAttributes */ + NULL, /* stopRemoteTx */ + NULL, /* startRemoteTx */ + TERMIOS_TASK_DRIVEN /* mode */ + }; + + /* open the port depending on the minor device number */ + if ( ( minor >= 0 ) && ( minor < MAX_UART_INFO ) ) + { + info = &IntUartInfo[minor]; + switch ( info->iomode ) + { + case TERMIOS_POLLED: + status = rtems_termios_open(major, minor, arg, &IntUartPollCallbacks); + break; + case TERMIOS_IRQ_DRIVEN: + status = rtems_termios_open(major, minor, arg, &IntUartIntrCallbacks); + info->ttyp = args->iop->data1; + break; + case TERMIOS_TASK_DRIVEN: + status = rtems_termios_open(major, minor, arg, &IntUartTaskCallbacks); + info->ttyp = args->iop->data1; + break; + } + } + + if (status == RTEMS_SUCCESSFUL) + { + /* + * Reset the default baudrate. + */ + struct termios term; + if (tcgetattr (STDIN_FILENO, &term) >= 0) + { + term.c_cflag &= ~(CBAUD | CSIZE); + term.c_cflag |= CS8 | B19200; + tcsetattr (STDIN_FILENO, TCSANOW, &term); + } + } + + return( status ); +} + +/*************************************************************************** + Function : console_close + + Description : This closes the device via termios + ***************************************************************************/ +rtems_device_driver console_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg) +{ + return(rtems_termios_close (arg)); +} + +/****************** +********************************************************* + Function : console_read + + Description : Read from the device via termios + ***************************************************************************/ +rtems_device_driver console_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg) +{ + return(rtems_termios_read (arg)); +} + +/*************************************************************************** + Function : console_write + + Description : Write to the device via termios + ***************************************************************************/ +rtems_device_driver console_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg) +{ + return(rtems_termios_write (arg)); +} + +/*************************************************************************** + Function : console_ioctl + + Description : Pass the IOCtl call to termios + ***************************************************************************/ +rtems_device_driver console_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg) +{ + return( rtems_termios_ioctl (arg) ); +} +int DEBUG_OUTCHAR(int c) +{ + if(c == '\n') + DEBUG_OUTCHAR('\r'); + _BSP_null_char(c); + return c; +} +void DEBUG_OUTSTR(const char *msg) +{ + while (*msg) + DEBUG_OUTCHAR(*msg++); +} +void DEBUG_OUTNUM(int i) +{ + int n; + static const char map[] = "0123456789ABCDEF"; + DEBUG_OUTCHAR(' '); + for (n = 28 ; n >= 0 ; n -= 4) + DEBUG_OUTCHAR(map[(i >> n) & 0xF]); +} diff --git a/c/src/lib/libbsp/m68k/mcf52235/gdb-init b/c/src/lib/libbsp/m68k/mcf52235/gdb-init new file mode 100644 index 0000000000..fc86b13e35 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/gdb-init @@ -0,0 +1,46 @@ +# +# Show the exception stack frame. +# +define show-exception-sframe + set $frsr = *(unsigned short *)((unsigned long)$sp + 2) + set $frpc = *(unsigned long *)((unsigned long)$sp + 4) + set $frfvo = *(unsigned short *)((unsigned long)$sp + 0) + set $frcode = $frfvo >> 12 + set $frvect = ($frfvo & 0xFFF) >> 2 + set $frstatus = ((($frfvo >> 10) & 3) << 2) | ($frfvo & 3) + printf "EXCEPTION -- SR:0x%X PC:0x%X FRAME:0x%x VECTOR:%d STATUS:%d\n", $frsr, $frpc, $frcode, $frvect, $frstatus + if $frstatus == 4 + printf " Fault Type: Error on instruction fetch" + end + if $frstatus == 8 + printf " Fault Type: Error on operand write" + end + if $frstatus == 12 + printf " Fault Type: Error on operand read" + end + if $frstatus == 9 + printf " Fault Type: Attempted write to write-protected space" + end +end + +# Add -v and -d flags for bdm info +#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf0 +target remote | m68k-bdm-gdbserver pipe /dev/tblcf2 -B + +#monitor set remote-debug 1 +monitor bdm-reset + +# Set VBR to the beginning of what will be SRAM +monitor bdm-ctl-set 0x0801 0x20000000 + +# Set RAMBAR1 +monitor bdm-ctl-set 0x0C05 0x20000021 + +# Set FLASHBAR +monitor bdm-ctl-set 0x0C04 0x00000061 + +# Enable PST[3:0] signals +set *((char*) 0x40100074) = 0x0F + +# Add the load when debugging from ram, should never happen with rtems +#load diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h b/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h new file mode 100644 index 0000000000..307f0f5325 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/include/bsp.h @@ -0,0 +1,90 @@ +/* + * mcf52235 BSP header file + */ + +#ifndef _BSP_H +#define _BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include <bspopts.h> +#include <rtems.h> +#include <rtems/iosupp.h> +#include <rtems/console.h> +#include <rtems/clockdrv.h> +#include <rtems/iosupp.h> +#include <rtems/bspIo.h> + +/***************************************************************************/ +/** Hardware data structure headers **/ +#include <mcf52235/mcf52235.h> /* internal MCF52235 modules */ + +/***************************************************************************/ +/** Network driver configuration **/ +#if 0 +struct rtems_bsdnet_ifconfig; +extern int rtems_fec_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching ); +#define RTEMS_BSP_NETWORK_DRIVER_NAME "fs1" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_fec_driver_attach +#endif + +/***************************************************************************/ +/** User Definable configuration **/ + +/* define which port the console should use - all other ports are then defined as general purpose */ +#define CONSOLE_PORT 0 + +/* externals */ + +/* constants */ + +/* miscellaneous stuff assumed to exist */ + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + + +/* functions */ + +uint32_t bsp_get_CPU_clock_speed(void); +void bsp_cleanup(void); +m68k_isr_entry set_vector( + rtems_isr_entry handler, + rtems_vector_number vector, + int type +); + +/* + * Interrupt assignments + * Highest-priority listed first + */ +#define FEC_IRQ_LEVEL 4 +#define FEC_IRQ_RX_PRIORITY 7 +#define FEC_IRQ_TX_PRIORITY 6 + +#define PIT3_IRQ_LEVEL 4 +#define PIT3_IRQ_PRIORITY 0 + +#define UART0_IRQ_LEVEL 3 +#define UART0_IRQ_PRIORITY 7 +#define UART1_IRQ_LEVEL 3 +#define UART1_IRQ_PRIORITY 6 +#define UART2_IRQ_LEVEL 3 +#define UART2_IRQ_PRIORITY 5 + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/bspopts.h.in b/c/src/lib/libbsp/m68k/mcf52235/include/bspopts.h.in new file mode 100644 index 0000000000..a8a4bcbb38 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/include/bspopts.h.in @@ -0,0 +1,24 @@ +/* include/bspopts.h.in. Generated from configure.ac by autoheader. */ + +/* BSP uses shared logic in bootcard.c */ +#undef BSP_BOOTCARD_HANDLES_RAM_ALLOCATION + +/* If defined, then PSIM will put a non-zero pattern into the RTEMS Workspace + and C program heap. This should assist in finding code that assumes memory + starts set to zero. */ +#undef BSP_DIRTY_MEMORY + +/* Define to the address where bug reports for this package should be sent. */ +#undef PACKAGE_BUGREPORT + +/* Define to the full name of this package. */ +#undef PACKAGE_NAME + +/* Define to the full name and version of this package. */ +#undef PACKAGE_STRING + +/* Define to the one symbol short name of this package. */ +#undef PACKAGE_TARNAME + +/* Define to the version of this package. */ +#undef PACKAGE_VERSION diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/coverhd.h b/c/src/lib/libbsp/m68k/mcf52235/include/coverhd.h new file mode 100644 index 0000000000..a0aaa20535 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/include/coverhd.h @@ -0,0 +1,105 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 0 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 0 +#define CALLING_OVERHEAD_TASK_CREATE 0 +#define CALLING_OVERHEAD_TASK_IDENT 0 +#define CALLING_OVERHEAD_TASK_START 0 +#define CALLING_OVERHEAD_TASK_RESTART 0 +#define CALLING_OVERHEAD_TASK_DELETE 0 +#define CALLING_OVERHEAD_TASK_SUSPEND 0 +#define CALLING_OVERHEAD_TASK_RESUME 0 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 0 +#define CALLING_OVERHEAD_TASK_MODE 0 +#define CALLING_OVERHEAD_TASK_GET_NOTE 0 +#define CALLING_OVERHEAD_TASK_SET_NOTE 0 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 1 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 0 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 0 +#define CALLING_OVERHEAD_CLOCK_GET 1 +#define CALLING_OVERHEAD_CLOCK_SET 1 +#define CALLING_OVERHEAD_CLOCK_TICK 0 + +#define CALLING_OVERHEAD_TIMER_CREATE 0 +#define CALLING_OVERHEAD_TIMER_IDENT 0 +#define CALLING_OVERHEAD_TIMER_DELETE 0 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 1 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 1 +#define CALLING_OVERHEAD_TIMER_RESET 0 +#define CALLING_OVERHEAD_TIMER_CANCEL 0 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 0 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 0 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 0 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 0 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 0 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 0 + +#define CALLING_OVERHEAD_EVENT_SEND 0 +#define CALLING_OVERHEAD_EVENT_RECEIVE 0 +#define CALLING_OVERHEAD_SIGNAL_CATCH 0 +#define CALLING_OVERHEAD_SIGNAL_SEND 0 +#define CALLING_OVERHEAD_PARTITION_CREATE 0 +#define CALLING_OVERHEAD_PARTITION_IDENT 0 +#define CALLING_OVERHEAD_PARTITION_DELETE 0 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 0 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 0 +#define CALLING_OVERHEAD_REGION_CREATE 0 +#define CALLING_OVERHEAD_REGION_IDENT 0 +#define CALLING_OVERHEAD_REGION_DELETE 0 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 0 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 0 +#define CALLING_OVERHEAD_PORT_CREATE 0 +#define CALLING_OVERHEAD_PORT_IDENT 0 +#define CALLING_OVERHEAD_PORT_DELETE 0 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0 + +#define CALLING_OVERHEAD_IO_INITIALIZE 0 +#define CALLING_OVERHEAD_IO_OPEN 0 +#define CALLING_OVERHEAD_IO_CLOSE 0 +#define CALLING_OVERHEAD_IO_READ 0 +#define CALLING_OVERHEAD_IO_WRITE 0 +#define CALLING_OVERHEAD_IO_CONTROL 0 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 0 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 0 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 0 + +#endif diff --git a/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h b/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h new file mode 100644 index 0000000000..f8fe447335 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/include/tm27.h @@ -0,0 +1,29 @@ +/* + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +/* + * Stuff for Time Test 27 + * Don't bother with hardware -- just use a software-interrupt + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 35, 1 ) + +#define Cause_tm27_intr() asm volatile ("trap #3"); + +#define Clear_tm27_intr() /* empty */ + +#define Lower_tm27_intr() /* empty */ + +#endif diff --git a/c/src/lib/libbsp/m68k/mcf52235/preinstall.am b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am new file mode 100644 index 0000000000..48b2c6e3f3 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/preinstall.am @@ -0,0 +1,58 @@ +## Automatically generated by ampolish3 - Do not edit + +if AMPOLISH3 +$(srcdir)/preinstall.am: Makefile.am + $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am +endif + +PREINSTALL_DIRS = +DISTCLEANFILES += $(PREINSTALL_DIRS) + +all-local: $(TMPINSTALL_FILES) + +TMPINSTALL_FILES = +CLEANFILES = $(TMPINSTALL_FILES) + +all-am: $(PREINSTALL_FILES) + +PREINSTALL_FILES = +CLEANFILES += $(PREINSTALL_FILES) + +$(PROJECT_LIB)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_LIB) + @: > $(PROJECT_LIB)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) + +$(PROJECT_INCLUDE)/$(dirstamp): + @$(MKDIR_P) $(PROJECT_INCLUDE) + @: > $(PROJECT_INCLUDE)/$(dirstamp) +PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) + +$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs +PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs + +$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h + +$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h + +$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h + +$(PROJECT_INCLUDE)/coverhd.h: include/coverhd.h $(PROJECT_INCLUDE)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/coverhd.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/coverhd.h + +$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) +TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) + +$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds + diff --git a/c/src/lib/libbsp/m68k/mcf52235/start/start.S b/c/src/lib/libbsp/m68k/mcf52235/start/start.S new file mode 100644 index 0000000000..ff4e7dc8c2 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/start/start.S @@ -0,0 +1,463 @@ +/* + * mcf52235 startup code + * + * This file contains the entry point for the application. + * The name of this entry point is compiler dependent. + * It jumps to the BSP which is responsible for performing + * all initialization. + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems/asm.h> + +.extern _StackInit + +BEGIN_CODE + + PUBLIC (_INTERRUPT_VECTOR) +SYM(_INTERRUPT_VECTOR): + + .long _StackInit /* 00 Initial 'SSP' */ + .long SYM(start) /* 01 Initial PC */ + .long SYM(_uhoh) /* 02 Access Error */ + .long SYM(_uhoh) /* 03 Address Error */ + .long SYM(_uhoh) /* 04 Illegal Instruction */ + .long SYM(_uhoh) /* 05 Reserved */ + .long SYM(_uhoh) /* 06 Reserved */ + .long SYM(_uhoh) /* 07 Reserved */ + .long SYM(_uhoh) /* 08 Privilege Violation */ + .long SYM(_uhoh) /* 09 Trace */ + .long SYM(_uhoh) /* 10 Unimplemented A-Line */ + .long SYM(_uhoh) /* 11 Unimplemented F-Line */ + .long SYM(_uhoh) /* 12 Debug Interrupt */ + .long SYM(_uhoh) /* 13 Reserved */ + .long SYM(_uhoh) /* 14 Format Error */ + .long SYM(_uhoh) /* 15 Unitialized Int. */ + .long SYM(_uhoh) /* 16 Reserved */ + .long SYM(_uhoh) /* 17 Reserved */ + .long SYM(_uhoh) /* 18 Reserved */ + .long SYM(_uhoh) /* 19 Reserved */ + .long SYM(_uhoh) /* 20 Reserved */ + .long SYM(_uhoh) /* 21 Reserved */ + .long SYM(_uhoh) /* 22 Reserved */ + .long SYM(_uhoh) /* 23 Reserved */ + .long SYM(_spuriousInterrupt) /* 24 Spurious Interrupt */ + .long SYM(_uhoh) /* 25 Autovector Level 1 */ + .long SYM(_uhoh) /* 26 Autovector Level 2 */ + .long SYM(_uhoh) /* 27 Autovector Level 3 */ + .long SYM(_uhoh) /* 28 Autovector Level 4 */ + .long SYM(_uhoh) /* 29 Autovector Level 5 */ + .long SYM(_uhoh) /* 30 Autovector Level 6 */ + .long SYM(_uhoh) /* 31 Autovector Level 7 */ + .long SYM(_uhoh) /* 32 TRAP #0 */ + .long SYM(_uhoh) /* 33 TRAP #1 */ + .long SYM(_uhoh) /* 34 TRAP #2 */ + .long SYM(_uhoh) /* 35 TRAP #3 */ + .long SYM(_uhoh) /* 36 TRAP #4 */ + .long SYM(_uhoh) /* 37 TRAP #5 */ + .long SYM(_uhoh) /* 38 TRAP #6 */ + .long SYM(_uhoh) /* 39 TRAP #7 */ + .long SYM(_uhoh) /* 40 TRAP #8 */ + .long SYM(_uhoh) /* 41 TRAP #9 */ + .long SYM(_uhoh) /* 42 TRAP #10 */ + .long SYM(_uhoh) /* 43 TRAP #11 */ + .long SYM(_uhoh) /* 44 TRAP #12 */ + .long SYM(_uhoh) /* 45 TRAP #13 */ + .long SYM(_uhoh) /* 46 TRAP #14 */ + .long SYM(_uhoh) /* 47 TRAP #15 */ + .long SYM(_uhoh) /* 48 Reserved */ + .long SYM(_uhoh) /* 49 Reserved */ + .long SYM(_uhoh) /* 50 Reserved */ + .long SYM(_uhoh) /* 51 Reserved */ + .long SYM(_uhoh) /* 52 Reserved */ + .long SYM(_uhoh) /* 53 Reserved */ + .long SYM(_uhoh) /* 54 Reserved */ + .long SYM(_uhoh) /* 55 Reserved */ + .long SYM(_uhoh) /* 56 Reserved */ + .long SYM(_uhoh) /* 57 Reserved */ + .long SYM(_uhoh) /* 58 Reserved */ + .long SYM(_uhoh) /* 59 Reserved */ + .long SYM(_uhoh) /* 60 Reserved */ + .long SYM(_uhoh) /* 61 Reserved */ + .long SYM(_uhoh) /* 62 Reserved */ + .long SYM(_uhoh) /* 63 Reserved */ + + /* INTC0 */ + + .long SYM(_uhoh) /* 64*/ + .long SYM(_uhoh) /* 65*/ + .long SYM(_uhoh) /* 66*/ + .long SYM(_uhoh) /* 67*/ + .long SYM(_uhoh) /* 68*/ + .long SYM(_uhoh) /* 69*/ + .long SYM(_uhoh) /* 70*/ + .long SYM(_uhoh) /* 71*/ + .long SYM(_uhoh) /* 72*/ + .long SYM(_uhoh) /* 73*/ + .long SYM(_uhoh) /* 74*/ + .long SYM(_uhoh) /* 75*/ + .long SYM(_uhoh) /* 76*/ + .long SYM(_uhoh) /* 77*/ + .long SYM(_uhoh) /* 78*/ + .long SYM(_uhoh) /* 79*/ + .long SYM(_uhoh) /* 80*/ + .long SYM(_uhoh) /* 81*/ + .long SYM(_uhoh) /* 82*/ + .long SYM(_uhoh) /* 83*/ + .long SYM(_uhoh) /* 84*/ + .long SYM(_uhoh) /* 85*/ + .long SYM(_uhoh) /* 86*/ + .long SYM(_uhoh) /* 87*/ + .long SYM(_uhoh) /* 88*/ + .long SYM(_uhoh) /* 89*/ + .long SYM(_uhoh) /* 90*/ + .long SYM(_uhoh) /* 91*/ + .long SYM(_uhoh) /* 92*/ + .long SYM(_uhoh) /* 93*/ + .long SYM(_uhoh) /* 94*/ + .long SYM(_uhoh) /* 95*/ + .long SYM(_uhoh) /* 96*/ + .long SYM(_uhoh) /* 97*/ + .long SYM(_uhoh) /* 98*/ + .long SYM(_uhoh) /* 99*/ + .long SYM(_uhoh) /* 100*/ + .long SYM(_uhoh) /* 101*/ + .long SYM(_uhoh) /* 102*/ + .long SYM(_uhoh) /* 103*/ + .long SYM(_uhoh) /* 104*/ + .long SYM(_uhoh) /* 105*/ + .long SYM(_uhoh) /* 106*/ + .long SYM(_uhoh) /* 107*/ + .long SYM(_uhoh) /* 108*/ + .long SYM(_uhoh) /* 109*/ + .long SYM(_uhoh) /* 110*/ + .long SYM(_uhoh) /* 111*/ + .long SYM(_uhoh) /* 112*/ + .long SYM(_uhoh) /* 113*/ + .long SYM(_uhoh) /* 114*/ + .long SYM(_uhoh) /* 115*/ + .long SYM(_uhoh) /* 116*/ + .long SYM(_uhoh) /* 117*/ + .long SYM(_uhoh) /* 118*/ + .long SYM(_uhoh) /* 119*/ + .long SYM(_uhoh) /* 120*/ + .long SYM(_uhoh) /* 121*/ + .long SYM(_uhoh) /* 122*/ + .long SYM(_uhoh) /* 123*/ + .long SYM(_uhoh) /* 124*/ + .long SYM(_uhoh) /* 125*/ + .long SYM(_uhoh) /* 126*/ + .long SYM(_uhoh) /* 127*/ + + /* INTC1 */ + + .long SYM(_uhoh) /* 128*/ + .long SYM(_uhoh) /* 129*/ + .long SYM(_uhoh) /* 130*/ + .long SYM(_uhoh) /* 131*/ + .long SYM(_uhoh) /* 132*/ + .long SYM(_uhoh) /* 133*/ + .long SYM(_uhoh) /* 134*/ + .long SYM(_uhoh) /* 135*/ + .long SYM(_uhoh) /* 136*/ + .long SYM(_uhoh) /* 137*/ + .long SYM(_uhoh) /* 138*/ + .long SYM(_uhoh) /* 139*/ + .long SYM(_uhoh) /* 140*/ + .long SYM(_uhoh) /* 141*/ + .long SYM(_uhoh) /* 142*/ + .long SYM(_uhoh) /* 143*/ + .long SYM(_uhoh) /* 144*/ + .long SYM(_uhoh) /* 145*/ + .long SYM(_uhoh) /* 146*/ + .long SYM(_uhoh) /* 147*/ + .long SYM(_uhoh) /* 148*/ + .long SYM(_uhoh) /* 149*/ + .long SYM(_uhoh) /* 150*/ + .long SYM(_uhoh) /* 151*/ + .long SYM(_uhoh) /* 152*/ + .long SYM(_uhoh) /* 153*/ + .long SYM(_uhoh) /* 154*/ + .long SYM(_uhoh) /* 155*/ + .long SYM(_uhoh) /* 156*/ + .long SYM(_uhoh) /* 157*/ + .long SYM(_uhoh) /* 158*/ + .long SYM(_uhoh) /* 159*/ + .long SYM(_uhoh) /* 160*/ + .long SYM(_uhoh) /* 161*/ + .long SYM(_uhoh) /* 162*/ + .long SYM(_uhoh) /* 163*/ + .long SYM(_uhoh) /* 164*/ + .long SYM(_uhoh) /* 165*/ + .long SYM(_uhoh) /* 166*/ + .long SYM(_uhoh) /* 167*/ + .long SYM(_uhoh) /* 168*/ + .long SYM(_uhoh) /* 169*/ + .long SYM(_uhoh) /* 170*/ + .long SYM(_uhoh) /* 171*/ + .long SYM(_uhoh) /* 172*/ + .long SYM(_uhoh) /* 173*/ + .long SYM(_uhoh) /* 174*/ + .long SYM(_uhoh) /* 175*/ + .long SYM(_uhoh) /* 176*/ + .long SYM(_uhoh) /* 177*/ + .long SYM(_uhoh) /* 178*/ + .long SYM(_uhoh) /* 179*/ + .long SYM(_uhoh) /* 180*/ + .long SYM(_uhoh) /* 181*/ + .long SYM(_uhoh) /* 182*/ + .long SYM(_uhoh) /* 183*/ + .long SYM(_uhoh) /* 184*/ + .long SYM(_uhoh) /* 185*/ + .long SYM(_uhoh) /* 186*/ + .long SYM(_uhoh) /* 187*/ + .long SYM(_uhoh) /* 188*/ + .long SYM(_uhoh) /* 189*/ + .long SYM(_uhoh) /* 190*/ + .long SYM(_uhoh) /* 191*/ + .long SYM(_uhoh) /* 192*/ + + /* */ + + .long SYM(_uhoh) /* 193*/ + .long SYM(_uhoh) /* 194*/ + .long SYM(_uhoh) /* 195*/ + .long SYM(_uhoh) /* 196*/ + .long SYM(_uhoh) /* 197*/ + .long SYM(_uhoh) /* 198*/ + .long SYM(_uhoh) /* 199*/ + .long SYM(_uhoh) /* 200*/ + .long SYM(_uhoh) /* 201*/ + .long SYM(_uhoh) /* 202*/ + .long SYM(_uhoh) /* 203*/ + .long SYM(_uhoh) /* 204*/ + .long SYM(_uhoh) /* 205*/ + .long SYM(_uhoh) /* 206*/ + .long SYM(_uhoh) /* 207*/ + .long SYM(_uhoh) /* 208*/ + .long SYM(_uhoh) /* 209*/ + .long SYM(_uhoh) /* 210*/ + .long SYM(_uhoh) /* 211*/ + .long SYM(_uhoh) /* 212*/ + .long SYM(_uhoh) /* 213*/ + .long SYM(_uhoh) /* 214*/ + .long SYM(_uhoh) /* 215*/ + .long SYM(_uhoh) /* 216*/ + .long SYM(_uhoh) /* 217*/ + .long SYM(_uhoh) /* 218*/ + .long SYM(_uhoh) /* 219*/ + .long SYM(_uhoh) /* 220*/ + .long SYM(_uhoh) /* 221*/ + .long SYM(_uhoh) /* 222*/ + .long SYM(_uhoh) /* 223*/ + .long SYM(_uhoh) /* 224*/ + .long SYM(_uhoh) /* 225*/ + .long SYM(_uhoh) /* 226*/ + .long SYM(_uhoh) /* 227*/ + .long SYM(_uhoh) /* 228*/ + .long SYM(_uhoh) /* 229*/ + .long SYM(_uhoh) /* 230*/ + .long SYM(_uhoh) /* 231*/ + .long SYM(_uhoh) /* 232*/ + .long SYM(_uhoh) /* 233*/ + .long SYM(_uhoh) /* 234*/ + .long SYM(_uhoh) /* 235*/ + .long SYM(_uhoh) /* 236*/ + .long SYM(_uhoh) /* 237*/ + .long SYM(_uhoh) /* 238*/ + .long SYM(_uhoh) /* 239*/ + .long SYM(_uhoh) /* 240*/ + .long SYM(_uhoh) /* 241*/ + .long SYM(_uhoh) /* 242*/ + .long SYM(_uhoh) /* 243*/ + .long SYM(_uhoh) /* 244*/ + .long SYM(_uhoh) /* 245*/ + .long SYM(_uhoh) /* 246*/ + .long SYM(_uhoh) /* 247*/ + .long SYM(_uhoh) /* 248*/ + .long SYM(_uhoh) /* 249*/ + .long SYM(_uhoh) /* 250*/ + .long SYM(_uhoh) /* 251*/ + .long SYM(_uhoh) /* 252*/ + .long SYM(_uhoh) /* 253*/ + .long SYM(_uhoh) /* 254*/ + .long SYM(_uhoh) /* 255*/ + +/* + * We must write the flash configuration here. This portion of flash is shadowed + * by some flash registers, so we can't put code here! + */ + + PUBLIC (_FLASH_CONFIGURATION_FIELD) +SYM(_FLASH_CONFIGURATION_FIELD): + +_key_upper: .long 0x00000000 +_key_lower: .long 0x00000000 +_cfm_prot: .long 0x00000000 +_cfm_sacc: .long 0x00000000 +_cfm_dacc: .long 0x00000000 +_cfm_msec: .long 0x00000000 + +/* + * Default trap handler + * With an oscilloscope you can see AS* stop + */ +.align 4 + PUBLIC (_uhoh) +SYM(_uhoh): +/* + link a6,#0 + lea -20(sp), sp + movem.l d0-d2/a0-a1, (sp) + pea.l 20(sp) | push exception frame address + jsr mcf5xxx_exception_handler + movem.l 4(sp), d0-d2/a0-a1 + lea 24(sp), sp + unlk a6 + rte +*/ + nop | Leave spot for breakpoint + stop #0x2700 | Stop with interrupts disabled + bra.w SYM(_uhoh) | Stuck forever + +/* + * Spurious Interrupt Handler + */ +.align 4 + PUBLIC (_spuriousInterrupt) +SYM(_spuriousInterrupt): + addql #1, SYM(_M68kSpuriousInterruptCount) + rte + +/* + * Write VBR Register + */ +.align 4 + PUBLIC (_wr_vbr) +SYM(_wr_vbr): + move.l 4(sp), d0 + movec d0, vbr + nop + rts + +/* + * Board startup + * Disable watchdog, interrupts + * Enable sram + */ +.align 4 + PUBLIC (start) +SYM(start): + + /* Mask off interupts */ + move.w #0x2700, sr + + /* Save off reset values of D0 and D1 */ + move.l d0, d6 + move.l d1, d7 + + /* Initialize RAMBAR: locate SRAM and validate it */ + move.l #_RamBase, d0 + add.l #0x21, d0 + movec d0, %rambar + + /* Locate Stack Pointer */ + move.l #_StackInit, sp + + /* Initialize FLASHBAR */ + move.l #_FlashBase, d0 + cmp.l #0x00000000, d0 + bne _change_flashbar + add.l #0x61, d0 + movec d0, %flashbar + +_continue_startup: + + /* Locate Stack Pointer */ + move.l #_StackInit, sp + + /* Save off intial D0 and D1 to RAM */ + move.l d6, SYM(_d0_reset) + move.l d7, SYM(_d1_reset) + + /* + * Remainder of the startup code is handled by C code + * This never returns + */ + jmp SYM(Init52235) + +_change_flashbar: + /* + * The following sequence is used to set FLASHBAR. Since we may + * be executing from Flash, we must put the routine into SRAM for + * execution and then jump back to Flash using the new address. + * + * The following instructions are coded into the SRAM: + * + * move.l #(__FLASH + 0x61),d0 + * movec d0, FLASHBAR + * jmp _continue_startup + * + * An arbitrary SRAM address is chosen until the real address + * can be loaded. + * + * This routine is not necessary if the default Flash address + * (0x00000000) is used. + * + * If running in SRAM, change_flashbar should not be executed + */ + + move.l #_RamBase, a0 + + /* Code "move.l #(__FLASH + 0x61),d0" into SRAM */ + move.w #0x203C, d0 + move.w d0, (a0)+ + move.l #_FlashBase, d0 + add.l #0x61, d0 + move.l d0, (a0)+ + + /* Code "movec d0,FLASHBAR" into SRAM */ + move.l #0x4e7b0C04, d0 + move.l d0, (a0)+ + + /* Code "jmp _continue_startup" into SRAM */ + move.w #0x4EF9, d0 + move.w d0, (a0)+ + move.l #_continue_startup, d0 + move.l d0, (a0)+ + + /* Jump to code segment in internal SRAM */ + jmp _RamBase + +END_CODE + + +BEGIN_DATA_DCL + + .align 4 + +PUBLIC (_M68kSpuriousInterruptCount) +SYM (_M68kSpuriousInterruptCount): + .long 0 + +PUBLIC (_d0_reset) +SYM (_d0_reset): + .long 0 + +PUBLIC (_d1_reset) +SYM (_d1_reset): + .long 0 + +END_DATA_DCL + +END + diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/bspclean.c b/c/src/lib/libbsp/m68k/mcf52235/startup/bspclean.c new file mode 100644 index 0000000000..7bddc13392 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/bspclean.c @@ -0,0 +1,34 @@ +/* + * SBC5206 bsp_cleanup + * + * This routine returns control from RTEMS to the monitor. + * + * Author: + * David Fiddes, D.J@fiddes.surfaid.org + * http://www.calm.hw.ac.uk/davidf/coldfire/ + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <rtems.h> +#include <bsp.h> +#include <rtems/bspIo.h> + +void bsp_cleanup( void ) +{ + printk("\nRTEMS exited!\n"); + for ( ;; ) + { + asm volatile ( " nop " ); + asm volatile ( " nop " ); + } + +} diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/bspstart.c b/c/src/lib/libbsp/m68k/mcf52235/startup/bspstart.c new file mode 100644 index 0000000000..bb57277dc7 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/bspstart.c @@ -0,0 +1,64 @@ +/* + * BSP startup + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * Author: + * David Fiddes, D.J@fiddes.surfaid.org + * http://www.calm.hw.ac.uk/davidf/coldfire/ + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.rtems.com/license/LICENSE. + * + * $Id$ + */ + +#include <bsp.h> +#include <rtems/libio.h> +#include <rtems/libcsupport.h> + +/* + * Cannot be frozen + */ +void _CPU_cache_freeze_data(void) {} +void _CPU_cache_unfreeze_data(void) {} +void _CPU_cache_freeze_instruction(void) {} +void _CPU_cache_unfreeze_instruction(void) {} + +/* + * Write-through data cache -- flushes are unnecessary + */ +void _CPU_cache_flush_1_data_line(const void *d_addr) {} +void _CPU_cache_flush_entire_data(void) {} + +void _CPU_cache_enable_instruction(void) {} +void _CPU_cache_disable_instruction(void) {} +void _CPU_cache_invalidate_entire_instruction(void) {} +void _CPU_cache_invalidate_1_instruction_line(const void *addr) {} + +void _CPU_cache_enable_data(void) {} +void _CPU_cache_disable_data(void) {} +void _CPU_cache_invalidate_entire_data(void) {} +void _CPU_cache_invalidate_1_data_line(const void *addr) {} + +/* + * bsp_start + * + * This routine does the bulk of the system initialisation. + */ +void bsp_start( void ) +{ +} + +uint32_t bsp_get_CPU_clock_speed(void) +{ + return 60000000; +} diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c new file mode 100644 index 0000000000..5f7c2a5c54 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/cfinit.c @@ -0,0 +1,566 @@ +/*********************************************************************
+* Initialisation Code for ColdFire MCF52235 Processor *
+**********************************************************************
+ Generated by ColdFire Initialisation Utility 2.10.8
+ Fri May 23 14:39:00 2008
+
+ MicroAPL Ltd makes no warranties in respect of the suitability
+ of this code for any particular purpose, and accepts
+ no liability for any loss arising out of its use. The person or
+ persons making use of this file must make the final evaluation
+ as to its suitability and correctness for a particular application.
+
+*/
+
+/* Processor/internal bus clocked at 60.00 MHz */
+
+#include <mcf52235/mcf52235.h>
+
+/* Additional register read/write macros (missing in headers) */
+#define MCF_CIM_CCON (*(vuint16*)(void*)(&__IPSBAR[0x00110004]))
+
+/* Bit definitions and macros for MCF_CIM_CCON */
+#define MCF_CIM_CCON_SZEN (0x00000040)
+#define MCF_CIM_CCON_PSTEN (0x00000020)
+#define MCF_CIM_CCON_BME (0x00000008)
+#define MCF_CIM_CCON_BMT(x) (((x)&0x00000007)<<0)
+
+/* Function prototypes */
+void init_main (void);
+static void disable_interrupts (void);
+static void disable_watchdog_timer (void);
+static void init_ipsbar (void);
+static void init_clock_config (void);
+static void init_sram (void);
+static void init_flash_controller (void);
+static void init_eport (void);
+static void init_flexcan (void);
+static void init_bus_config (void);
+static void init_power_management (void);
+static void init_dma_timers (void);
+static void init_gp_timer (void);
+static void init_interrupt_timers (void);
+static void init_real_time_clock (void);
+static void init_watchdog_timer (void);
+static void init_pin_assignments (void);
+static void init_interrupt_controller (void);
+
+/*********************************************************************
+* init_main - Main entry point for initialisation code *
+**********************************************************************/
+void init_main (void)
+{
+ /* Mask all interrupts */
+ asm("move.w #0x2700,%sr");
+
+ /* Initialise base address of peripherals, VBR, etc */
+ init_ipsbar ();
+ init_clock_config ();
+
+ /* Disable interrupts and watchdog timer */
+ disable_interrupts ();
+ disable_watchdog_timer ();
+
+ /* Initialise individual modules */
+ init_sram ();
+ init_flash_controller ();
+ init_eport ();
+ init_flexcan ();
+ init_bus_config ();
+ init_power_management ();
+ init_dma_timers ();
+ init_gp_timer ();
+ init_interrupt_timers ();
+ init_real_time_clock ();
+ init_watchdog_timer ();
+ init_pin_assignments ();
+
+ /* Initialise interrupt controller */
+ init_interrupt_controller ();
+}
+
+/*********************************************************************
+* disable_interrupts - Disable all interrupt sources *
+**********************************************************************/
+static void disable_interrupts (void)
+{
+ vuint8 *p;
+ int i;
+
+ /* Set ICR008-ICR063 to 0x0 */
+ p = (vuint8 *) &MCF_INTC0_ICR8;
+ for (i = 8; i <= 63; i++)
+ *p++ = 0x0;
+
+ /* Set ICR108-ICR139 to 0x0 */
+ p = (vuint8 *) &MCF_INTC1_ICR8;
+ for (i = 108; i <= 139; i++)
+ *p++ = 0x0;
+}
+
+/*********************************************************************
+* disable_watchdog_timer - Disable system watchdog timer *
+**********************************************************************/
+static void disable_watchdog_timer (void)
+{
+ /* Disable Core Watchdog Timer */
+ MCF_SCM_CWCR = 0;
+}
+
+/*********************************************************************
+* init_clock_config - Clock Module *
+**********************************************************************/
+static void init_clock_config (void)
+{
+ /* Clock source is 25.0000 MHz external crystal
+ Clock mode: Normal PLL mode
+ Processor/Bus clock frequency = 60.00 MHz
+ Loss of clock detection disabled
+ Reset on loss of lock disabled
+ */
+
+ /* Divide 25.0000 MHz clock to get 5.00 MHz PLL input clock */
+ MCF_CLOCK_CCHR = MCF_CLOCK_CCHR_PFD(0x4);
+
+ /* Set RFD+1 to avoid frequency overshoot and wait for PLL to lock */
+ MCF_CLOCK_SYNCR = 0x4103;
+ while ((MCF_CLOCK_SYNSR & 0x08) == 0)
+ ;
+
+ /* Set desired RFD=0 and MFD=4 and wait for PLL to lock */
+ MCF_CLOCK_SYNCR = 0x4003;
+ while ((MCF_CLOCK_SYNSR & 0x08) == 0)
+ ;
+ MCF_CLOCK_SYNCR = 0x4007; /* Switch to using PLL */
+}
+
+/*********************************************************************
+* init_ipsbar - Internal Peripheral System Base Address (IPSBAR) *
+**********************************************************************/
+static void init_ipsbar (void)
+{
+ /* Base address of internal peripherals (IPSBAR) = 0x40000000
+
+ Note: Processor powers up with IPS base address = 0x40000000
+ Write to IPS base + 0x00000000 to set new value
+ */
+ * (vuint32 *) 0x40000000 = (vuint32) __IPSBAR + 1; /* +1 for Enable */
+}
+
+/*********************************************************************
+* init_flash_controller - Flash Module *
+**********************************************************************/
+static void init_flash_controller (void)
+{
+ /* Internal Flash module enabled, address = $00000000
+ Flash state machine clock = 197.37 kHz
+ All access types except CPU space/interrupt acknowledge cycle allowed
+ Flash is Write-Protected
+ All interrupts disabled
+ */
+ MCF_CFM_CFMCLKD = MCF_CFM_CFMCLKD_PRDIV8 |
+ MCF_CFM_CFMCLKD_DIV(0x12);
+ MCF_CFM_CFMMCR = 0;
+
+ /* WARNING: Setting FLASHBAR[6]=1 in order to turn off address speculation
+ This is a workaround for a hardware problem whereby a speculative
+ access to the Flash occuring at the same time as an SRAM access
+ can return corrupt data.
+
+ This workaround can result in a 4% - 9% performance penalty. Other workarounds
+ are possible for certain applications.
+
+ For example, if you know that you will not be using the top 32 KB of the Flash
+ you can place the SRAM base address at 0x20038000
+
+ See Device Errata for further details
+ */
+ asm("move.l #0x00000161,%d0");
+ asm("movec %d0,%FLASHBAR");
+}
+
+/*********************************************************************
+* init_eport - Edge Port Module (EPORT) *
+**********************************************************************/
+static void init_eport (void)
+{
+ /* Pins 1-15 configured as GPIO inputs */
+ MCF_EPORT_EPDDR0 = 0;
+ MCF_EPORT_EPDDR1 = 0;
+ MCF_EPORT_EPPAR0 = 0;
+ MCF_EPORT_EPPAR1 = 0;
+ MCF_EPORT_EPIER0 = 0;
+ MCF_EPORT_EPIER1 = 0;
+}
+
+/*********************************************************************
+* init_flexcan - FlexCAN Module *
+**********************************************************************/
+static void init_flexcan (void)
+{
+ /* FlexCAN controller disabled (CANMCR0[MDIS]=1) */
+ MCF_CAN_IMASK = 0;
+ MCF_CAN_RXGMASK = MCF_CAN_RXGMASK_MI(0x1fffffff);
+ MCF_CAN_RX14MASK = MCF_CAN_RX14MASK_MI(0x1fffffff);
+ MCF_CAN_RX15MASK = MCF_CAN_RX15MASK_MI(0x1fffffff);
+ MCF_CAN_CANCTRL = 0;
+ MCF_CAN_CANMCR = MCF_CAN_CANMCR_MDIS |
+ MCF_CAN_CANMCR_FRZ |
+ MCF_CAN_CANMCR_HALT |
+ MCF_CAN_CANMCR_SUPV |
+ MCF_CAN_CANMCR_MAXMB(0xf);
+}
+
+/*********************************************************************
+* init_bus_config - Internal Bus Arbitration *
+**********************************************************************/
+static void init_bus_config (void)
+{
+ /* Use round robin arbitration scheme
+ Assigned priorities (highest first):
+ Ethernet
+ DMA Controller
+ ColdFire Core
+ DMA bandwidth control disabled
+ Park on last active bus master
+ */
+ MCF_SCM_MPARK = MCF_SCM_MPARK_M3PRTY(0x3) |
+ MCF_SCM_MPARK_M2PRTY(0x2) |
+ (0x1 << 16);
+}
+
+/*********************************************************************
+* init_sram - On-chip SRAM *
+**********************************************************************/
+static void init_sram (void)
+{
+ /* Internal SRAM module enabled, address = $20000000
+ DMA access to SRAM block disabled
+ All access types (supervisor and user) allowed
+ */
+ asm("move.l #0x20000001,%d0");
+ asm("movec %d0,%RAMBAR");
+}
+
+/*********************************************************************
+* init_power_management - Power Management *
+**********************************************************************/
+static void init_power_management (void)
+{
+ /* On executing STOP instruction, processor enters RUN mode
+ Mode is exited when an interrupt of level 1 or higher is received
+ */
+ MCF_PMM_LPICR = MCF_PMM_LPICR_ENBSTOP;
+ MCF_PMM_LPCR = MCF_PMM_LPCR_LPMD_RUN;
+}
+
+/*********************************************************************
+* init_dma_timers - DMA Timer Modules *
+**********************************************************************/
+static void init_dma_timers (void)
+{
+ /* DMA Timer 0 disabled (DTMR0[RST] = 0) */
+ MCF_DTIM0_DTMR = MCF_DTIM_DTMR_CLK(0x1);
+ MCF_DTIM0_DTXMR = 0;
+ MCF_DTIM0_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+ /* DMA Timer 1 disabled (DTMR1[RST] = 0) */
+ MCF_DTIM1_DTMR = 0;
+ MCF_DTIM1_DTXMR = 0;
+ MCF_DTIM1_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+ /* DMA Timer 2 disabled (DTMR2[RST] = 0) */
+ MCF_DTIM2_DTMR = 0;
+ MCF_DTIM2_DTXMR = 0;
+ MCF_DTIM2_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+
+ /* DMA Timer 3 disabled (DTMR3[RST] = 0) */
+ MCF_DTIM3_DTMR = MCF_DTIM_DTMR_CLK(0x1);
+ MCF_DTIM3_DTXMR = 0;
+ MCF_DTIM3_DTRR = MCF_DTIM_DTRR_REF(0xffffffff);
+}
+
+/*********************************************************************
+* init_gp_timer - General Purpose Timer (GPT) Module *
+**********************************************************************/
+static void init_gp_timer (void)
+{
+ /*
+ GPT disabled (GPTASCR1[GPTEN] = 0)
+ Channel 0 configured as GPIO input
+ Channel 1 configured as GPIO input
+ Channel 2 configured as GPIO input
+ Channel 3 configured as GPIO input
+ */
+ MCF_GPT_GPTSCR1 = 0;
+ MCF_GPT_GPTDDR = 0;
+}
+
+/**********************************************************************
+* init_interrupt_timers - Programmable Interrupt Timer (PIT) Modules *
+***********************************************************************/
+static void init_interrupt_timers (void)
+{
+ /* PIT0 disabled (PCSR0[EN]=0) */
+ MCF_PIT0_PCSR = 0;
+
+ /* PIT1 disabled (PCSR1[EN]=0) */
+ MCF_PIT1_PCSR = 0;
+}
+
+/*********************************************************************
+* init_real_time_clock - Real-Time Clock (RTC) *
+**********************************************************************/
+static void init_real_time_clock (void)
+{
+ /* Disable the RTC */
+ MCF_RTC_CR = 0;
+}
+
+/*********************************************************************
+* init_watchdog_timer - Watchdog Timer *
+**********************************************************************/
+static void init_watchdog_timer (void)
+{
+ /* Core Watchdog Timer disabled (CWCR[CWE]=0) */
+ MCF_SCM_CWCR = 0;
+}
+
+/*********************************************************************
+* init_interrupt_controller - Interrupt Controller *
+**********************************************************************/
+static void init_interrupt_controller (void)
+{
+ /* Configured interrupt sources in order of priority...
+ Level 7: External interrupt /IRQ7, (initially masked)
+ Level 6: External interrupt /IRQ6, (initially masked)
+ Level 5: External interrupt /IRQ5, (initially masked)
+ Level 4: External interrupt /IRQ4, (initially masked)
+ Level 3: External interrupt /IRQ3, (initially masked)
+ Level 2: External interrupt /IRQ2, (initially masked)
+ Level 1: External interrupt /IRQ1, (initially masked)
+ */
+ MCF_INTC0_ICR1 = 0;
+ MCF_INTC0_ICR2 = 0;
+ MCF_INTC0_ICR3 = 0;
+ MCF_INTC0_ICR4 = 0;
+ MCF_INTC0_ICR5 = 0;
+ MCF_INTC0_ICR6 = 0;
+ MCF_INTC0_ICR7 = 0;
+ MCF_INTC0_ICR8 = 0;
+ MCF_INTC0_ICR9 = 0;
+ MCF_INTC0_ICR10 = 0;
+ MCF_INTC0_ICR11 = 0;
+ MCF_INTC0_ICR12 = 0;
+ MCF_INTC0_ICR13 = 0;
+ MCF_INTC0_ICR14 = 0;
+ MCF_INTC0_ICR15 = 0;
+ MCF_INTC0_ICR17 = 0;
+ MCF_INTC0_ICR18 = 0;
+ MCF_INTC0_ICR19 = 0;
+ MCF_INTC0_ICR20 = 0;
+ MCF_INTC0_ICR21 = 0;
+ MCF_INTC0_ICR22 = 0;
+ MCF_INTC0_ICR23 = 0;
+ MCF_INTC0_ICR24 = 0;
+ MCF_INTC0_ICR25 = 0;
+ MCF_INTC0_ICR26 = 0;
+ MCF_INTC0_ICR27 = 0;
+ MCF_INTC0_ICR28 = 0;
+ MCF_INTC0_ICR29 = 0;
+ MCF_INTC0_ICR30 = 0;
+ MCF_INTC0_ICR31 = 0;
+ MCF_INTC0_ICR32 = 0;
+ MCF_INTC0_ICR33 = 0;
+ MCF_INTC0_ICR34 = 0;
+ MCF_INTC0_ICR35 = 0;
+ MCF_INTC0_ICR36 = 0;
+ MCF_INTC0_ICR41 = 0;
+ MCF_INTC0_ICR42 = 0;
+ MCF_INTC0_ICR43 = 0;
+ MCF_INTC0_ICR44 = 0;
+ MCF_INTC0_ICR45 = 0;
+ MCF_INTC0_ICR46 = 0;
+ MCF_INTC0_ICR47 = 0;
+ MCF_INTC0_ICR48 = 0;
+ MCF_INTC0_ICR49 = 0;
+ MCF_INTC0_ICR50 = 0;
+ MCF_INTC0_ICR51 = 0;
+ MCF_INTC0_ICR52 = 0;
+ MCF_INTC0_ICR53 = 0;
+ MCF_INTC0_ICR55 = 0;
+ MCF_INTC0_ICR56 = 0;
+ MCF_INTC0_ICR59 = 0;
+ MCF_INTC0_ICR60 = 0;
+ MCF_INTC0_ICR61 = 0;
+ MCF_INTC0_ICR62 = 0;
+ MCF_INTC0_ICR63 = 0;
+ MCF_INTC1_ICR8 = 0;
+ MCF_INTC1_ICR9 = 0;
+ MCF_INTC1_ICR10 = 0;
+ MCF_INTC1_ICR11 = 0;
+ MCF_INTC1_ICR12 = 0;
+ MCF_INTC1_ICR13 = 0;
+ MCF_INTC1_ICR14 = 0;
+ MCF_INTC1_ICR15 = 0;
+ MCF_INTC1_ICR16 = 0;
+ MCF_INTC1_ICR17 = 0;
+ MCF_INTC1_ICR18 = 0;
+ MCF_INTC1_ICR19 = 0;
+ MCF_INTC1_ICR20 = 0;
+ MCF_INTC1_ICR21 = 0;
+ MCF_INTC1_ICR22 = 0;
+ MCF_INTC1_ICR23 = 0;
+ MCF_INTC1_ICR24 = 0;
+ MCF_INTC1_ICR25 = 0;
+ MCF_INTC1_ICR32 = 0;
+ MCF_INTC1_ICR33 = 0;
+ MCF_INTC1_ICR34 = 0;
+ MCF_INTC1_ICR35 = 0;
+ MCF_INTC1_ICR36 = 0;
+ MCF_INTC1_ICR37 = 0;
+ MCF_INTC1_ICR38 = 0;
+ MCF_INTC1_ICR39 = 0;
+ MCF_INTC0_IMRH = 0xffffffff;
+ MCF_INTC0_IMRL = 0xfffffffe;
+ MCF_INTC1_IMRH = 0xffffffff;
+ MCF_INTC1_IMRL = 0xfffffffe;
+}
+
+/*********************************************************************
+* init_pin_assignments - Pin Assignment and General Purpose I/O *
+**********************************************************************/
+static void init_pin_assignments (void)
+{
+ /* Pin assignments for port NQ
+ Pins NQ7-NQ1 : EdgePort GPIO/IRQ
+ */
+ MCF_GPIO_DDRNQ = 0;
+ MCF_GPIO_PNQPAR = MCF_GPIO_PNQPAR_PNQPAR7(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR6(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR5(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR4(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR3(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR2(0x1) |
+ MCF_GPIO_PNQPAR_PNQPAR1(0x1);
+
+ /* Pin assignments for port GP
+ Pins PG7-PG0 : EdgePort GPIO/IRQ
+ */
+ MCF_GPIO_DDRGP = 0;
+ MCF_GPIO_PGPPAR = MCF_GPIO_PGPPAR_PGPPAR7 |
+ MCF_GPIO_PGPPAR_PGPPAR6 |
+ MCF_GPIO_PGPPAR_PGPPAR5 |
+ MCF_GPIO_PGPPAR_PGPPAR4 |
+ MCF_GPIO_PGPPAR_PGPPAR3 |
+ MCF_GPIO_PGPPAR_PGPPAR2 |
+ MCF_GPIO_PGPPAR_PGPPAR1 |
+ MCF_GPIO_PGPPAR_PGPPAR0;
+
+ /* Pin assignments for port DD
+ Pin DD7 : DDATA[3]
+ Pin DD6 : DDATA[2]
+ Pin DD5 : DDATA[1]
+ Pin DD4 : DDATA[0]
+ Pin DD3 : PST[3]
+ Pin DD2 : PST[2]
+ Pin DD1 : PST[1]
+ Pin DD0 : PST[0]
+ CCON[PSTEN] = 1 to enable PST/DDATA function
+ */
+ MCF_GPIO_DDRDD = 0;
+ MCF_GPIO_PDDPAR = MCF_GPIO_PDDPAR_PDDPAR7 |
+ MCF_GPIO_PDDPAR_PDDPAR6 |
+ MCF_GPIO_PDDPAR_PDDPAR5 |
+ MCF_GPIO_PDDPAR_PDDPAR4 |
+ MCF_GPIO_PDDPAR_PDDPAR3 |
+ MCF_GPIO_PDDPAR_PDDPAR2 |
+ MCF_GPIO_PDDPAR_PDDPAR1 |
+ MCF_GPIO_PDDPAR_PDDPAR0;
+ MCF_CIM_CCON = 0x0021;
+
+ /* Pin assignments for port AN
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRAN = 0;
+ MCF_GPIO_PANPAR = 0;
+
+ /* Pin assignments for port AS
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRAS = 0;
+ MCF_GPIO_PASPAR = 0;
+
+ /* Pin assignments for port LD
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRLD = 0;
+ MCF_GPIO_PLDPAR = 0;
+
+ /* Pin assignments for port QS
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRQS = 0;
+ MCF_GPIO_PQSPAR = 0;
+
+ /* Pin assignments for port TA
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRTA = 0;
+ MCF_GPIO_PTAPAR = 0;
+
+ /* Pin assignments for port TC
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRTC = 0;
+ MCF_GPIO_PTCPAR = 0;
+
+ /* Pin assignments for port TD
+ Pins are all GPIO inputs
+ */
+ MCF_GPIO_DDRTD = 0;
+ MCF_GPIO_PTDPAR = 0;
+
+ /* Pin assignments for port UA
+ Pin UA3 : UART 0 clear-to-send, UCTS0
+ Pin UA2 : UART 0 request-to-send, URTS0
+ Pin UA1 : UART 0 receive data, URXD0
+ Pin UA0 : UART 0 transmit data, UTXD0
+ */
+ MCF_GPIO_DDRUA = 0;
+ MCF_GPIO_PUAPAR = MCF_GPIO_PUAPAR_PUAPAR3(0x1) |
+ MCF_GPIO_PUAPAR_PUAPAR2(0x1) |
+ MCF_GPIO_PUAPAR_PUAPAR1(0x1) |
+ MCF_GPIO_PUAPAR_PUAPAR0(0x1);
+
+ /* Pin assignments for port UB
+ Pin UB3 : UART 1 clear-to-send, UCTS1
+ Pin UB2 : UART 1 request-to-send, URTS1
+ Pin UB1 : UART 1 receive data, URXD1
+ Pin UB0 : UART 1 transmit data, UTXD1
+ */
+ MCF_GPIO_DDRUB = 0;
+ MCF_GPIO_PUBPAR = MCF_GPIO_PUBPAR_PUBPAR3(0x1) |
+ MCF_GPIO_PUBPAR_PUBPAR2(0x1) |
+ MCF_GPIO_PUBPAR_PUBPAR1(0x1) |
+ MCF_GPIO_PUBPAR_PUBPAR0(0x1);
+
+ /* Pin assignments for port UC
+ Pin UC3 : UART 2 clear-to-send, UCTS2
+ Pin UC2 : UART 2 request-to-send, URTS2
+ Pin UC1 : UART 2 receive data, URXD2
+ Pin UC0 : UART 2 transmit data, UTXD2
+ */
+ MCF_GPIO_DDRUC = 0;
+ MCF_GPIO_PUCPAR = MCF_GPIO_PUCPAR_PUCPAR3 |
+ MCF_GPIO_PUCPAR_PUCPAR2 |
+ MCF_GPIO_PUCPAR_PUCPAR1 |
+ MCF_GPIO_PUCPAR_PUCPAR0;
+
+ /* Configure drive strengths */
+ MCF_GPIO_PDSRH = 0;
+ MCF_GPIO_PDSRL = 0;
+
+ /* Configure Wired-OR register */
+ MCF_GPIO_PWOR = 0;
+}
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c b/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c new file mode 100644 index 0000000000..ad0ac54d52 --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/init52235.c @@ -0,0 +1,283 @@ +/*
+ * This is where the real hardware setup is done. A minimal stack
+ * has been provided by the start.S code. No normal C or RTEMS
+ * functions can be called from here.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+
+extern void _wr_vbr(uint32_t);
+extern void init_main();
+extern int boot_card(int, char **, char **);
+
+/*
+ * From linkcmds
+ */
+
+extern uint8_t _RamBase[];
+extern uint8_t _INTERRUPT_VECTOR[];
+
+extern uint8_t _clear_start[];
+extern uint8_t _clear_end[];
+
+extern uint8_t _data_src_start[];
+extern uint8_t _data_dest_start[];
+extern uint8_t _data_dest_end[];
+
+
+void Init52235 (void)
+{
+ register uint32_t i;
+ register uint32_t *dp, *sp;
+ register uint8_t *dbp, *sbp;
+
+ /*
+ * Initialize the hardware
+ */
+ init_main();
+
+ /*
+ * Copy the vector table to RAM
+ */
+
+ if(_RamBase != _INTERRUPT_VECTOR)
+ {
+ sp = (uint32_t *) _INTERRUPT_VECTOR;
+ dp = (uint32_t *) _RamBase;
+ for(i = 0; i < 256; i++)
+ {
+ *dp++ = *sp++;
+ }
+ }
+
+ _wr_vbr((uint32_t) _RamBase);
+
+ /*
+ * Move initialized data from ROM to RAM.
+ */
+ if (_data_src_start != _data_dest_start)
+ {
+ dbp = (uint8_t *) _data_dest_start;
+ sbp = (uint8_t *) _data_src_start;
+ i = _data_dest_end - _data_dest_start;
+ while (i--)
+ *dbp++ = *sbp++;
+ }
+
+ /*
+ * Zero uninitialized data
+ */
+
+ if (_clear_start != _clear_end)
+ {
+ sbp = _clear_start;
+ dbp = _clear_end;
+ i = dbp - sbp;
+ while (i--)
+ *sbp++ = 0;
+ }
+
+ /*
+ * We have to call some kind of RTEMS function here!
+ */
+
+ boot_card(0, 0, 0);
+ for(;;);
+}
+
+#if 0
+/***********************************************************************
+ *
+ * This is the exception handler for all defined exceptions. Most
+ * exceptions do nothing, but some of the more important ones are
+ * handled to some extent.
+ *
+ * Called by asm_exception_handler
+ *
+ * The ColdFire family of processors has a simplified exception stack
+ * frame that looks like the following:
+ *
+ * 3322222222221111 111111
+ * 1098765432109876 5432109876543210
+ * 8 +----------------+----------------+
+ * | Program Counter |
+ * 4 +----------------+----------------+
+ * |FS/Fmt/Vector/FS| SR |
+ * SP --> 0 +----------------+----------------+
+ *
+ * The stack self-aligns to a 4-byte boundary at an exception, with
+ * the FS/Fmt/Vector/FS field indicating the size of the adjustment
+ * (SP += 0,1,2,3 bytes).
+ */
+#define MCF5XXX_RD_SF_FORMAT(PTR) \
+ ((*((uint16_t *)(PTR)) >> 12) & 0x00FF)
+
+#define MCF5XXX_RD_SF_VECTOR(PTR) \
+ ((*((uint16_t *)(PTR)) >> 2) & 0x00FF)
+
+#define MCF5XXX_RD_SF_FS(PTR) \
+ ( ((*((uint16_t *)(PTR)) & 0x0C00) >> 8) | (*((uint16_t *)(PTR)) & 0x0003) )
+
+#define MCF5XXX_SF_SR(PTR) *((uint16_t *)(PTR)+1)
+#define MCF5XXX_SF_PC(PTR) *((uint32_t *)(PTR)+1)
+
+void ecatch(const char* a_error, uint32_t a_pc)
+{
+ volatile const char* error = a_error;
+ volatile uint32_t pc = a_pc;
+ return;
+}
+
+void mcf5xxx_exception_handler(void *framep)
+{
+ volatile uint16_t sr;
+ volatile uint32_t pc;
+
+ switch (MCF5XXX_RD_SF_FORMAT(framep))
+ {
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ break;
+ default:
+ // Illegal stack type
+ ecatch("Illegal stack type", MCF5XXX_SF_PC(framep));
+ break;
+ }
+
+ switch (MCF5XXX_RD_SF_VECTOR(framep))
+ {
+ case 2:
+ ecatch("Access Error", MCF5XXX_SF_PC(framep));
+ switch (MCF5XXX_RD_SF_FS(framep))
+ {
+ case 4:
+ ecatch("Error on instruction fetch\n", 0);
+ break;
+ case 8:
+ ecatch("Error on operand write\n", 0);
+ break;
+ case 9:
+ ecatch("Attempted write to write-protected space\n", 0);
+ break;
+ case 12:
+ ecatch("Error on operand read\n", 0);
+ break;
+ default:
+ ecatch("Reserved Fault Status Encoding\n", 0);
+ break;
+ }
+ break;
+ case 3:
+ ecatch("Address Error", MCF5XXX_SF_PC(framep));
+ switch (MCF5XXX_RD_SF_FS(framep))
+ {
+ case 4:
+ ecatch("Error on instruction fetch\n", 0);
+ break;
+ case 8:
+ ecatch("Error on operand write\n", 0);
+ break;
+ case 9:
+ ecatch("Attempted write to write-protected space\n", 0);
+ break;
+ case 12:
+ ecatch("Error on operand read\n", 0);
+ break;
+ default:
+ ecatch("Reserved Fault Status Encoding\n", 0);
+ break;
+ }
+ break;
+ case 4:
+ ecatch("Illegal instruction", MCF5XXX_SF_PC(framep));
+ break;
+ case 8:
+ ecatch("Privilege violation", MCF5XXX_SF_PC(framep));
+ break;
+ case 9:
+ ecatch("Trace Exception", MCF5XXX_SF_PC(framep));
+ break;
+ case 10:
+ ecatch("Unimplemented A-Line Instruction", MCF5XXX_SF_PC(framep));
+ break;
+ case 11:
+ ecatch("Unimplemented F-Line Instruction", MCF5XXX_SF_PC(framep));
+ break;
+ case 12:
+ ecatch("Debug Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 14:
+ ecatch("Format Error", MCF5XXX_SF_PC(framep));
+ break;
+ case 15:
+ ecatch("Unitialized Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 24:
+ ecatch("Spurious Interrupt", MCF5XXX_SF_PC(framep));
+ break;
+ case 25:
+ case 26:
+ case 27:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ ecatch("Autovector interrupt level %d\n", MCF5XXX_RD_SF_VECTOR(framep) - 24);
+ break;
+ case 32:
+ case 33:
+ case 34:
+ case 35:
+ case 36:
+ case 37:
+ case 38:
+ case 39:
+ case 40:
+ case 41:
+ case 42:
+ case 43:
+ case 44:
+ case 45:
+ case 46:
+ case 47:
+ ecatch("TRAP #%d\n", MCF5XXX_RD_SF_VECTOR(framep) - 32);
+ break;
+ case 5:
+ case 6:
+ case 7:
+ case 13:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 48:
+ case 49:
+ case 50:
+ case 51:
+ case 52:
+ case 53:
+ case 54:
+ case 55:
+ case 56:
+ case 57:
+ case 58:
+ case 59:
+ case 60:
+ case 61:
+ case 62:
+ case 63:
+ ecatch("Reserved: #%d\n", MCF5XXX_RD_SF_VECTOR(framep));
+ break;
+ default:
+ ecatch("derivitave handler", MCF5XXX_RD_SF_VECTOR(framep));
+ break;
+ }
+}
+#endif
diff --git a/c/src/lib/libbsp/m68k/mcf52235/startup/linkcmds b/c/src/lib/libbsp/m68k/mcf52235/startup/linkcmds new file mode 100644 index 0000000000..1f3343f69f --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/startup/linkcmds @@ -0,0 +1,173 @@ +/* + * This file contains directives for the GNU linker which are specific + * to the Freescale ColdFire mcf52235 + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE.e + * + * $Id$ + */ + +/* + * Declare some sizes. + */ +_RamBase = DEFINED(_RamBase) ? _RamBase : 0x20000000; +_RamSize = DEFINED(_RamSize) ? _RamSize : 32K; +_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0; +_StackSize = DEFINED(_StackSize) ? _StackSize : 0x400; +_FlashBase = DEFINED(_FlashBase) ? _FlashBase : 0x00000000; + +__IPSBAR = DEFINED(__IPSBAR) ? __IPSBAR : 0x40000000; +_VBR = 0x20000000; + +ENTRY(start) + +MEMORY +{ + sram : ORIGIN = 0x20000000, LENGTH = 32K + flash : ORIGIN = 0x00000000, LENGTH = 256K +} + +SECTIONS +{ + /* + * Text, data and bss segments + */ + .text : { + + *(.text*) + *(.ram_code) + + /* + * C++ constructors/destructors + */ + *(.gnu.linkonce.t.*) + + /* + * Initialization and finalization code. + * + * Various files can provide initialization and finalization + * functions. crtbegin.o and crtend.o are two instances. The + * body of these functions are in .init and .fini sections. We + * accumulate the bodies here, and prepend function prologues + * from crti.o and function epilogues from crtn.o. crti.o must + * be linked first; crtn.o must be linked last. Because these + * are wildcards, it doesn't matter if the user does not + * actually link against crti.o and crtn.o; the linker won't + * look for a file to match a wildcard. The wildcard also + * means that it doesn't matter which directory crti.o and + * crtn.o are in. + */ + PROVIDE (_init = .); + *crti.o(.init) + *(.init) + *crtn.o(.init) + PROVIDE (_fini = .); + *crti.o(.fini) + *(.fini) + *crtn.o(.fini) + + /* + * Special FreeBSD sysctl sections. + */ + . = ALIGN (16); + __start_set_sysctl_set = .; + *(set_sysctl_*); + __stop_set_sysctl_set = ABSOLUTE(.); + *(set_domain_*); + *(set_pseudo_*); + + /* + * C++ constructors/destructors + * + * gcc uses crtbegin.o to find the start of the constructors + * and destructors so we make sure it is first. Because this + * is a wildcard, it doesn't matter if the user does not + * actually link against crtbegin.o; the linker won't look for + * a file to match a wildcard. The wildcard also means that + * it doesn't matter which directory crtbegin.o is in. The + * constructor and destructor list are terminated in + * crtend.o. The same comments apply to it. + */ + . = ALIGN (16); + *crtbegin.o(.ctors) + *(.ctors) + *crtend.o(.ctors) + *crtbegin.o(.dtors) + *(.dtors) + *crtend.o(.dtors) + + /* + * Exception frame info + */ + . = ALIGN (16); + *(.eh_frame) + + /* + * Read-only data + */ + . = ALIGN (16); + _rodata_start = . ; + *(.rodata*) + *(.gnu.linkonce.r*) + + . = ALIGN (16); + + *(.console_gdb_xfer) + *(.bootstrap_data) + . = ALIGN(16); + _estuff = .; + PROVIDE (_etext = .); + } >flash + + .data 0x20000400 : AT (_estuff) + { + PROVIDE( _data_dest_start = . ); + PROVIDE( _copy_start = .); + *(.data) + *(.gnu.linkonce.d*) + *(.gcc_except_table*) + *(.jcr) + . = ALIGN (16); + PROVIDE (_edata = .); + PROVIDE (_copy_end = .); + PROVIDE (_data_dest_end = . ); + } >sram + + _data_src_start = _estuff; + _data_src_end = _data_dest_start + SIZEOF(.data); + + .bss : + { + _clear_start = .; + *(.bss*) + *(COMMON) + . = ALIGN (16); + PROVIDE (_end = .); + + /* + * Starting Stack + */ + . += _StackSize; + . = ALIGN (16); + PROVIDE(_StackInit = .); + + _clear_end = .; + _WorkspaceBase = .; + } >sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + PROVIDE (end_of_all = .); +} diff --git a/c/src/lib/libbsp/m68k/mcf52235/timer/timer.c b/c/src/lib/libbsp/m68k/mcf52235/timer/timer.c new file mode 100644 index 0000000000..fbf075028a --- /dev/null +++ b/c/src/lib/libbsp/m68k/mcf52235/timer/timer.c @@ -0,0 +1,58 @@ +/* + * Timer Init + * + * Use the last DMA timer (DTIM3) as the diagnostic timer. + * + * Author: W. Eric Norum <norume@aps.anl.gov> + * + * COPYRIGHT (c) 2005. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#include <rtems.h> +#include <bsp.h> + +typedef volatile unsigned char vuint8; +typedef volatile unsigned short vuint16; +typedef volatile unsigned long vuint32; + +/* Declare base address of peripherals area */ +#define __IPSBAR ((vuint8 *) 0x40000000) + +void +Timer_initialize(void) +{ + uint32_t preScaleDivisor = bsp_get_CPU_clock_speed() / 1000000; + MCF_DTIM3_DTMR = 0; + MCF_DTIM3_DTMR = MCF_DTIM_DTMR_PS(preScaleDivisor - 1) | + MCF_DTIM_DTMR_CLK_DIV1 | + MCF_DTIM_DTMR_RST; +} + +/* + * Return timer value in microsecond units + */ +int +Read_timer(void) +{ + return MCF_DTIM3_DTCN; +} + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ +rtems_status_code +Empty_function(void) +{ + return RTEMS_SUCCESSFUL; +} + +void +Set_find_average_overhead(rtems_boolean find_flag) +{ +} |