added variant to gen68360 BSP

added genmcf548x BSP

5 files changed, 1164 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspclean.c b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspclean.c
new file mode 100644
index 0000000000..87aeef194c
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspclean.c
@@ -0,0 +1,60 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: bspclean.c                                                |
++-----------------------------------------------------------------+
+| The file contains the BSP cleanup code of the generic MCF548x   |
+| BSP.                                                            |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/bspIo.h>
+
+void bsp_cleanup( void )
+{
+	printk("\nRTEMS exited!\n");
+	for ( ;; )
+	{
+		asm volatile ( " nop " );
+		asm volatile ( " nop " );
+	}
+
+}
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
new file mode 100644
index 0000000000..32c5f53439
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
@@ -0,0 +1,323 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: bspstart.c                                                |
++-----------------------------------------------------------------+
+| The file contains the startup code of generic MCF548x BSP       |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <rtems/libcsupport.h>
+#include <string.h>
+
+char *HeapStart, *HeapEnd;
+unsigned long _HeapSize;
+
+extern uint32_t _CPU_cacr_shadow;
+
+extern char _SdramBase[];
+extern char _BootFlashBase[];
+extern char _CodeFlashBase[];
+extern char _SdramSize[];
+extern char _BootFlashSize[];
+extern char _CodeFlashSize[];
+
+/*
+ * CPU-space access
+ */
+#define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
+#define m68k_set_acr0(_acr0) asm volatile ("movec %0,#0x0004" : : "d" (_acr0))
+#define m68k_set_acr1(_acr1) asm volatile ("movec %0,#0x0005" : : "d" (_acr1))
+#define m68k_set_acr2(_acr2) asm volatile ("movec %0,#0x0005" : : "d" (_acr2))
+#define m68k_set_acr3(_acr3) asm volatile ("movec %0,#0x0007" : : "d" (_acr3))
+
+/*
+ * Set initial cacr mode, mainly enables branch/intruction/data cache and switch off FPU.
+ */
+static uint32_t cacr_mode = (0                                          |
+                             MCF548X_CACR_DEC                           | /* enable data cache */
+                             MCF548X_CACR_BEC                           | /* enable branch cache */
+                             MCF548X_CACR_IEC                           | /* enable instruction cache */
+                             MCF548X_CACR_DDCM(DCACHE_ON_WRIGHTTHROUGH) | /* set data cache mode to write-through */
+                             MCF548X_CACR_DESB                          | /* enable data store buffer */
+                             MCF548X_CACR_DDSP                          | /* data access only in supv. mode */
+                             MCF548X_CACR_IDSP                          | /* instr. access only in supv. mode */
+                             MCF548X_CACR_DF);                            /* disable FPU */
+
+
+/*
+ * Coldfire cacr maintenance functions
+ */
+void _CPU_cacr_set_mode(uint32_t new_cacr_mode)
+{
+rtems_interrupt_level level;
+
+rtems_interrupt_disable(level);
+cacr_mode = new_cacr_mode;
+m68k_set_cacr(new_cacr_mode);
+rtems_interrupt_enable(level);
+}
+
+/*
+ * There is no complete cache lock (only 2 ways of 4 can be locked)
+ */
+void _CPU_cache_freeze_data(void)
+{
+}
+
+void _CPU_cache_unfreeze_data(void)
+{
+}
+
+void _CPU_cache_freeze_instruction(void)
+{
+}
+
+void _CPU_cache_unfreeze_instruction(void)
+{
+}
+
+void _CPU_cache_enable_instruction(void)
+{
+    cacr_mode &= ~(MCF548X_CACR_IDCM);
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_disable_instruction(void)
+{
+    cacr_mode |= MCF548X_CACR_IDCM;
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_invalidate_entire_instruction(void)
+{
+	cacr_mode |= MCF548X_CACR_ICINVA;
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_invalidate_1_instruction_line(const void *addr)
+{
+
+    asm volatile ("cpushl %%ic,(%0)" :: "a" (addr));
+}
+
+void _CPU_cache_enable_data(void)
+{
+    cacr_mode &= ~MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_disable_data(void)
+{
+    cacr_mode |= MCF548X_CACR_DDCM(DCACHE_OFF_IMPRECISE);
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_invalidate_entire_data(void)
+{
+    cacr_mode |= MCF548X_CACR_DCINVA;
+    _CPU_cacr_set_mode(cacr_mode);
+}
+
+void _CPU_cache_invalidate_1_data_line(const void *addr)
+{
+
+   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
+}
+
+void _CPU_cache_flush_1_data_line(const void *addr)
+{
+   asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
+}
+
+void _CPU_cache_flush_entire_data(void)
+{
+register uint32_t way_cnt, set_cnt, addr;
+
+asm volatile("nop");
+
+for(way_cnt=0; way_cnt<4; way_cnt++)
+  {
+  for(addr=0,set_cnt=0; set_cnt<512; set_cnt++,addr+=0x10)
+    {
+    asm volatile ("cpushl %%dc,(%0)" :: "a" (addr));
+    }
+  addr=way_cnt;
+  }
+}
+
+/*
+ *  Use the shared implementations of the following routines
+ */
+
+void bsp_predriver_hook()
+{
+	/* Do nothing */
+}
+
+void bsp_postdriver_hook(void);
+void bsp_libc_init( void *, uint32_t, int );
+void bsp_pretasking_hook(void);		/* m68k version */
+
+void bsp_calc_mem_layout()
+{
+  /*
+   * these labels (!) are defined in the linker command file
+   * or when the linker is invoked
+   * NOTE: the information(size) is the address of the object,
+   * not the object otself
+   */
+  extern char _TopRamReserved [];
+  extern char _WorkspaceBase [];
+
+  /*
+   * compute the memory layout:
+   * - first unused address is Workspace start
+   * - Heap starts at end of workspace
+   * - Heap ends at end of memory - reserved memory area
+   */
+  Configuration.work_space_start = _WorkspaceBase;
+
+  HeapStart = ((char *)Configuration.work_space_start +
+                    Configuration.work_space_size);
+
+  HeapEnd = (void *)(RAM_END - (uint32_t)_TopRamReserved);
+
+  _HeapSize = HeapEnd - HeapStart;
+}
+
+
+/*
+ * Coldfire acr and mmu settings
+ */
+ void acr_mmu_mapping(void)
+   {
+
+  /*
+   * Cache disabled for internal register area (256 kB).
+   * Choose the smallest maskable size of 1MB.
+   */
+  m68k_set_acr0(MCF548X_ACR_BA((uint32_t)(__MBAR))                           |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(0xFFFFF))                   |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_OFF_PRECISE));
+
+#ifdef M5484FIREENGINE
+
+
+  /*
+   * Cache enabled for entire SDRAM (64 MB)
+   */
+  m68k_set_acr1(MCF548X_ACR_BA((uint32_t)(_SdramBase))                       |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_SdramSize - 1))            |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_WRIGHTTHROUGH));
+
+  /*
+   * Cache enabled for entire boot flash (2 MB)
+   */
+  m68k_set_acr2(MCF548X_ACR_BA((uint32_t)(_BootFlashBase))                   |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_BootFlashSize - 1))        |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_COPYBACK));
+
+  /*
+   * Cache enabled for entire code flash (16 MB)
+   */
+  m68k_set_acr3(MCF548X_ACR_BA((uint32_t)(_CodeFlashBase))                   |
+                MCF548X_ACR_ADMSK_AMM((uint32_t)(_CodeFlashSize - 1))        |
+                MCF548X_ACR_E                                                |
+                MCF548X_ACR_SP               /* supervisor protection */     |
+                MCF548X_ACR_S(S_ACCESS_SUPV) /* always in supervisor mode */ |
+                MCF548X_ACR_CM(CM_ON_COPYBACK));
+#endif
+
+   }
+
+/*
+ *  bsp_start
+ *
+ *  This routine does the bulk of the system initialisation.
+ */
+void bsp_start( void )
+{
+  extern char _RamSize[];
+  extern unsigned long  _M68k_Ramsize;
+
+  _M68k_Ramsize = (unsigned long)_RamSize;		/* RAM size set in linker script */
+
+  /*
+   *  Allocate the memory for the RTEMS Work Space and Heap.  This can come from
+   *  a variety of places: hard coded address, malloc'ed from outside
+   *  RTEMS world (e.g. simulator or primitive memory manager), or (as
+   *  typically done by stock BSPs) by subtracting the required amount
+   *  of work space from the last physical address on the CPU board.
+   */
+  bsp_calc_mem_layout();
+
+  /*
+   * do mapping of acr's and/or mmu
+   */
+  acr_mmu_mapping();
+
+  /*
+   * Load the shadow variable of cacr with initial mode and write it to the cacr.
+   * Interrupts are still disabled, so there is no need for surrounding rtems_interrupt_enable()/rtems_interrupt_disable()
+   */
+  _CPU_cacr_shadow = cacr_mode;
+  m68k_set_cacr(_CPU_cacr_shadow);
+
+}
+
+
+/*
+ * Get the XLB clock speed
+ */
+uint32_t get_CPU_clock_speed(void)
+{
+    return (uint32_t)BSP_CPU_CLOCK_SPEED;
+}
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/init548x.c b/c/src/lib/libbsp/m68k/genmcf548x/startup/init548x.c
new file mode 100644
index 0000000000..22541781c2
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/init548x.c
@@ -0,0 +1,317 @@
+/*===============================================================*\

+| Project: RTEMS generic mcf548x BSP                              |

++-----------------------------------------------------------------+

+| File: init548x.c                                                |

++-----------------------------------------------------------------+

+| The file contains the c part of MCF548x init code               |

++-----------------------------------------------------------------+

+|                    Copyright (c) 2007                           |

+|                    Embedded Brains GmbH                         |

+|                    Obere Lagerstr. 30                           |

+|                    D-82178 Puchheim                             |

+|                    Germany                                      |

+|                    rtems@embedded-brains.de                     |

++-----------------------------------------------------------------+

+|                                                                 |

+| Parts of the code has been derived from the "dBUG source code"  |

+| package Freescale is providing for M548X EVBs. The usage of     |

+| the modified or unmodified code and it's integration into the   |

+| generic mcf548x BSP has been done according to the Freescale    |

+| license terms.                                                  |

+|                                                                 |

+| The Freescale license terms can be reviewed in the file         |

+|                                                                 |

+|    Freescale_license.txt                                        |

+|                                                                 |

++-----------------------------------------------------------------+

+|                                                                 |

+| The generic mcf548x BSP has been developed on the basic         |

+| structures and modules of the av5282 BSP.                       |

+|                                                                 |

++-----------------------------------------------------------------+

+|                                                                 |

+| The license and distribution terms for this file may be         |

+| found in the file LICENSE in this distribution or at            |

+|                                                                 |

+| http://www.rtems.com/license/LICENSE.                           |

+|                                                                 |

++-----------------------------------------------------------------+

+|                                                                 |

+|   date                      history                        ID   |

+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |

+| 12.11.07                    1.0                            ras  |

+|                                                                 |

+\*===============================================================*/

+

+#include <rtems.h>

+#include <bsp.h>

+

+#define SYSTEM_PERIOD			10  	/* system bus period in ns */

+

+/* SDRAM Timing Parameters */

+#define SDRAM_TWR		    	2  		/* in clocks */

+#define SDRAM_CASL		    	2.5 	/* in clocks */

+#define SDRAM_TRCD		    	20		/* in ns */

+#define SDRAM_TRP		    	20		/* in ns */

+#define SDRAM_TRFC		    	75		/* in ns */

+#define SDRAM_TREFI		    	7800	/* in ns */

+

+extern uint8_t _DataRom[];

+extern uint8_t _DataRam[];

+extern uint8_t _DataEnd[];

+extern uint8_t _BssStart[];

+extern uint8_t _BssEnd[];

+extern uint8_t _BootFlashBase[];

+extern uint8_t _CodeFlashBase[];

+extern uint8_t _RamBase[];

+extern uint32_t InterruptVectorTable[];

+extern uint32_t _VectorRam[];

+

+void gpio_init(void);

+void fbcs_init(void);

+void sdramc_init(void);

+void mcf548x_init(void);

+

+

+void mcf548x_init(void)

+    {

+    uint32_t n;

+    uint8_t *dp, *sp;

+

+    /* set XLB arbiter timeouts */

+#ifdef M5484FIREENGINE

+    /* set XLB arbiter timeouts */

+    MCF548X_XLB_ADRTO = 0x00000100;

+    MCF548X_XLB_DATTO = 0x00000100;

+    MCF548X_XLB_BUSTO = 0x00000100;

+#endif

+

+    gpio_init();

+    fbcs_init();

+    sdramc_init();

+

+    /* Copy the vector table to RAM */

+    if (_VectorRam != InterruptVectorTable)

+    {

+	for( n = 0; n < 256; n++)

+	  {

+      _VectorRam[n] = InterruptVectorTable[n];

+	  }

+    }

+

+    m68k_set_vbr((uint32_t)_VectorRam);

+

+    /* Move initialized data from ROM to RAM. */

+    if (_DataRom != _DataRam)

+    {

+		n = _DataEnd - _DataRam;

+        sp = (uint8_t *)_DataRom;

+        dp = (uint8_t *)_DataRam;

+		while(n--)

+           *dp++ = *sp++;

+     }

+

+    /* Zero uninitialized data */

+    if (_BssStart != _BssEnd)

+    {

+		n = _BssEnd - _BssStart;

+        sp = (uint8_t *)_BssStart;

+        while (n--)

+            *sp++ = 0;

+    }

+

+}

+/********************************************************************/

+void

+fbcs_init (void)

+{

+#ifdef M5484FIREENGINE

+

+volatile uint32_t cscr, clk_ratio, fb_period, ws;

+

+/* boot flash already valid ? */

+if(!(MCF548X_FBCS_CSMR0 & MCF548X_FBCS_CSMR_V))

+  {

+

+    /*

+     * Boot Flash

+     */

+    MCF548X_FBCS_CSAR0 = MCF548X_FBCS_CSAR_BA((uint32_t)(_BootFlashBase));

+

+    cscr = (0

+            | MCF548X_FBCS_CSCR_ASET(1)

+            | MCF548X_FBCS_CSCR_WRAH(0)

+            | MCF548X_FBCS_CSCR_RDAH(0)

+            | MCF548X_FBCS_CSCR_AA

+            | MCF548X_FBCS_CSCR_PS_16);

+

+    /*

+     * Determine the necessary wait states based on the defined system

+     * period (XLB clock period) and the CLKIN to XLB ratio.

+     * The boot flash has a max access time of 110ns.

+     */

+    clk_ratio = (MCF548X_PCI_PCIGSCR >> 24) & 0x7;

+    fb_period = SYSTEM_PERIOD * clk_ratio;

+    ws = 110 / fb_period;

+

+    MCF548X_FBCS_CSCR0 = cscr | MCF548X_FBCS_CSCR_WS(ws);

+    MCF548X_FBCS_CSMR0 = (0

+                          | MCF548X_FBCS_CSMR_BAM_2M

+                          | MCF548X_FBCS_CSMR_V);

+

+  }

+

+/* code flash already valid ? */

+if(!(MCF548X_FBCS_CSMR1 & MCF548X_FBCS_CSMR_V))

+  {

+

+    /*

+     * Code Flash

+     */

+    MCF548X_FBCS_CSAR1 = MCF548X_FBCS_CSAR_BA((uint32_t)(_CodeFlashBase));

+

+    /*

+     * Determine the necessary wait states based on the defined system

+     * period (XLB clock period) and the CLKIN to XLB ratio.

+     * The user/code flash has a max access time of 120ns.

+     */

+    ws = 120 / fb_period;

+    MCF548X_FBCS_CSCR1 = cscr | MCF548X_FBCS_CSCR_WS(ws);

+    MCF548X_FBCS_CSMR1 = (0

+                          | MCF548X_FBCS_CSMR_BAM_16M

+                          | MCF548X_FBCS_CSMR_V);

+    }

+

+#endif

+}

+

+/********************************************************************/

+void

+sdramc_init (void)

+{

+

+	/*

+	 * Check to see if the SDRAM has already been initialized

+	 * by a run control tool

+	 */

+	if (!(MCF548X_SDRAMC_SDCR & MCF548X_SDRAMC_SDCR_REF))

+	{

+		/*

+         * Basic configuration and initialization

+         */

+		MCF548X_SDRAMC_SDRAMDS = (0

+			| MCF548X_SDRAMC_SDRAMDS_SB_E(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)

+			| MCF548X_SDRAMC_SDRAMDS_SB_C(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)

+			| MCF548X_SDRAMC_SDRAMDS_SB_A(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)

+			| MCF548X_SDRAMC_SDRAMDS_SB_S(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)

+			| MCF548X_SDRAMC_SDRAMDS_SB_D(MCF548X_SDRAMC_SDRAMDS_DRIVE_8MA)

+            );

+        MCF548X_SDRAMC_CS0CFG = (0

+            | MCF548X_SDRAMC_CSnCFG_CSBA((uint32_t)(_RamBase))

+            | MCF548X_SDRAMC_CSnCFG_CSSZ(MCF548X_SDRAMC_CSnCFG_CSSZ_64MBYTE)

+            );

+        MCF548X_SDRAMC_SDCFG1 = (0

+			| MCF548X_SDRAMC_SDCFG1_SRD2RW(7)

+			| MCF548X_SDRAMC_SDCFG1_SWT2RD(SDRAM_TWR + 1)

+			| MCF548X_SDRAMC_SDCFG1_RDLAT((int)((SDRAM_CASL*2) + 2))

+			| MCF548X_SDRAMC_SDCFG1_ACT2RW((int)(((SDRAM_TRCD/SYSTEM_PERIOD) - 1) + 0.5))

+			| MCF548X_SDRAMC_SDCFG1_PRE2ACT((int)(((SDRAM_TRP/SYSTEM_PERIOD) - 1) + 0.5))

+			| MCF548X_SDRAMC_SDCFG1_REF2ACT((int)(((SDRAM_TRFC/SYSTEM_PERIOD) - 1) + 0.5))

+			| MCF548X_SDRAMC_SDCFG1_WTLAT(3)

+            );

+		MCF548X_SDRAMC_SDCFG2 = (0

+			| MCF548X_SDRAMC_SDCFG2_BRD2PRE(4)

+			| MCF548X_SDRAMC_SDCFG2_BWT2RW(6)

+			| MCF548X_SDRAMC_SDCFG2_BRD2WT(7)

+			| MCF548X_SDRAMC_SDCFG2_BL(7)

+            );

+

+		/*

+         * Precharge and enable write to SDMR

+         */

+        MCF548X_SDRAMC_SDCR = (0

+			| MCF548X_SDRAMC_SDCR_MODE_EN

+			| MCF548X_SDRAMC_SDCR_CKE

+			| MCF548X_SDRAMC_SDCR_DDR

+			| MCF548X_SDRAMC_SDCR_MUX(1)

+			| MCF548X_SDRAMC_SDCR_RCNT((int)(((SDRAM_TREFI/(SYSTEM_PERIOD*64)) - 1) + 0.5))

+			| MCF548X_SDRAMC_SDCR_IPALL

+            );

+

+		/*

+         * Write extended mode register

+         */

+		MCF548X_SDRAMC_SDMR = (0

+			| MCF548X_SDRAMC_SDMR_BNKAD_LEMR

+			| MCF548X_SDRAMC_SDMR_AD(0x0)

+			| MCF548X_SDRAMC_SDMR_CMD

+            );

+

+		/*

+         * Write mode register and reset DLL

+         */

+		MCF548X_SDRAMC_SDMR = (0

+			| MCF548X_SDRAMC_SDMR_BNKAD_LMR

+			| MCF548X_SDRAMC_SDMR_AD(0x163)

+			| MCF548X_SDRAMC_SDMR_CMD

+            );

+

+		/*

+         * Execute a PALL command

+         */

+		MCF548X_SDRAMC_SDCR |=MCF548X_SDRAMC_SDCR_IPALL;

+

+		/*

+         * Perform two REF cycles

+         */

+		MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;

+		MCF548X_SDRAMC_SDCR |= MCF548X_SDRAMC_SDCR_IREF;

+

+		/*

+         * Write mode register and clear reset DLL

+         */

+		MCF548X_SDRAMC_SDMR = (0

+			| MCF548X_SDRAMC_SDMR_BNKAD_LMR

+			| MCF548X_SDRAMC_SDMR_AD(0x063)

+			| MCF548X_SDRAMC_SDMR_CMD

+            );

+

+		/*

+         * Enable auto refresh and lock SDMR

+         */

+		MCF548X_SDRAMC_SDCR &= ~MCF548X_SDRAMC_SDCR_MODE_EN;

+        MCF548X_SDRAMC_SDCR |= (0

+			| MCF548X_SDRAMC_SDCR_REF

+			| MCF548X_SDRAMC_SDCR_DQS_OE(0xF)

+            );

+    }

+

+}

+

+/********************************************************************/

+void

+gpio_init(void)

+{

+

+#ifdef M5484FIREENGINE

+

+    /*

+     * Enable Ethernet signals so that, if a cable is plugged into

+     * the ports, the lines won't be floating and potentially cause

+     * erroneous transmissions

+     */

+    MCF548X_GPIO_PAR_FECI2CIRQ = (0

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDC_EMDC

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MDIO_EMDIO

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E1MII

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E17

+        );

+    MCF548X_GPIO_PAR_FECI2CIRQ = (0

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDC

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MDIO

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E0MII

+        | MCF548X_GPIO_PAR_FECI2CIRQ_PAR_E07

+        );

+

+#endif

+}

diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds b/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds
new file mode 100644
index 0000000000..93edba1b72
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds
@@ -0,0 +1,232 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: linkcmd                                                   |
++-----------------------------------------------------------------+
+| The file contains the linker directives for the generic MCF548x |
+| BSP to be used with an m5484FireEngine EVB to load and execute  |
+| code in the RAM.                                                |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+/* 
+ * Location and size of on-chip devices
+ */
+_SdramBase          = DEFINED(_SdramBase)        ? _SdramBase        : 0x00000000;
+_SdramSize	    = DEFINED(_SdramSize)        ? _SdramSize        : (64 * 1024 * 1024);
+_SysSramBase        = DEFINED(_SysSramBase)      ? _SysSramBase      : __MBAR + 0x00010000;
+_SysSramSize	    = DEFINED(_SysSramSize)      ? _SysSramSize      : (32 * 1024);
+_McdapiBase         = DEFINED(_McdapiBase)       ? _McdapiBase       : _SysSramBase;                 
+_McdapiSize         = DEFINED(_McdapiSize)       ? _McdapiSize       : (12 * 1024);                  
+_CoreSramBase0      = DEFINED(_CoreSramBase0)    ? _CoreSramBase0    : 0x20000000;
+_CoreSramBase1      = DEFINED(_CoreSramBase1)    ? _CoreSramBase1    : 0x20001000;
+_CoreSramSize0      = DEFINED(_CoreSramSize0)    ? _CoreSramSize0    : (4 * 1024);
+_CoreSramSize1      = DEFINED(_CoreSramSize1)    ? _CoreSramSize1    : (4 * 1024);
+_BootFlashBase      = DEFINED(_BootFlashBase)    ? _BootFlashBase    : 0xFF800000;
+_BootFlashSize      = DEFINED(_BootFlashSize)    ? _BootFlashSize    : (2 * 1024 * 1024);
+_CodeFlashBase      = DEFINED(_CodeFlashBase)    ? _CodeFlashBase    : 0xE0000000;
+_CodeFlashSize      = DEFINED(_CodeFlashSize)    ? _CodeFlashSize    : (16 * 1024 * 1024);
+
+_VectorRam          = DEFINED(_VectorRam)        ? _VectorRam        : _SdramBase;
+_DataRam            = DEFINED(_DataRam)          ? _DataRam          : _data_dest_start;
+_DataRom            = DEFINED(_DataRom)          ? _DataRom          : _data_src_start;
+_DataEnd            = DEFINED(_DataEnd)          ? _DataEnd          : _data_dest_end;
+_BssStart           = DEFINED(_BssStart)         ? _BssStart         : _clear_start;
+_BssEnd             = DEFINED(_BssEnd)           ? _BssEnd           : _clear_end;
+_SpInit             = DEFINED(_SpInit)           ? _SpInit           : _EndInitStackSpace;
+_InitPc             = DEFINED(_InitPc)           ? _InitPc           : _SdramBase + 0x400;
+
+_InitStackSize      = DEFINED(StackSize)         ? StackSize         : 0x800;  /* 2 kB   */
+_TopRamReserved     = DEFINED(_TopRamReserved)   ? _TopRamReserved   : 0;
+
+_RamBase            = DEFINED(_SdramBase)        ? _SdramBase        : _SdramBase;
+_RamSize            = DEFINED(_SdramSize)        ? _SdramSize        : _SdramSize;
+_VBR                = DEFINED(_VBR)              ? _VBR              : _RamBase;
+
+__MBAR	            = DEFINED(__MBAR)            ? __MBAR            : 0x10000000;
+
+ENTRY(start)
+MEMORY
+{
+    sdram      : ORIGIN = 0x400     , LENGTH = 64M - 0x400
+    code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
+    boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
+}
+
+SECTIONS
+{
+     
+    _header_offset = 0;
+    
+    /*
+     * Text, data and bss segments .vectors          
+     */    
+    .vectors : {
+                 *(.vectors*)
+               } >sdram
+    .text : {
+       
+        *(.text*)
+        *(.ram_code)
+
+        /*
+         * C++ constructors/destructors
+         */
+        *(.gnu.linkonce.t.*)
+
+        /*
+         * Initialization and finalization code.
+              *
+              * Various files can provide initialization and finalization
+         * functions.  crtbegin.o and crtend.o are two instances. The
+         * body of these functions are in .init and .fini sections. We
+         * accumulate the bodies here, and prepend function prologues
+         * from crti.o and function epilogues from crtn.o. crti.o must
+         * be linked first; crtn.o must be linked last.  Because these
+         * are wildcards, it doesn't matter if the user does not
+         * actually link against crti.o and crtn.o; the linker won't
+         * look for a file to match a wildcard.  The wildcard also
+         * means that it doesn't matter which directory crti.o and
+         * crtn.o are in. 
+         */
+        PROVIDE (_init = .);
+        *crti.o(.init)
+        *(.init)
+        *crtn.o(.init)
+        PROVIDE (_fini = .);
+        *crti.o(.fini)
+        *(.fini)
+        *crtn.o(.fini)
+
+        /*
+         * Special FreeBSD sysctl sections.
+         */
+        . = ALIGN (16);
+        __start_set_sysctl_set = .;
+        *(set_sysctl_*);
+        __stop_set_sysctl_set = ABSOLUTE(.);
+        *(set_domain_*);
+        *(set_pseudo_*);
+
+
+        /*
+         * C++ constructors/destructors
+         *
+         * gcc uses crtbegin.o to find the start of the constructors
+         * and destructors so we make sure it is first.  Because this
+         * is a wildcard, it doesn't matter if the user does not
+         * actually link against crtbegin.o; the linker won't look for
+         * a file to match a wildcard.  The wildcard also means that
+         * it doesn't matter which directory crtbegin.o is in. The
+         * constructor and destructor list are terminated in
+         * crtend.o.  The same comments apply to it.
+         */
+        . = ALIGN (16);
+        *crtbegin.o(.ctors)
+        *(.ctors)
+        *crtend.o(.ctors)
+        *crtbegin.o(.dtors)
+        *(.dtors)
+        *crtend.o(.dtors)
+
+        /*
+         * Exception frame info
+         */
+        . = ALIGN (16);
+        *(.eh_frame)
+
+        /*
+         * Read-only data
+         */
+        . = ALIGN (16);
+        _rodata_start = . ;
+        *(.rodata*)
+        *(.gnu.linkonce.r*)
+        
+        . = ALIGN (16);
+
+        *(.console_gdb_xfer)
+        *(.bootstrap_data)
+        . = ALIGN(16);
+        _estuff = .;
+    PROVIDE (_etext = .);
+    } >sdram
+        
+        .data : {
+        /*.data : {*/
+            PROVIDE( _data_dest_start = . );
+            PROVIDE( _copy_start = .);
+            *(.data*)
+            *(.gnu.linkonce.d*)
+            *(.gcc_except_table)
+            *(.jcr)
+            . = ALIGN (16);
+            PROVIDE (_edata = .);
+        PROVIDE (_copy_end = .);
+        PROVIDE (_data_dest_end = . );
+        } >sdram
+
+        _data_src_start = _etext; /*LOADADDR(.data);*/
+        _data_src_end = _data_src_start + SIZEOF(.data);        
+        
+        .bss : {
+               PROVIDE (_clear_start = .);
+                *(.bss*)
+                *(COMMON)
+                . = ALIGN (16);
+                PROVIDE (end = .);
+                PROVIDE (_clear_end = .);
+                . = ALIGN (4);
+                PROVIDE (_StartInitStackSpace = .);
+                /*. = _StartInitStackSpace + _InitStackSize;*/
+                . += _InitStackSize;
+                PROVIDE (_EndInitStackSpace = .);
+                PROVIDE (_WorkspaceBase = .);
+        } >sdram
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+
+PROVIDE (end_of_all = .);  
+}
diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.m5484FireEngine.flash b/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.m5484FireEngine.flash
new file mode 100644
index 0000000000..5dcb520261
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/linkcmds.m5484FireEngine.flash
@@ -0,0 +1,232 @@
+/*===============================================================*\
+| Project: RTEMS generic mcf548x BSP                              |
++-----------------------------------------------------------------+
+| File: linkcmd.m5484FireEngine.flash                             |
++-----------------------------------------------------------------+
+| The file contains the linker directives for the generic MCF548x |
+| BSP to be used with an m5484FireEngine EVB to load and execute  |
+| code in the boot FLASH.                                         |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2007                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+|                                                                 |
+| Parts of the code has been derived from the "dBUG source code"  |
+| package Freescale is providing for M548X EVBs. The usage of     |
+| the modified or unmodified code and it's integration into the   |
+| generic mcf548x BSP has been done according to the Freescale    |
+| license terms.                                                  |
+|                                                                 |
+| The Freescale license terms can be reviewed in the file         |
+|                                                                 |
+|    Freescale_license.txt                                        |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The generic mcf548x BSP has been developed on the basic         |
+| structures and modules of the av5282 BSP.                       |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.com/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+|                                                                 |
+|   date                      history                        ID   |
+| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
+| 12.11.07                    1.0                            ras  |
+|                                                                 |
+\*===============================================================*/
+
+/* 
+ * Location and size of on-chip devices
+ */
+_SdramBase          = DEFINED(_SdramBase)        ? _SdramBase        : 0x00000000;
+_SdramSize	    = DEFINED(_SdramSize)        ? _SdramSize        : (64 * 1024 * 1024);
+_SysSramBase        = DEFINED(_SysSramBase)      ? _SysSramBase      : __MBAR + 0x00010000;
+_SysSramSize	    = DEFINED(_SysSramSize)      ? _SysSramSize      : (32 * 1024);
+_McdapiBase         = DEFINED(_McdapiBase)       ? _McdapiBase       : _SysSramBase;                 
+_McdapiSize         = DEFINED(_McdapiSize)       ? _McdapiSize       : (12 * 1024);                  
+_CoreSramBase0      = DEFINED(_CoreSramBase0)    ? _CoreSramBase0    : 0x20000000;
+_CoreSramBase1      = DEFINED(_CoreSramBase1)    ? _CoreSramBase1    : 0x20001000;
+_CoreSramSize0      = DEFINED(_CoreSramSize0)    ? _CoreSramSize0    : (4 * 1024);
+_CoreSramSize1      = DEFINED(_CoreSramSize1)    ? _CoreSramSize1    : (4 * 1024);
+_BootFlashBase      = DEFINED(_BootFlashBase)    ? _BootFlashBase    : 0xFF800000;
+_BootFlashSize      = DEFINED(_BootFlashSize)    ? _BootFlashSize    : (2 * 1024 * 1024);
+_CodeFlashBase      = DEFINED(_CodeFlashBase)    ? _CodeFlashBase    : 0xE0000000;
+_CodeFlashSize      = DEFINED(_CodeFlashSize)    ? _CodeFlashSize    : (16 * 1024 * 1024);
+
+_VectorRam          = DEFINED(_VectorRam)        ? _VectorRam        : _SdramBase;
+_DataRam            = DEFINED(_DataRam)          ? _DataRam          : _data_dest_start;
+_DataRom            = DEFINED(_DataRom)          ? _DataRom          : _data_src_start;
+_DataEnd            = DEFINED(_DataEnd)          ? _DataEnd          : _data_dest_end;
+_BssStart           = DEFINED(_BssStart)         ? _BssStart         : _clear_start;
+_BssEnd             = DEFINED(_BssEnd)           ? _BssEnd           : _clear_end;
+_SpInit             = DEFINED(_SpInit)           ? _SpInit           : _EndInitStackSpace;
+_InitPc             = DEFINED(_InitPc)           ? _InitPc           : _SdramBase + 0x400;
+
+_InitStackSize      = DEFINED(StackSize)         ? StackSize         : 0x2000;  /* 8 kB   */
+_TopRamReserved     = DEFINED(_TopRamReserved)   ? _TopRamReserved   : 0;
+
+_RamBase            = DEFINED(_SdramBase)        ? _SdramBase        : _SdramBase;
+_RamSize            = DEFINED(_SdramSize)        ? _SdramSize        : _SdramSize;
+_VBR                = DEFINED(_VBR)              ? _VBR              : _RamBase;
+
+__MBAR	            = DEFINED(__MBAR)            ? __MBAR            : 0x10000000;
+
+ENTRY(start)
+MEMORY
+{
+    sdram      : ORIGIN = 0x400     , LENGTH = 64M - 0x400
+    code_flash : ORIGIN = 0xE0000000, LENGTH = 16M
+    boot_flash : ORIGIN = 0xFF800000, LENGTH = 2M
+}
+
+SECTIONS
+{
+     
+    _header_offset = 0;
+    
+    /*
+     * Text, data and bss segments .vectors          
+     */    
+    .vectors : {
+                 *(.vectors*)
+               } >boot_flash
+    .text : {
+       
+        *(.text*)
+        *(.ram_code)
+
+        /*
+         * C++ constructors/destructors
+         */
+        *(.gnu.linkonce.t.*)
+
+        /*
+         * Initialization and finalization code.
+              *
+              * Various files can provide initialization and finalization
+         * functions.  crtbegin.o and crtend.o are two instances. The
+         * body of these functions are in .init and .fini sections. We
+         * accumulate the bodies here, and prepend function prologues
+         * from crti.o and function epilogues from crtn.o. crti.o must
+         * be linked first; crtn.o must be linked last.  Because these
+         * are wildcards, it doesn't matter if the user does not
+         * actually link against crti.o and crtn.o; the linker won't
+         * look for a file to match a wildcard.  The wildcard also
+         * means that it doesn't matter which directory crti.o and
+         * crtn.o are in. 
+         */
+        PROVIDE (_init = .);
+        *crti.o(.init)
+        *(.init)
+        *crtn.o(.init)
+        PROVIDE (_fini = .);
+        *crti.o(.fini)
+        *(.fini)
+        *crtn.o(.fini)
+
+        /*
+         * Special FreeBSD sysctl sections.
+         */
+        . = ALIGN (16);
+        __start_set_sysctl_set = .;
+        *(set_sysctl_*);
+        __stop_set_sysctl_set = ABSOLUTE(.);
+        *(set_domain_*);
+        *(set_pseudo_*);
+
+
+        /*
+         * C++ constructors/destructors
+         *
+         * gcc uses crtbegin.o to find the start of the constructors
+         * and destructors so we make sure it is first.  Because this
+         * is a wildcard, it doesn't matter if the user does not
+         * actually link against crtbegin.o; the linker won't look for
+         * a file to match a wildcard.  The wildcard also means that
+         * it doesn't matter which directory crtbegin.o is in. The
+         * constructor and destructor list are terminated in
+         * crtend.o.  The same comments apply to it.
+         */
+        . = ALIGN (16);
+        *crtbegin.o(.ctors)
+        *(.ctors)
+        *crtend.o(.ctors)
+        *crtbegin.o(.dtors)
+        *(.dtors)
+        *crtend.o(.dtors)
+
+        /*
+         * Exception frame info
+         */
+        . = ALIGN (16);
+        *(.eh_frame)
+
+        /*
+         * Read-only data
+         */
+        . = ALIGN (16);
+        _rodata_start = . ;
+        *(.rodata*)
+        *(.gnu.linkonce.r*)
+        
+        . = ALIGN (16);
+
+        *(.console_gdb_xfer)
+        *(.bootstrap_data)
+        . = ALIGN(16);
+        _estuff = .;
+    PROVIDE (_etext = .);
+    } >boot_flash
+        
+        .data : AT(LOADADDR(.text) + SIZEOF(.text)) {
+        /*.data : {*/
+            PROVIDE( _data_dest_start = . );
+            PROVIDE( _copy_start = .);
+            *(.data*)
+            *(.gnu.linkonce.d*)
+            *(.gcc_except_table)
+            *(.jcr)
+            . = ALIGN (16);
+            PROVIDE (_edata = .);
+        PROVIDE (_copy_end = .);
+        PROVIDE (_data_dest_end = . );
+        } >sdram
+
+        _data_src_start = _etext; /*LOADADDR(.data);*/
+        _data_src_end = _data_src_start + SIZEOF(.data);        
+        
+        .bss : {
+               PROVIDE (_clear_start = .);
+                *(.bss*)
+                *(COMMON)
+                . = ALIGN (16);
+                PROVIDE (end = .);
+                PROVIDE (_clear_end = .);
+                . = ALIGN (4);
+                PROVIDE (_StartInitStackSpace = .);
+                /*. = _StartInitStackSpace + _InitStackSize;*/
+                . += _InitStackSize;
+                PROVIDE (_EndInitStackSpace = .);
+                PROVIDE (_WorkspaceBase = .);
+        } >sdram
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+
+PROVIDE (end_of_all = .);  
+}