added variant to gen68360 BSP

added genmcf548x BSP

1 files changed, 175 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
index 37fd35f5e2..f1f0f26dce 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
@@ -14,6 +14,13 @@
 #include <bsp.h>
 #include <rtems/m68k/m68360.h>
 
+
+/*
+ * Declare the m360 structure here for the benefit of the debugger
+ */
+
+volatile m360_t m360;
+
 /*
  * Send a command to the CPM RISC processer
  */
@@ -335,6 +342,174 @@ void _Init68360 (void)
 	 *	BCLRO* arbitration level 3
 	 */
 
+#elif defined(PGH360)
+	/*
+	 * Step 6: Is this a power-up reset?
+	 * For now we just ignore this and do *all* the steps
+	 * Someday we might want to:
+	 *	if (Hard, Loss of Clock, Power-up)
+	 *		Do all steps
+	 *	else if (Double bus fault, watchdog or soft reset)
+	 *		Skip to step 12
+	 *	else (must be a CPU32+ reset command)
+	 *		Skip to step 14
+	 */
+
+	/*
+	 * Step 7: Deal with clock synthesizer
+	 * HARDWARE:
+	 *	Change if you're not using an external 25 MHz oscillator.
+	 */
+	m360.clkocr = 0x8e;	/* No more writes, CLKO1=1/3, CLKO2=off */
+	/*
+	 * adjust crystal to average between 4.19 MHz and 4.00 MHz
+	 * reprogram pll
+	 */
+	m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
+					/* LPSTOP slowdown, PLL /128*??? */
+	m360.cdvcr = 0x8000;	/* No more writes, no clock division */
+
+	/*
+	 * Step 8: Initialize system protection
+	 *	Enable watchdog
+	 *	Watchdog causes system reset
+	 *	128 sec. watchdog timeout
+	 *	Enable double bus fault monitor
+	 *	Enable bus monitor external
+	 *	128 clocks for external timeout
+	 */
+	m360.sypcr = 0xEF;
+	/*
+	 * also initialize the SWP bit in PITR to 1
+	 */
+	m360.pitr |= 0x0200;
+	/*
+	 * and trigger SWSR twice to ensure, that interval starts right now
+	 */
+	m360.swsr = 0x55;
+	m360.swsr = 0xAA;
+	m360.swsr = 0x55;
+	m360.swsr = 0xAA;
+	/*
+	 * Step 9: Clear parameter RAM and reset communication processor module
+	 */
+	for (i = 0 ; i < 192  ; i += sizeof (long)) {
+		*((long *)((char *)&m360 + 0xC00 + i)) = 0;
+		*((long *)((char *)&m360 + 0xD00 + i)) = 0;
+		*((long *)((char *)&m360 + 0xE00 + i)) = 0;
+		*((long *)((char *)&m360 + 0xF00 + i)) = 0;
+	}
+	M360ExecuteRISC (M360_CR_RST);
+
+	/*
+	 * Step 10: Write PEPAR
+	 *	SINTOUT not used (CPU32+ mode)
+	 *	CF1MODE=00 (CONFIG1 input)
+	 *	IPIPE1
+	 *	WE0-3
+	 *	OE* output
+	 *	CAS2* / CAS3*
+	 *	CAS0* / CAS1*
+	 *	CS7*
+	 *	AVEC*
+	 * HARDWARE:
+	 *	Change if you are using a different memory configuration
+	 *	(static RAM, external address multiplexing, etc).
+	 */
+	m360.pepar = 0x0080;
+	/*
+	 * Step 11: Remap Chip Select 0 (CS0*), set up GMR
+	 *	no DRAM support
+	 * HARDWARE:
+	 *	Change if you are using a different memory configuration
+	 */
+	m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
+		   M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
+	           M360_GMR_GAMX;
+
+	m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+							M360_MEMC_BR_V;
+	m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
+							M360_MEMC_OR_8BIT;
+
+	/*
+	 * Step 12: Initialize the system RAM
+	 *	Set up option/base registers
+	 *		16 MB DRAM
+	 *		1 wait state
+	 * HARDWARE:
+	 *	Change if you are using a different memory configuration
+	 *      NOTE: no Page mode possible for EDO RAMs (?)
+	 */
+	ramSize = 16 * 1024 * 1024;
+	m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
+			  M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
+                          M360_MEMC_OR_32BIT    | M360_MEMC_OR_DRAM;
+	m360.memc[7].br = (unsigned long)&_RamBase | M360_MEMC_BR_V;
+
+	/*
+	 * FIXME: here we should wait for 8 refresh cycles...
+	 */
+	/*
+	 * Step 12a: test the ram, if wanted
+	 * FIXME: when do we call this?
+	 * -> only during firmware execution
+	 * -> perform intesive test only on request
+	 * -> ensure, that results are stored properly
+	 */
+#if 0 /* FIXME: activate RAM tests again */
+	{
+	  void *ram_base, *ram_end, *code_loc;
+	  extern char ramtest_start,ramtest_end;
+	  ram_base = &ramtest_start;
+	  ram_end  = &ramtest_end;
+	  code_loc = (void *)ramtest_exec;
+	  if ((ram_base < ram_end) &&
+	    !((ram_base <= code_loc) && (code_loc < ram_end))) {	    
+	    ramtest_exec(ram_base,ram_end);
+	  }
+	}
+#endif
+	/*
+	 * Step 13: Copy  the exception vector table to system RAM
+	 */
+	m68k_get_vbr (vbr);
+	for (i = 0; i < 256; ++i)
+		M68Kvec[i] = vbr[i];
+	m68k_set_vbr (M68Kvec);
+	
+	/*
+	 * Step 14: More system initialization
+	 * SDCR (Serial DMA configuration register)
+	 *	Disable SDMA during FREEZE
+	 *	Give SDMA priority over all interrupt handlers
+	 *	Set DMA arbiration level to 4
+	 * CICR (CPM interrupt configuration register):
+	 *	SCC1 requests at SCCa position
+	 *	SCC2 requests at SCCb position
+	 *	SCC3 requests at SCCc position
+	 *	SCC4 requests at SCCd position
+	 *	Interrupt request level 4
+	 *	Maintain original priority order
+	 *	Vector base 128
+	 *	SCCs priority grouped at top of table
+	 */
+	m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+	m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
+						(4 << 13) | (0x1F << 8) | (128);
+
+	/*
+	 * Step 15: Set module configuration register
+	 *	Disable timers during FREEZE
+	 *	Enable bus monitor during FREEZE
+	 *	BCLRO* arbitration level 3
+	 *	No show cycles
+	 *	User/supervisor access
+	 *	Bus clear interupt service level 7
+	 *	SIM60 interrupt sources higher priority than CPM
+	 */
+	m360.mcr = 0x4C7F;
+
 #elif (defined (GEN68360_WITH_SRAM))
    /*
     ***************************************************