Actually adding efi bsp's from John Gwynne after forgetting to

commit them.

5 files changed, 685 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/m68k/efi68k/include/16550.h b/c/src/lib/libbsp/m68k/efi68k/include/16550.h
new file mode 100644
index 0000000000..d13b5a1fc7
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/efi68k/include/16550.h
@@ -0,0 +1,120 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ *   16550 -- header file for National Semiconducor's 16550 UART
+ *
+ * This file has been created by John S. Gwynne for the efi68k
+ * project.
+ * 
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ *    the above authorship, this list of conditions and the
+ *    following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ *
+ *  $Id$
+ */
+
+#ifndef _16550_H_
+#define _16550_H_
+
+/* base address is the physical location of register 0 */
+#define UART_BASE_ADDRESS 0x0400001
+
+/* definitions of register addresses and associate bits */
+
+#define RBR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)	
+                                /* Receiver Buffer Register (w/DLAB=0)*/
+				/*    8-bit data */
+
+#define THR (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)	
+                                /* Transmitter Holding Register (w/DLAB=0) */
+				/*    8-bit data */
+
+#define DLL (volatile unsigned char * const)(0*2+UART_BASE_ADDRESS)
+                          	/* Divisor Latch (LS) (w/DLAB=1) */
+				/*    LSB of Divisor */
+
+#define DLM (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS)
+                                /* Divisor Latch (MS) (w/DLAB=1) */
+				/*    MSB of Divisor */
+
+#define IER (volatile unsigned char * const)(1*2+UART_BASE_ADDRESS)
+                              	/* Interrupt Enable Register (w/DLAB=0) */
+#define    ERBFI 0x01		/*    Enable Recv Data Available Interrupt */
+#define    ETBEI 0x02		/*    Enable Trans Holding Reg Empty Inter */
+#define    ELSI  0x04		/*    Enable Recv Line Status Interrupt */
+#define    EDSSI 0x08		/*    Enable Modem Status Interrupt */
+
+#define IIR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS)
+                              	/* Interrupt Ident Register (read only) */
+#define    NIP   0x01		/*    No Interrupt Pending */
+#define    IID_MASK 0x0e	/*    Interrupt ID mask */
+#define    FE_MASK 0xc0		/*    FIFO's Enabled */
+
+#define FCR (volatile unsigned char * const)(2*2+UART_BASE_ADDRESS)
+                             	/* FIFO Control Register (write only) */
+#define    FIFO_E 0x01		/*    FIFO Enable */
+#define    RFR   0x02		/*    RCVR FIFO Reset */
+#define    XFR   0x04		/*    XMIT FIFO Reset */
+#define    DMAMS 0x08		/*    DMA Mode Select */
+#define    RCVRTG_MASK 0xC0	/*    RCVR Triger MSBit/LSBit */
+
+#define LCR (volatile unsigned char * const)(3*2+UART_BASE_ADDRESS)
+                               	/* Line Control Register */
+#define    WLS_MASK 0x03	/*    Word Legth Select Mask */
+#define       WL_5 0x00		/*       5 bits */
+#define       WL_6 0x01		/*       6 bits */
+#define       WL_7 0x02		/*       7 bits */
+#define       WL_8 0x03		/*       8 bits */
+#define    NSB   0x04		/*    Number of Stop Bits (set is 2/1.5) */
+#define    PEN   0x08		/*    Parity Enable */
+#define    EPS   0x10		/*    Even Parity Select */
+#define    STP   0x20		/*    Stick Parity */
+#define    SETBK 0x40		/*    Set Break */
+#define    DLAB  0x80		/*    Divisor Latch Access Bit */
+
+#define MCR (volatile unsigned char * const)(4*2+UART_BASE_ADDRESS)
+                              	/* Modem Control Register */
+#define    DTR   0x01		/*    Data Terminal Ready */
+#define    RTS   0x02		/*    Request to Send */
+#define    OUT1  0x04		/*    Out 1 */
+#define    OUT2  0x08		/*    Out 2 */
+#define    LOOP  0x10		/*    Loop */
+
+#define LSR (volatile unsigned char * const)(5*2+UART_BASE_ADDRESS)
+                           	/* Line Status Register */
+#define    DR    0x01		/*    Data Ready */
+#define    OE    0x02		/*    Overrun error */
+#define    PE    0x04		/*    Parity error */
+#define    FE    0x08		/*    Framing error */
+#define    BI    0x10		/*    Break Interrupt */
+#define    THRE  0x20		/*    Transmitter Holding Register */
+#define    TEMT  0x40		/*    Transmitter Empty */
+#define    RCVFIE 0x80		/*    Recv FIFO Error */
+
+#define MDSR (volatile unsigned char * const)(6*2+UART_BASE_ADDRESS)
+                           	/* Modem Status Register */
+#define    DCTS  0x01		/*    Delta Clear to Send */
+#define    DDSR  0x02		/*    Delta Data Set Ready */
+#define    TERI  0x04		/*    Trailing Edge Ring Indicator */
+#define    DDCD  0x08		/*    Delta Data Carrier Detect */
+#define    CTS   0x10		/*    Clear to Send */
+#define    DSR   0x20		/*    Data Set Ready */
+#define    RI    0x40		/*    Ring Indicator */
+#define    DCD   0x80		/*    Data Carrier Detect */
+
+#define SCR (volatile unsigned char * const)(7*2+UART_BASE_ADDRESS)
+                              	/* Scratch Register */
+				/*    8-bit register */
+#endif
diff --git a/c/src/lib/libbsp/m68k/efi68k/include/DP8570A.h b/c/src/lib/libbsp/m68k/efi68k/include/DP8570A.h
new file mode 100644
index 0000000000..7409d489ce
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/efi68k/include/DP8570A.h
@@ -0,0 +1,285 @@
+/*
+ *-------------------------------------------------------------------
+ *
+ *   DP8570A -- header file for National Semiconducor's DP8570A TCP
+ *
+ * This file has been created by John S. Gwynne for the efi68k
+ * project.
+ * 
+ * Redistribution and use in source and binary forms are permitted
+ * provided that the following conditions are met:
+ * 1. Redistribution of source code and documentation must retain
+ *    the above authorship, this list of conditions and the
+ *    following disclaimer.
+ * 2. The name of the author may not be used to endorse or promote
+ *    products derived from this software without specific prior
+ *    written permission.
+ *
+ * This software is provided "AS IS" without warranty of any kind,
+ * either expressed or implied, including, but not limited to, the
+ * implied warranties of merchantability, title and fitness for a
+ * particular purpose.
+ *
+ *------------------------------------------------------------------
+ *
+ *  $Id$
+ */
+
+#ifndef _DP8570A_H_
+#define _DP8570A_H_
+
+/* base address is the physical location of register 0 */
+#define TCP_BASE_ADDRESS 0x0600001
+
+
+/* definitions of register addresses and associate bits */
+
+/* ********************************************************* */
+/* Control Registers */
+/* ********************************************************* */
+
+/* REMEMBER: if you are in an interrupt routine, you must
+   reset RS and PS of MSR to the value they had on entry
+   to the ISR before exiting */
+
+#define MSR (volatile unsigned char * const)(0x00*2+TCP_BASE_ADDRESS)
+				/* Main Status Register */
+#define    INT 0x01		/*    Interrupt Status */
+#define    PF  0x02		/*    Power Fail Interrupt */
+#define    PER 0x04		/*    Period Interrupt */
+#define    AL  0x08		/*    Alarm Interrupt */
+#define    T0  0x10		/*    Timer 0 Interrupt */
+#define    T1  0x20		/*    Timer 1 Interrupt */
+#define    RS  0x40		/*    Register Select Bit */
+#define    PS  0x80		/*    Page Select Bit */
+
+#define T0CR (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS)
+				/* Timer 0 Control Register */
+#define T1CR (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS)
+				/* Timer 1 Control Register */
+#define    TSS 0x01		/*    Timer Start/!Stop */
+#define    M0  0x02		/*    Mode Select */
+#define    M1  0x04		/*    Mode Select */
+#define    C0  0x08		/*    Input Clock Select */
+#define    C1  0x10		/*    Input Clock Select */
+#define    C2  0x20		/*    Input Clock Select */
+#define    RD  0x40		/*    Timer Read */
+#define    CHG 0x80		/*    Count Hold/Gate */
+
+#define PFR (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS)
+				/* Periodic Flag Register */
+#define    R_1MIN  0x01		/*    Minute Flage */
+#define    R_10S   0x02		/*    10 Second Flag */
+#define    R_1S    0x04		/*    Second Flag */
+#define    R_100MS 0x08		/*    100 Millisec Flag */
+#define    R_10MS  0x10		/*    10 Millisec Flag */
+#define    R_1MS   0x20		/*    1 Millisec Flag */
+#define    OSF     0x40		/*    Oscillator Failed/Single Supply */
+#define    TMODE   0x80		/*    Test Mode Enable */
+
+#define IRR (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS)
+				/* Interrupt Routing Register */
+#define    PF_R 0x01		/*    Power Fail Route */
+#define    PR_R 0x02		/*    Periodic Route */
+#define    AL_R 0x04		/*    Alarm Route */
+#define    T0_R 0x08		/*    Timer 0 Route */
+#define    T1_R 0x10		/*    Timer 1 Route */
+#define    PFD  0x20		/*    PF Delay Enable */
+#define    LBF  0x40		/*    Low Battery Flag */
+#define    TMSE 0x80		/*    Time Save Enable */
+
+#define RTMR (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS)
+				/* Real Time Mode Register */
+#define    LY0 0x01		/*    Leap Year LSB */
+#define    LY1 0x02		/*    Leap Year MSB */
+#define    H12 0x04		/*    12/!24 Hour Mode */
+#define    CSS 0x08		/*    Clock Start/!Stop */
+#define    IPF 0x10		/*    Interrupt PF Operation */
+#define    TPF 0x20		/*    Timer PF Operation */
+#define    XT0 0x40		/*    Crystal Frequency LSB */
+#define    XT1 0x80		/*    Crystal Frequency MSB */
+
+#define OMR (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS)
+				/* Output Mode Register */
+#define    TH  0x01		/*    T1 Active Hi/!Low */
+#define    TP  0x02		/*    T1 Push Pull/!Open Drain */
+#define    IH  0x04		/*    INTR Active Hi/!Low */
+#define    IP  0x08		/*    INTR Push Pull/!Open Drain */
+#define    MH  0x10		/*    MFO Active Hi/!Low */
+#define    MP  0x20		/*    MFO Push Pull/!Open Drain */
+#define    MT  0x40		/*    MFO Pin as Timer 0 */
+#define    MO  0x80		/*    MFO Pin as Oscillator */
+
+#define ICR0 (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS)
+				/* Interrupt control Register 0 */
+#define    ME  0x01		/*    Minutes Enable */
+#define    TSE 0x02		/*    10 Second Enable */
+#define    SE  0x04		/*    Seconds Enable */
+#define    HME 0x08		/*    100 Millisec Enable */
+#define    TME 0x10		/*    10 Millisec Enable */
+#define    OME 0x20		/*    Millisec Enable */
+#define    T0E 0x40		/*    Timer 0 Enable */
+#define    T1E 0x80		/*    Timer 1 Enable */
+
+#define ICR1 (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS)
+				/* Interrupt control Register 1 */
+#define    SCE  0x01		/*    Second Compare Enable */
+#define    MNE  0x02		/*    Minute Compare Enable */
+#define    HRE  0x04		/*    Hour Compare Enable */
+#define    DOME 0x08		/*    Day of Month Compare Enable */
+#define    MOE  0x10		/*    Month Compare Enable */
+#define    DOWE 0x20		/*    Day of Week Compare Enable */
+#define    ALE  0x40		/*    Alarm Interrupt Enable */
+#define    PFE  0x80		/*    Power Fail Interrupt Enable */
+
+
+
+/* ********************************************************* */
+/* Counters: Clock and Calendar (data is stored in BCD) */
+/* ********************************************************* */
+#define HOFS (volatile unsigned char * const)(0x05*2+TCP_BASE_ADDRESS)
+				/* Hundredth of Seconds */
+#define SEC (volatile unsigned char * const)(0x06*2+TCP_BASE_ADDRESS)
+				/* Seconds */
+#define MIN (volatile unsigned char * const)(0x07*2+TCP_BASE_ADDRESS)
+				/* Minutes */
+#define HRS (volatile unsigned char * const)(0x08*2+TCP_BASE_ADDRESS)
+				/* Hours */
+#define DOM (volatile unsigned char * const)(0x09*2+TCP_BASE_ADDRESS)
+				/* Day of Month */
+#define MON (volatile unsigned char * const)(0x0a*2+TCP_BASE_ADDRESS)
+				/* Month */
+#define YR (volatile unsigned char * const)(0x0b*2+TCP_BASE_ADDRESS)
+				/* Year */
+#define JD_LSB (volatile unsigned char * const)(0x0c*2+TCP_BASE_ADDRESS)
+				/* Julian Date (LSB) */
+#define JD_MSM (volatile unsigned char * const)(0x0d*2+TCP_BASE_ADDRESS)
+				/* Julian Date (MSB) */
+#define DOW (volatile unsigned char * const)(0x0e*2+TCP_BASE_ADDRESS)
+				/* Day of week */
+
+
+/* ********************************************************* */
+/* Timer Data Registers */
+/* ********************************************************* */
+#define T0_LSB (volatile unsigned char * const)(0x0f*2+TCP_BASE_ADDRESS)
+				/* Timer 0 LSB */
+#define T0_MSB (volatile unsigned char * const)(0x10*2+TCP_BASE_ADDRESS)
+				/* Timer 0 MSB */
+#define T1_LSB (volatile unsigned char * const)(0x11*2+TCP_BASE_ADDRESS)
+				/* Timer 1 LSB */
+#define T1_MSB (volatile unsigned char * const)(0x12*2+TCP_BASE_ADDRESS)
+				/* Timer 1 MSB */
+
+
+/* ********************************************************* */
+/* Timer Compare RAM */
+/* ********************************************************* */
+#define TC_SEC (volatile unsigned char * const)(0x13*2+TCP_BASE_ADDRESS)
+				/* Seconds Compare RAM */
+#define TC_MIN (volatile unsigned char * const)(0x14*2+TCP_BASE_ADDRESS)
+				/* Minutes Compare RAM */
+#define TC_HRS (volatile unsigned char * const)(0x15*2+TCP_BASE_ADDRESS)
+				/* Hours Compare RAM */
+#define TC_DOM (volatile unsigned char * const)(0x16*2+TCP_BASE_ADDRESS)
+				/* Day of Month Compare RAM */
+#define TC_MON (volatile unsigned char * const)(0x17*2+TCP_BASE_ADDRESS)
+				/* Month Compare RAM */
+#define TC_DOW (volatile unsigned char * const)(0x18*2+TCP_BASE_ADDRESS)
+				/* Day of Week Compare RAM */
+
+
+/* ********************************************************* */
+/* Time Save RAM */
+/* ********************************************************* */
+#define S_SEC (volatile unsigned char * const)(0x19*2+TCP_BASE_ADDRESS)
+				/* Seconds Save RAM */
+#define S_MIN (volatile unsigned char * const)(0x1a*2+TCP_BASE_ADDRESS)
+				/* Minutes Save RAM */
+#define S_HRS (volatile unsigned char * const)(0x1b*2+TCP_BASE_ADDRESS)
+				/* Hours Save RAM */
+#define S_DOM (volatile unsigned char * const)(0x1c*2+TCP_BASE_ADDRESS)
+				/* Day of Month Save RAM */
+#define S_MON (volatile unsigned char * const)(0x1d*2+TCP_BASE_ADDRESS)
+				/* Month Save RAM */
+
+
+/* ********************************************************* */
+/* Miscellaneous Registers */
+/* ********************************************************* */
+				/* rem: 0x1e is general purpose RAM */
+#define TMR (volatile unsigned char * const)(0x1F*2+TCP_BASE_ADDRESS)
+				/* RAM/Test Mode Register */
+
+
+
+/* ********************************************************* */
+/* RAM allocation */
+/* ********************************************************* */
+#define RAM_OSC_FAIL (volatile unsigned char * const)(0x01*2+TCP_BASE_ADDRESS)
+				/* 1: osc. failed time lost */
+#define RAM_POWERUP (volatile unsigned char * const)(0x02*2+TCP_BASE_ADDRESS)
+				/* 1: power was removed and the applied
+				      before last TCP init */
+#define RAM_LOWBAT (volatile unsigned char * const)(0x03*2+TCP_BASE_ADDRESS)
+				/* 1: battery voltage is low (2.2V) */
+				/* not valid in single supply mode */
+#define RAM_SINGLE_SUP (volatile unsigned char * const)(0x04*2+TCP_BASE_ADDRESS)
+                                /* 1: single supply mode */
+                                /* note: single supply mode will be
+				   selected when no backup battery is
+				   present and/or the first time the
+				   system is booted after the loss of
+				   backup battery voltage. */
+#define RAM_TCP_FAILURE (volatile unsigned char * const)(0x05*2+TCP_BASE_ADDRESS)
+				/* 1: TCP failed to start oscillating */
+
+
+/* ********************************************************* */
+/* TCP data structures */
+/* ********************************************************* */
+
+struct clock_counters {
+  unsigned char hofs;
+  unsigned char d0;		/* the dx's are place holders since */
+  unsigned char sec;		/* the TCP is addressable only on */
+  unsigned char d1;		/* odd addresses. */
+  unsigned char min;
+  unsigned char d2;
+  unsigned char hrs;
+  unsigned char d3;
+  unsigned char dom;
+  unsigned char d4;
+  unsigned char mon;
+  unsigned char d5;
+  unsigned char yr;
+  unsigned char d6;
+  unsigned char jd0;
+  unsigned char d7;
+  unsigned char jd1;
+  unsigned char d8;
+  unsigned char dow;
+};
+
+extern struct clock_ram * const tcp_power_up;
+
+struct clock_ram {
+  unsigned char sec;
+  unsigned char d0;		/* the dx's are place holders since */
+  unsigned char min;		/* the TCP is addressable only on */
+  unsigned char d1;		/* odd addresses. */
+  unsigned char hrs;
+  unsigned char d2;
+  unsigned char dom;
+  unsigned char d3;
+  unsigned char mon;
+};
+
+extern struct clock_ram * const tcp_power_up;
+extern struct clock_ram * const tcp_power_down;
+extern struct clock_counters * const tcp_clock;
+extern struct clock_ram * const tcp_save_ram;
+
+void tcp_init(void);
+
+#endif /* _DP8570A_H_ */
diff --git a/c/src/lib/libbsp/m68k/efi68k/include/bsp.h b/c/src/lib/libbsp/m68k/efi68k/include/bsp.h
new file mode 100644
index 0000000000..988383c0d1
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/efi68k/include/bsp.h
@@ -0,0 +1,153 @@
+/*  bsp.h
+ *
+ *  This include file contains all efi68k board IO definitions.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#ifndef __EFI68K_BSP_h
+#define __EFI68K_BSP_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems.h>
+#include <clockdrv.h>
+#include <console.h>
+#include <iosupp.h>
+#include <efi68k.h>
+#include <DP8570A.h>
+#include <16550.h>
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ */
+
+/* XXX - JRS - I want to compile the tmtests */
+
+#define MUST_WAIT_FOR_INTERRUPT 1 
+
+#define Install_tm27_vector( handler )
+
+#define Cause_tm27_intr()
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr() 
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+#define delay( microseconds ) \
+  { register rtems_unsigned32 _delay=(microseconds); \
+    register rtems_unsigned32 _tmp=123; \
+    asm volatile( "0: \
+                     nbcd      %0 ; \
+                     nbcd      %0 ; \
+                     dbf       %1,0b" \
+                  : "=d" (_tmp), "=d" (_delay) \
+                  : "0"  (_tmp), "1"  (_delay) ); \
+  }
+
+/* macros */
+
+#define RAM_START 0x200000
+#define RAM_END   0x240000
+
+#define RAW_PUTS(str) \
+  { register char *ptr = str; \
+    while (*ptr) outbyte(*ptr++); \
+  }
+
+#define RAW_PUTI(n) { \
+    register int i, j; \
+    \
+    RAW_PUTS("0x"); \
+    for (i=28;i>=0;i -= 4) { \
+      j = (n>>i) & 0xf; \
+      outbyte( (j>9 ? j-10+'a' : j+'0') ); \
+    } \
+  }
+
+/* miscellaneous stuff assumed to exist */
+
+extern rtems_configuration_table BSP_Configuration;
+
+extern m68k_isr_entry M68Kvec[];   /* vector table address */
+
+extern int stack_size;
+
+extern int stack_start;
+
+extern rtems_unsigned32 Timer_interrupts;
+
+/*
+ *  Device Driver Table Entries
+ */
+ 
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+ 
+/*
+ * How many libio files we want
+ */
+ 
+#define BSP_LIBIO_MAX_FDS       20
+ 
+/* functions */
+
+void bsp_cleanup( void );
+
+m68k_isr_entry set_vector(
+  rtems_isr_entry     handler,
+  rtems_vector_number vector,
+  int                 type
+);
+
+void console_init(void);
+
+void watch_dog_init(void);
+
+void tcp_init(void);
+
+void Spurious_Initialize(void);
+
+void _UART_flush(void);
+
+void Clock_exit(void);
+
+void outbyte(char);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/m68k/efi68k/include/coverhd.h b/c/src/lib/libbsp/m68k/efi68k/include/coverhd.h
new file mode 100644
index 0000000000..671f20d197
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/efi68k/include/coverhd.h
@@ -0,0 +1,106 @@
+/*  coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C.  These are used in the
+ *  Timing Test Suite to ignore the overhead required to pass arguments 
+ *  to directives.  On some CPUs and/or target boards, this overhead 
+ *  is significant and makes it difficult to distinguish internal 
+ *  RTEMS execution time from that used to call the directive.
+ *  This file should be updated after running the C overhead timing
+ *  test.  Once this update has been performed, the RTEMS Time Test
+ *  Suite should be rebuilt to account for these overhead times in the
+ *  timing results.
+ *
+ *  NOTE:  If these are all zero, then the times reported include all
+ *         all calling overhead including passing of arguments.
+ *
+ *  COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
+ *  On-Line Applications Research Corporation (OAR).
+ *  All rights assigned to U.S. Government, 1994.
+ *
+ *  This material may be reproduced by or for the U.S. Government pursuant
+ *  to the copyright license under the clause at DFARS 252.227-7013.  This
+ *  notice must appear in all copies of this file and its derivatives.
+ *
+ *  $Id$
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      0
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        0
+#define CALLING_OVERHEAD_TASK_CREATE               0
+#define CALLING_OVERHEAD_TASK_IDENT                0
+#define CALLING_OVERHEAD_TASK_START                0
+#define CALLING_OVERHEAD_TASK_RESTART              0
+#define CALLING_OVERHEAD_TASK_DELETE               0
+#define CALLING_OVERHEAD_TASK_SUSPEND              0
+#define CALLING_OVERHEAD_TASK_RESUME               0
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         0
+#define CALLING_OVERHEAD_TASK_MODE                 0
+#define CALLING_OVERHEAD_TASK_GET_NOTE             0
+#define CALLING_OVERHEAD_TASK_SET_NOTE             0
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            0
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           0
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           0
+#define CALLING_OVERHEAD_CLOCK_GET                 0
+#define CALLING_OVERHEAD_CLOCK_SET                 0
+#define CALLING_OVERHEAD_CLOCK_TICK                0
+
+#define CALLING_OVERHEAD_TIMER_CREATE              0
+#define CALLING_OVERHEAD_TIMER_IDENT               0
+#define CALLING_OVERHEAD_TIMER_DELETE              0
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          0
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           0
+#define CALLING_OVERHEAD_TIMER_RESET               0
+#define CALLING_OVERHEAD_TIMER_CANCEL              0
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          0
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           0
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          0
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          0
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     0
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       0
+
+#define CALLING_OVERHEAD_EVENT_SEND                0
+#define CALLING_OVERHEAD_EVENT_RECEIVE             0
+#define CALLING_OVERHEAD_SIGNAL_CATCH              0
+#define CALLING_OVERHEAD_SIGNAL_SEND               0
+#define CALLING_OVERHEAD_PARTITION_CREATE          0
+#define CALLING_OVERHEAD_PARTITION_IDENT           0
+#define CALLING_OVERHEAD_PARTITION_DELETE          0
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      0
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   0
+#define CALLING_OVERHEAD_REGION_CREATE             0
+#define CALLING_OVERHEAD_REGION_IDENT              0
+#define CALLING_OVERHEAD_REGION_DELETE             0
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        0
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     0
+#define CALLING_OVERHEAD_PORT_CREATE               0
+#define CALLING_OVERHEAD_PORT_IDENT                0
+#define CALLING_OVERHEAD_PORT_DELETE               0
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 0
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 0
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             0
+#define CALLING_OVERHEAD_IO_OPEN                   0
+#define CALLING_OVERHEAD_IO_CLOSE                  0
+#define CALLING_OVERHEAD_IO_READ                   0
+#define CALLING_OVERHEAD_IO_WRITE                  0
+#define CALLING_OVERHEAD_IO_CONTROL                0
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     0
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     0
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  0
+
+#endif
diff --git a/c/src/lib/libbsp/m68k/efi68k/include/efi68k.h b/c/src/lib/libbsp/m68k/efi68k/include/efi68k.h
new file mode 100644
index 0000000000..398dbf2fb4
--- /dev/null
+++ b/c/src/lib/libbsp/m68k/efi68k/include/efi68k.h
@@ -0,0 +1,21 @@
+/*  efi68k.h
+ *
+ *  $Id$
+ */
+
+#ifndef _EFI68k_H_
+#define _EFI68k_H_
+
+
+/* interrupt levels */
+#define WD_ISR_LEVEL 1
+#define TCP_ISR_LEVEL 4
+#define UART_ISR_LEVEL 6
+#define INTR7 7
+
+
+/* macro/function definitions */
+static void reboot(void) __attribute__ ((noreturn));
+__inline__ static void reboot(void) {asm("trap #15");}
+     
+#endif /* _EFI68k_H_ */