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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-07-11 19:31:04 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-07-11 19:31:04 +0000 |
| commit | bc85fd5a6df8753543ba55c98a588e255471752b (patch) | |
| tree | b51e3eb5c77cca042081bb7ba88e5515560451d2 /c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c | |
| parent | Patch rtems-rc-20000711-2-cvs.diff from Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
| download | rtems-bc85fd5a6df8753543ba55c98a588e255471752b.tar.bz2 | |
Reworked score/cpu/i960 so it can be safely compiled multilib. All
routines and structures that require CPU model specific information
are now in libcpu. This required significant rework of the
score/cpu header files and the creation of multiple header files
and subdirectories in libcpu/i960.
Diffstat (limited to 'c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c')
| -rw-r--r-- | c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c index 6f3d97d6b0..fcaf48e06f 100644 --- a/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c +++ b/c/src/lib/libbsp/i960/rxgen960/startup/rom_cntrltbl.c @@ -6,7 +6,7 @@ * $Id$ */ -#include <i960RP.h> +#include <bsp.h> #include "cntrltbl.h" /*-------------------------------------*/ /* Control Table. |