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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 15:29:18 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 15:29:18 +0000 |
commit | 702c5f5b42e975c35a94f1ae3d39a77815f36f70 (patch) | |
tree | 46a9caa5230280f7c51530aeeff50355f893083c /c/src/lib/libbsp/i960/rxgen960/startup/prcb.h | |
parent | First attempt at icluding Eric Valette and Emmanuel Raguet. (diff) | |
download | rtems-702c5f5b42e975c35a94f1ae3d39a77815f36f70.tar.bz2 |
The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@ramix.com> of RAMIX.
Diffstat (limited to 'c/src/lib/libbsp/i960/rxgen960/startup/prcb.h')
-rw-r--r-- | c/src/lib/libbsp/i960/rxgen960/startup/prcb.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h new file mode 100644 index 0000000000..9b9f4c59bc --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/prcb.h @@ -0,0 +1,57 @@ +/*-------------------------------------*/ +/* prcb.h */ +/* Last change : 11. 1.95 */ +/*-------------------------------------*/ +#ifndef _PRCB_H_ +#define _PRCB_H_ + +#include "flttbl.h" +#include "cntrltbl.h" +#include "intrtbl.h" +#include "systbl.h" + + /* PRocess Control Block + */ +struct PRCB { + FaultTblEntry * faultTbl; /* Fault Table Base */ + ControlTblEntry * controlTbl; /* Control Table Base */ + unsigned int arithConfig; /* Arithmetic Control Register Image */ + unsigned int faultConfig; /* Fault Configuration Word Image */ + InterruptTbl * interruptTbl; /* Interrupt Table Base */ + SystemTbl * systemTbl; /* System Procedure Table Base */ + unsigned int reserved; /* Reserved */ + unsigned int * intStackPtr; /* Interrupt Stack Pointer */ + unsigned int instCacheConfig; /* Instruction Cache Config */ + unsigned int regCacheConfig; /* Register Cache Config */ +}; + /* Constants for Arithmetic Control Register. + */ +#define INT_OVFL_ENABLE 0 +#define INT_OVFL_DISABLE 0x1000 + +#define PRECISE_FLTS 0x8000 +#define IMPRECISE_FLTS 0 + /* Constants for Fault Configuration Word. + */ +#define UNLGND_FAULT_ENABLE 0 +#define UNLGND_FAULT_DISABLE 0x40000000 + /* Constants for Instruction Cache Configuration Word. + */ +#define INST_CACHE_ENABLE 0 +#define INST_CACHE_DISABLE 0x10000 + /* RAM-based Process Control Block. + */ +extern struct PRCB ram_prcb; +extern struct PRCB rom_prcb; + /* Supervisor Stack. Is defined directly in rom.ld. + */ +extern unsigned int svrStackPtr[]; + /* Interrupt Stack. Is defined directly in rom.ld. + */ +extern unsigned int intStackPtr[]; + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + |