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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 15:29:18 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-10-27 15:29:18 +0000 |
| commit | 702c5f5b42e975c35a94f1ae3d39a77815f36f70 (patch) | |
| tree | 46a9caa5230280f7c51530aeeff50355f893083c /c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h | |
| parent | First attempt at icluding Eric Valette and Emmanuel Raguet. (diff) | |
| download | rtems-702c5f5b42e975c35a94f1ae3d39a77815f36f70.tar.bz2 | |
The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson
<mark@ramix.com> of RAMIX.
Diffstat (limited to 'c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h')
| -rw-r--r-- | c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h new file mode 100644 index 0000000000..aafca23b03 --- /dev/null +++ b/c/src/lib/libbsp/i960/rxgen960/startup/cntrltbl.h @@ -0,0 +1,48 @@ +/*-------------------------------------*/ +/* cntrltbl.h */ +/* Last change : 11. 1.95 */ +/*-------------------------------------*/ +#ifndef _CNTRLTBL_H_ +#define _CNTRLTBL_H_ + + /* Control Table Entry. + */ +typedef unsigned int ControlTblEntry; + /* Control Table itself. + */ +extern ControlTblEntry controlTbl[]; +extern ControlTblEntry rom_controlTbl[]; + + /* Interrupt Registers Initial. + */ +#define IPB0 0 +#define IPB1 0 +#define DAB0 0 +#define DAB1 0 + +#define I_DISABLE (0x1<<10) +#define I_ENABLE 0 + +#define MSK_UNCHNG 0 +#define MSK_CLEAR (0x1<<11) + +#define VECTOR_CACHE (0x1<<13) + + + + /* BreakPoint Control Register Initial. + */ +#define BPCON 0 + /* Bus Controller Mode Comstants. + */ +#define CONF_TBL_VALID 0x1 +#define PROTECT_RAM 0x2 +#define PROTECT_RAM_SUP 0x4 + + + +#endif +/*-------------*/ +/* End of file */ +/*-------------*/ + |