2004-09-29 Joel Sherrill <joel@OARcorp.com>

	* .cvsignore, ChangeLog, Makefile.am, acinclude.m4, configure.ac,
	cvme961/.cvsignore, cvme961/ChangeLog, cvme961/Makefile.am,
	cvme961/bsp_specs, cvme961/configure.ac, cvme961/times,
	cvme961/clock/ckinit.c, cvme961/console/console.c,
	cvme961/include/.cvsignore, cvme961/include/bsp.h,
	cvme961/include/tm27.h, cvme961/shmsupp/addrconv.c,
	cvme961/shmsupp/getcfg.c, cvme961/shmsupp/lock.c,
	cvme961/shmsupp/mpisr.c, cvme961/start/start.S,
	cvme961/startup/bspclean.c, cvme961/startup/bspstart.c,
	cvme961/startup/exit.c, cvme961/startup/linkcmds,
	cvme961/startup/setvec.c, cvme961/timer/timer.c,
	cvme961/timer/timerisr.S, i960sim/.cvsignore, i960sim/ChangeLog,
	i960sim/Makefile.am, i960sim/bsp_specs, i960sim/configure.ac,
	i960sim/clock/clockdrv.c, i960sim/console/console-io.c,
	i960sim/console/mon-syscalls.S, i960sim/include/.cvsignore,
	i960sim/include/bsp.h, i960sim/include/tm27.h, i960sim/start/start.c,
	i960sim/startup/bspstart.c, i960sim/startup/linkcmds,
	rxgen960/.cvsignore, rxgen960/ChangeLog, rxgen960/Makefile.am,
	rxgen960/README, rxgen960/bsp_specs, rxgen960/configure.ac,
	rxgen960/clock/ckinit.c, rxgen960/console/concntl.h,
	rxgen960/console/console.c, rxgen960/console/serial.c,
	rxgen960/console/serial.h, rxgen960/include/.cvsignore,
	rxgen960/include/bsp.h, rxgen960/include/rxgen960_config.h,
	rxgen960/include/tm27.h, rxgen960/start/rxgen_romld.S,
	rxgen960/startup/asmfault.S, rxgen960/startup/asmfault.h,
	rxgen960/startup/asmstub.S, rxgen960/startup/asmstub.h,
	rxgen960/startup/bspstart.c, rxgen960/startup/cntrltbl.c,
	rxgen960/startup/cntrltbl.h, rxgen960/startup/dram.ld,
	rxgen960/startup/exit.c, rxgen960/startup/fault.c,
	rxgen960/startup/fault.h, rxgen960/startup/faultret.h,
	rxgen960/startup/flttbl.c, rxgen960/startup/flttbl.h,
	rxgen960/startup/frmstr.c, rxgen960/startup/frmstr.h,
	rxgen960/startup/i960.h, rxgen960/startup/ihandler.S,
	rxgen960/startup/ihandler.h, rxgen960/startup/intrtbl.c,
	rxgen960/startup/intrtbl.h, rxgen960/startup/kkprintf.c,
	rxgen960/startup/linkcmds, rxgen960/startup/linkcmds.real,
	rxgen960/startup/main.h, rxgen960/startup/memchnl.h,
	rxgen960/startup/nmi.c, rxgen960/startup/nulsystbl.c,
	rxgen960/startup/pmc901_memmap.h, rxgen960/startup/prcb.c,
	rxgen960/startup/prcb.h, rxgen960/startup/rom.ld,
	rxgen960/startup/rom_cntrltbl.c, rxgen960/startup/rom_ibr.c,
	rxgen960/startup/rom_ibr.h, rxgen960/startup/rom_prcb.c,
	rxgen960/startup/rommon.h, rxgen960/startup/sctns.c,
	rxgen960/startup/sctns.h, rxgen960/startup/setvec.c,
	rxgen960/startup/systbl.c, rxgen960/startup/systbl.h,
	rxgen960/startup/time.h, rxgen960/timer/timer.c,
	rxgen960/timer/timerisr.S: Removed.

2 files changed, 0 insertions, 169 deletions

diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timer.c b/c/src/lib/libbsp/i960/cvme961/timer/timer.c
deleted file mode 100644
index a3da5e810f..0000000000
--- a/c/src/lib/libbsp/i960/cvme961/timer/timer.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*  Timer_init()
- *
- *  This routine initializes the Z8536 timer on the SQSIO4 SQUALL
- *  board for the CVME961 board.  The timer is setup to provide a
- *  tick every 1 millisecond.
- *
- *  Input parameters:  NONE
- *
- *  Output parameters:  NONE
- *
- *  NOTE: This routine will not work if the optimizer is enabled
- *        for most compilers.  The multiple writes to the Z8536
- *        will be optimized away.
- *
- *        It is important that the timer start/stop overhead be
- *        determined when porting or modifying this code.
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-#include <rtems.h>
-#include <bsp.h>
-#include <rtems/zilog/z8536.h>
-
-#define TIMER       0xc00000a0
-
-int Ttimer_val;
-rtems_boolean Timer_driver_Find_average_overhead;
-
-void flush_reg();
-rtems_isr timerisr();
-
-void Timer_initialize()
-{
-  set_vector( timerisr, 4, 0 );               /* install ISR */
-
-  i960_mask_intr( 5 );                        /* disable VIC068 tick */
-  flush_reg();                                /* timed code starts clean */
-  Ttimer_val = 0;                             /* clear timer ISR count */
-  Z8x36_WRITE( TIMER, MASTER_INTR,    0x01 ); /* reset              */
-  Z8x36_WRITE( TIMER, MASTER_INTR,    0x00 ); /* clear reset        */
-  Z8x36_WRITE( TIMER, MASTER_CFG,     0x00 ); /* disable everything */
-  Z8x36_WRITE( TIMER, CNT_TMR_VECTOR, 0x72 ); /* clear intr vector  */
-  Z8x36_WRITE( TIMER, MASTER_CFG,     0x20 ); /* clear intr info    */
-  Z8x36_WRITE( TIMER, MASTER_CFG,     0xe0 ); /* disable interrupts */
-  Z8x36_WRITE( TIMER, MASTER_CFG,     0x20 ); /* clear intr info    */
-  Z8x36_WRITE( TIMER, MASTER_CFG,     0xe0 ); /* disable interrupts */
-  Z8x36_WRITE( TIMER, MASTER_INTR,    0xe2 ); /* disable lower chain,   */
-                                              /*   no vector, set right */
-                                              /*   justified addr and   */
-                                              /*   master int enable    */
-  Z8x36_WRITE( TIMER, CT1_MODE_SPEC,      0x80 ); /* T1 continuous, and   */
-                                                  /*   cycle/pulse output */
-  Z8x36_WRITE( TIMER, CT1_TIME_CONST_MSB, 0x00 );
-  Z8x36_WRITE( TIMER, CT1_TIME_CONST_LSB, 0x00 );
-  Z8x36_WRITE( TIMER, CT1_CMD_STATUS,     0xc0 ); /* set INTR enable (IE) */
-  Z8x36_WRITE( TIMER, MASTER_CFG,         0x40 ); /* enable timer1        */
-  Z8x36_WRITE( TIMER, CT1_CMD_STATUS,     0x06 ); /* set trigger command  */
-                                                  /*   (TCB) and gate     */
-                                                  /* command (GCB) bits   */
-}
-
-#define AVG_OVERHEAD      11 /* It typically takes 5.5 microseconds */
-                             /* (11 countdowns) to start/stop the timer. */
-#define LEAST_VALID       15 /* Don't trust a value lower than this */
-
-int Read_timer()
-{
-  uint8_t          msb, lsb;
-  uint32_t         remaining, total;
-
-  Z8x36_WRITE( TIMER, CT1_CMD_STATUS,  0xce );  /* read the counter value */
-  Z8x36_READ(  TIMER, CT1_CUR_CNT_MSB, msb );
-  Z8x36_READ(  TIMER, CT1_CUR_CNT_LSB, lsb );
-
-  remaining = 0xffff - ((msb << 8) + lsb);
-  total = (Ttimer_val * 0x10000) + remaining;
-
-  if ( Timer_driver_Find_average_overhead == 1 )
-    return total;          /* in one-half microsecond units */
-  else {
-    if ( total < LEAST_VALID )
-      return 0;            /* below timer resolution */
-    return (total-AVG_OVERHEAD) >> 1;
-  }
-}
-
-rtems_status_code Empty_function( void )
-{
-  return RTEMS_SUCCESSFUL;
-}
-
-void Set_find_average_overhead(
-  rtems_boolean find_flag
-)
-{
-  Timer_driver_Find_average_overhead = find_flag;
-}
diff --git a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S b/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S
deleted file mode 100644
index d1e5982c0a..0000000000
--- a/c/src/lib/libbsp/i960/cvme961/timer/timerisr.S
+++ /dev/null
@@ -1,64 +0,0 @@
-/*  timer_isr()
- *
- *  This routine initializes the Z8536 timer on the SQSIO4 SQUALL
- *  board for the CVME961 board.  The timer is setup to provide a
- *  tick every 0x10000 / 2 milliseconds.  This is used to time
- *  executing code.
- *
- *  Input parameters:  NONE
- *
- *  Output parameters:  NONE
- *
- *  COPYRIGHT (c) 1989-1999.
- *  On-Line Applications Research Corporation (OAR).
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-#include <rtems/asm.h>
-
-.set PORT_A,     0xc00000a8                 # port A
-.set PORT_B,     0xc00000a4                 # port B
-.set PORT_C,     0xc00000a0                 # port C
-.set CTL_PORT,   0xc00000ac                 # control port
-
-.set T1CSR,      0x0a                       # T1 command/status reg
-.set RELOAD,     0x24                       # clr IP & IUS,allow countdown
-
-/*
- * Duplicating this symbol is stupid but eliminates
- * toolset variation problems.
- */
-        PUBLIC(timerisr)
-        PUBLIC(_timerisr)
-SYM (timerisr):
-SYM (_timerisr):
-        #ldconst   1,r4
-        #modpc     0,r4,r4               # enable tracing
-
-        ld      _Ttimer_val,r6           # r6 = test timer
-
-        ldconst T1CSR,r4                 # r4 = T1 control status reg
-        stob    r4,CTL_PORT              # select T1CSR
-        ldconst RELOAD,r5                # r5 = reset value
-        stob    r5,CTL_PORT              # reset countdown
-        addo    1,r6,r6
-        st      r6,_Ttimer_val           # increment test timer
-loop_til_cleared:
-        clrbit 4,sf0,sf0
-        bbs    4,sf0,loop_til_cleared
-leaf:   ret
-
-        .leafproc _flush_reg, flush_reg.lf
-        .globl    _flush_reg, flush_reg.lf
-_flush_reg:
-        lda     leaf,g14                 # g14 = exit address
-flush_reg.lf:
-        flushreg
-        mov     g14,g0                   # g0 = exit address
-        ldconst 0,g14                    # set g14 for non-leaf
-        bx      (g0)