New BSP from Tony R. Ambardar <tonya@ece.ubc.ca> from the

University of British Columbia.  The BSP is for:

    Yes, this is the "entry model" of a series of boards from Technologic
    Systems. Costs <$200 I believe. They have a WWW page at www.t-systems.com.
    I am letting them know about the availability of this BSP too.

4 files changed, 463 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/i386/ts_386ex/include/Makefile.in b/c/src/lib/libbsp/i386/ts_386ex/include/Makefile.in
new file mode 100644
index 0000000000..49be342e7a
--- /dev/null
+++ b/c/src/lib/libbsp/i386/ts_386ex/include/Makefile.in
@@ -0,0 +1,50 @@
+#
+#  $Id$
+#
+
+@SET_MAKE@
+srcdir = @srcdir@
+top_srcdir = @top_srcdir@
+top_builddir = ../../../../../../..
+subdir = c/src/lib/libbsp/i386/ts_386ex/include
+
+INSTALL = @INSTALL@
+
+RTEMS_ROOT = $(top_srcdir)/@RTEMS_TOPdir@
+PROJECT_ROOT = @PROJECT_ROOT@
+
+VPATH = @srcdir@
+
+# We only install wd80x3.h if HAS_NETWORKING was defined
+NE2000_yes_V = $(srcdir)/wd80x3.h
+NE2000 = $(NE2000_$(HAS_NETWORKING)_V)
+
+H_FILES = $(srcdir)/bsp.h $(srcdir)/coverhd.h $(NE2000)
+
+#
+#  Equate files are for including from assembly preprocessed by
+#  gm4 or gasp.  No examples are provided except for those for
+#  other CPUs.  The best way to generate them would be to
+#  provide a program which generates the constants used based
+#  on the C equivalents.
+#
+
+EQ_FILES =
+
+SRCS=$(H_FILES) $(EQ_FILES)
+
+include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg
+include $(RTEMS_ROOT)/make/leaf.cfg
+
+CLEAN_ADDITIONS +=
+CLOBBER_ADDITIONS +=
+
+all:	$(SRCS)
+	$(INSTALL_CHANGE) -m 444 $(H_FILES) $(PROJECT_INCLUDE)
+	$(INSTALL_CHANGE) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE)
+
+install:  all
+
+Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status
+	cd $(top_builddir) \
+	&& CONFIG_FILES=$(subdir)/$@ CONFIG_HEADERS= $(SHELL) ./config.status
diff --git a/c/src/lib/libbsp/i386/ts_386ex/include/bsp.h b/c/src/lib/libbsp/i386/ts_386ex/include/bsp.h
new file mode 100644
index 0000000000..f19341c853
--- /dev/null
+++ b/c/src/lib/libbsp/i386/ts_386ex/include/bsp.h
@@ -0,0 +1,186 @@
+/*
+ *  This include file definitions related to an Intel i386ex board.
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+
+#ifndef __TS386_h
+#define __TS386_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems.h>
+#include <iosupp.h>
+#include <console.h>
+#include <clockdrv.h>
+#include <bspIo.h>
+#include <irq.h>
+  
+/*
+ * Network driver configuration
+ */
+
+struct rtems_bsdnet_ifconfig;
+extern int rtems_ne_driver_attach (struct rtems_bsdnet_ifconfig *config);
+
+extern void Wait_X_ms (unsigned);
+
+#define RTEMS_BSP_NETWORK_DRIVER_NAME         "ne1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH       rtems_ne_driver_attach
+
+#define NE2000_BYTE_TRANSFERS
+
+/*
+ * Constants relating to the 8254 (or 8253) programmable interval timers.
+ */
+
+#define TIMER_CONFIG   0xF834
+#define IO_TIMER1      0xF040
+
+  /* Port address of the control port and timer channels */
+
+#define TIMER_CNTR0    (IO_TIMER1 + 0) /* timer 0 counter port           */
+#define TIMER_CNTR1    (IO_TIMER1 + 1) /* timer 1 counter port           */
+#define TIMER_CNTR2    (IO_TIMER1 + 2) /* timer 2 counter port           */
+#define TIMER_MODE     (IO_TIMER1 + 3) /* timer mode port                */
+#define TIMER_SEL0     0x00            /* select counter 0               */
+#define TIMER_SEL1     0x40            /* select counter 1               */
+#define TIMER_SEL2     0x80            /* select counter 2               */
+#define TIMER_INTTC    0x00            /* mode 0, intr on terminal cnt   */
+#define TIMER_ONESHOT  0x02            /* mode 1, one shot               */
+#define TIMER_RATEGEN  0x04            /* mode 2, rate generator         */
+#define TIMER_SQWAVE   0x06            /* mode 3, square wave            */
+#define TIMER_SWSTROBE 0x08            /* mode 4, s/w triggered strobe   */
+#define TIMER_HWSTROBE 0x0a            /* mode 5, h/w triggered strobe   */
+#define TIMER_LATCH    0x00            /* latch counter for reading      */
+#define TIMER_LSB      0x10            /* r/w counter LSB                */
+#define TIMER_MSB      0x20            /* r/w counter MSB                */
+#define TIMER_16BIT    0x30            /* r/w counter 16 bits, LSB first */
+#define TIMER_BCD      0x01            /* count in BCD                   */
+
+/*
+ *  Define the time limits for RTEMS Test Suite test durations.
+ *  Long test and short test duration limits are provided.  These
+ *  values are in seconds and need to be converted to ticks for the
+ *  application.
+ *
+ */
+
+#define MAX_LONG_TEST_DURATION       300 /* 5 minutes = 300 seconds */
+#define MAX_SHORT_TEST_DURATION      3   /* 3 seconds */
+
+/*
+ *  Define the interrupt mechanism for Time Test 27
+ *
+ *  NOTE: Use a software interrupt for the i386.
+ */
+
+#define MUST_WAIT_FOR_INTERRUTPT 0
+
+
+#define Install_tm27_vector(handler) \
+{ \
+  rtems_isr_entry dummy; \
+  rtems_interrupt_catch(handler, 0x90, &dummy); \
+}
+#define Cause_tm27_intr()              asm volatile( "int $0x90" : : );
+
+#define Clear_tm27_intr()
+
+#define Lower_tm27_intr()
+
+/*
+ *  Simple spin delay in microsecond units for device drivers.
+ *  This is very dependent on the clock speed of the target.
+ */
+
+#define delay( _microseconds ) \
+  { \
+    rtems_unsigned32 _counter; \
+    \
+    _counter = (_microseconds); \
+    \
+    asm volatile ( "0: nop;" \
+                   " mov %0,%0 ;" \
+                   " loop 0b" : "=c" (_counter) \
+                              : "0"  (_counter) \
+                 ); \
+    \
+  }
+
+/* Constants */
+
+#define RAM_START 0
+
+/* replaced the earlier EI kludge of 0xfffff */
+
+#define RAM_END   0x200000
+
+/* I/O addressing */
+
+/*
+ *#define Is_tx_ready( _status ) ( (_status) & 0x20 )
+ */
+/* dec 20. try the TE instead of TBE as the check */
+
+#define Is_tx_ready( _status ) ( (_status) & 0x40 )
+
+
+#define Is_rx_ready( _status ) ( (_status) & 0x01 )
+
+/* Structures */
+
+#ifdef F386_INIT
+#undef BSP_EXTERN
+#define BSP_EXTERN
+#else
+#undef BSP_EXTERN
+#define BSP_EXTERN extern
+#endif
+
+/*
+ *  Device Driver Table Entries
+ */
+ 
+/*
+ * NOTE: Use the standard Console driver entry
+ */
+ 
+/*
+ * NOTE: Use the standard Clock driver entry
+ */
+ 
+/* miscellaneous stuff assumed to exist */
+
+extern rtems_configuration_table BSP_Configuration;
+
+#define IDT_SIZE 256
+#define GDT_SIZE 3
+
+extern interrupt_gate_descriptor Interrupt_descriptor_table[IDT_SIZE];
+extern segment_descriptors Global_descriptor_table   [GDT_SIZE];
+
+BSP_EXTERN unsigned short Idt[3];  /* Interrupt Descriptor Table Address */
+BSP_EXTERN unsigned short Gdt[3];  /* Global Descriptor Table Address */
+BSP_EXTERN unsigned int   Idt_base;
+BSP_EXTERN unsigned int   Gdt_base;
+
+/* routines */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/i386/ts_386ex/include/coverhd.h b/c/src/lib/libbsp/i386/ts_386ex/include/coverhd.h
new file mode 100644
index 0000000000..de5e7aa742
--- /dev/null
+++ b/c/src/lib/libbsp/i386/ts_386ex/include/coverhd.h
@@ -0,0 +1,104 @@
+/* coverhd.h
+ *
+ *  This include file has defines to represent the overhead associated
+ *  with calling a particular directive from C on this target.
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#ifndef __COVERHD_h
+#define __COVERHD_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE      3
+#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE        3
+#define CALLING_OVERHEAD_TASK_CREATE               4
+#define CALLING_OVERHEAD_TASK_IDENT                4
+#define CALLING_OVERHEAD_TASK_START                4
+#define CALLING_OVERHEAD_TASK_RESTART              3
+#define CALLING_OVERHEAD_TASK_DELETE               3
+#define CALLING_OVERHEAD_TASK_SUSPEND              3
+#define CALLING_OVERHEAD_TASK_RESUME               3
+#define CALLING_OVERHEAD_TASK_SET_PRIORITY         4
+#define CALLING_OVERHEAD_TASK_MODE                 4
+#define CALLING_OVERHEAD_TASK_GET_NOTE             4
+#define CALLING_OVERHEAD_TASK_SET_NOTE             4
+#define CALLING_OVERHEAD_TASK_WAKE_WHEN            7
+#define CALLING_OVERHEAD_TASK_WAKE_AFTER           3
+#define CALLING_OVERHEAD_INTERRUPT_CATCH           4
+#define CALLING_OVERHEAD_CLOCK_GET                 7
+#define CALLING_OVERHEAD_CLOCK_SET                 7
+#define CALLING_OVERHEAD_CLOCK_TICK                2
+
+#define CALLING_OVERHEAD_TIMER_CREATE              3
+#define CALLING_OVERHEAD_TIMER_IDENT               3
+#define CALLING_OVERHEAD_TIMER_DELETE              3
+#define CALLING_OVERHEAD_TIMER_FIRE_AFTER          4
+#define CALLING_OVERHEAD_TIMER_FIRE_WHEN           8
+#define CALLING_OVERHEAD_TIMER_RESET               3
+#define CALLING_OVERHEAD_TIMER_CANCEL              3
+#define CALLING_OVERHEAD_SEMAPHORE_CREATE          4
+#define CALLING_OVERHEAD_SEMAPHORE_DELETE          3
+#define CALLING_OVERHEAD_SEMAPHORE_IDENT           4
+#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN          4
+#define CALLING_OVERHEAD_SEMAPHORE_RELEASE         3
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE      4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT       4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE      3
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND        3
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT      3
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST   4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE     4
+#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH       3
+
+#define CALLING_OVERHEAD_EVENT_SEND                4
+#define CALLING_OVERHEAD_EVENT_RECEIVE             4
+#define CALLING_OVERHEAD_SIGNAL_CATCH              3
+#define CALLING_OVERHEAD_SIGNAL_SEND               3
+#define CALLING_OVERHEAD_PARTITION_CREATE          4
+#define CALLING_OVERHEAD_PARTITION_IDENT           4
+#define CALLING_OVERHEAD_PARTITION_DELETE          3
+#define CALLING_OVERHEAD_PARTITION_GET_BUFFER      4
+#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER   4
+#define CALLING_OVERHEAD_REGION_CREATE             4
+#define CALLING_OVERHEAD_REGION_IDENT              3
+#define CALLING_OVERHEAD_REGION_DELETE             3
+#define CALLING_OVERHEAD_REGION_GET_SEGMENT        4
+#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT     4
+#define CALLING_OVERHEAD_PORT_CREATE               4
+#define CALLING_OVERHEAD_PORT_IDENT                3
+#define CALLING_OVERHEAD_PORT_DELETE               3
+#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4
+#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4
+
+#define CALLING_OVERHEAD_IO_INITIALIZE             4
+#define CALLING_OVERHEAD_IO_OPEN                   4
+#define CALLING_OVERHEAD_IO_CLOSE                  4
+#define CALLING_OVERHEAD_IO_READ                   4
+#define CALLING_OVERHEAD_IO_WRITE                  4
+#define CALLING_OVERHEAD_IO_CONTROL                4
+#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED      3
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE     3
+#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT      3
+#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE     3
+#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL     3
+#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD     3
+#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE  2
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
diff --git a/c/src/lib/libbsp/i386/ts_386ex/include/wd80x3.h b/c/src/lib/libbsp/i386/ts_386ex/include/wd80x3.h
new file mode 100644
index 0000000000..4bad00993c
--- /dev/null
+++ b/c/src/lib/libbsp/i386/ts_386ex/include/wd80x3.h
@@ -0,0 +1,123 @@
+
+/* Register descriptions */
+/* Controller DP8390.    */
+
+#define DATAPORT	0x10	/* Port Window. */
+#define RESET		0x1f	/* Issue a read for reset */
+#define W83CREG		0x00	/* I/O port definition */
+#define	ADDROM		0x08
+
+/* page 0 read or read/write registers */
+
+#define	CMDR		0x00+RO	
+#define CLDA0  		0x01+RO	/* current local dma addr 0 for read */
+#define CLDA1  		0x02+RO	/* current local dma addr 1 for read */
+#define BNRY   		0x03+RO	/* boundary reg for rd and wr */
+#define TSR    		0x04+RO	/* tx status reg for rd */
+#define NCR    		0x05+RO	/* number of collision reg for rd */
+#define FIFO   		0x06+RO	/* FIFO for rd */
+#define ISR    		0x07+RO	/* interrupt status reg for rd and wr */
+#define CRDA0  		0x08+RO	/* current remote dma address 0 for rd */
+#define CRDA1  		0x09+RO	/* current remote dma address 1 for rd */
+#define RSR    		0x0C+RO	/* rx status reg for rd */
+#define CNTR0  		0x0D+RO	/* tally cnt 0 for frm alg err for rd */
+#define CNTR1  		RO+0x0E	/* tally cnt 1 for crc err for rd */
+#define CNTR2  		0x0F+RO	/* tally cnt 2 for missed pkt for rd */
+
+/* page 0 write registers */
+
+#define PSTART 		0x01+RO	/* page start register */
+#define PSTOP  		0x02+RO	/* page stop register */
+#define TPSR   		0x04+RO	/* tx start page start reg */
+#define TBCR0  		0x05+RO	/* tx byte count 0 reg */
+#define TBCR1  		0x06+RO	/* tx byte count 1 reg */
+#define RSAR0  		0x08+RO	/* remote start address reg 0  */
+#define RSAR1  		0x09+RO	/* remote start address reg 1 */
+#define RBCR0  		0x0A+RO	/* remote byte count reg 0 */
+#define RBCR1  		0x0B+RO	/* remote byte count reg 1 */
+#define RCR    		0x0C+RO	/* rx configuration reg */
+#define TCR    		0x0D+RO	/* tx configuration reg */
+#define DCR    		RO+0x0E	/* data configuration reg */
+#define IMR    		0x0F+RO	/* interrupt mask reg */
+
+/* page 1 registers */
+
+#define PAR   		0x01+RO	/* physical addr reg base for rd and wr */
+#define CURR   		0x07+RO	/* current page reg for rd and wr */
+#define MAR   		0x08+RO	/* multicast addr reg base fro rd and WR */
+#define MARsize	8		/* size of multicast addr space */
+
+/*-----W83CREG command bits-----*/
+#define MSK_RESET  0x80		/* W83CREG masks */
+#define MSK_ENASH  0x40
+#define MSK_DECOD  0x3F		/* memory decode bits, corresponding */
+				/* to SA 18-13. SA 19 assumed to be 1 */
+
+/*-----CMDR command bits-----*/
+#define MSK_STP		0x01	/* stop the chip */
+#define MSK_STA		0x02	/* start the chip */  
+#define MSK_TXP	       	0x04	/* initial txing of a frm */
+#define MSK_RRE		0x08	/* remote read */
+#define MSK_RWR		0x10	/* remote write */
+#define MSK_RD2		0x20	/* no DMA used */
+#define MSK_PG0	       	0x00	/* select register page 0 */
+#define MSK_PG1	       	0x40	/* select register page 1 */
+#define MSK_PG2	       	0x80	/* select register page 2 */
+
+/*-----ISR and TSR status bits-----*/
+#define MSK_PRX 	0x01	/* rx with no error */
+#define MSK_PTX 	0x02	/* tx with no error */
+#define MSK_RXE 	0x04	/* rx with error */
+#define MSK_TXE 	0x08	/* tx with error */
+#define MSK_OVW 	0x10	/* overwrite warning */
+#define MSK_CNT 	0x20	/* MSB of one of the tally counters is set */
+#define MSK_RDC 	0x40	/* remote dma completed */
+#define MSK_RST		0x80	/* reset state indicator */
+
+/*-----DCR command bits-----*/
+#define MSK_WTS		0x01	/* word transfer mode selection */
+#define MSK_BOS		0x02	/* byte order selection */
+#define MSK_LAS		0x04	/* long addr selection */
+#define MSK_BMS		0x08	/* burst mode selection */
+#define MSK_ARM		0x10	/* autoinitialize remote */
+#define MSK_FT00	0x00	/* burst lrngth selection */
+#define MSK_FT01	0x20	/* burst lrngth selection */
+#define MSK_FT10	0x40	/* burst lrngth selection */
+#define MSK_FT11	0x60	/* burst lrngth selection */
+
+/*-----RCR command bits-----*/
+#define MSK_SEP		0x01	/* save error pkts */
+#define MSK_AR	 	0x02	/* accept runt pkt */
+#define MSK_AB		0x04	/* 8390 RCR */
+#define MSK_AM	 	0x08	/* accept multicast  */
+#define MSK_PRO		0x10	/* accept all pkt with physical adr */
+#define MSK_MON		0x20	/* monitor mode */
+
+/*-----TCR command bits-----*/
+#define MSK_CRC		0x01	/* inhibit CRC, do not append crc */
+#define MSK_LOOP	0x02	/* set loopback mode */
+#define MSK_BCST	0x04	/* Accept broadcasts */
+#define MSK_LB01	0x06	/* encoded loopback control */
+#define MSK_ATD		0x08	/* auto tx disable */
+#define MSK_OFST	0x10	/* collision offset enable  */
+
+/*-----receive status bits-----*/
+#define SMK_PRX   0x01		/* rx without error */
+#define SMK_CRC   0x02		/* CRC error */
+#define SMK_FAE   0x04		/* frame alignment error */
+#define SMK_FO    0x08		/* FIFO overrun */
+#define SMK_MPA   0x10		/* missed pkt */
+#define SMK_PHY   0x20		/* physical/multicase address */
+#define SMK_DIS   0x40		/* receiver disable. set in monitor mode */
+#define SMK_DEF	  0x80		/* deferring */
+
+/*-----transmit status bits-----*/
+#define SMK_PTX   0x01		/* tx without error */
+#define SMK_DFR   0x02		/* non deferred tx */
+#define SMK_COL   0x04		/* tx collided */
+#define SMK_ABT   0x08		/* tx abort because of excessive collisions */
+#define SMK_CRS   0x10		/* carrier sense lost */
+#define SMK_FU    0x20		/* FIFO underrun */
+#define SMK_CDH   0x40		/* collision detect heartbeat */
+#define SMK_OWC	  0x80		/* out of window collision */
+