diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2003-08-21 17:05:56 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2003-08-21 17:05:56 +0000 |
commit | fe235a1e289d4ae8be6825180c6aec29cd704298 (patch) | |
tree | bf44a36809fe08cec0a1f26a00765d3dfe134f4e /c/src/lib/libbsp/i386/shared/irq/irq.c | |
parent | 2003-08-21 Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
download | rtems-fe235a1e289d4ae8be6825180c6aec29cd704298.tar.bz2 |
2003-08-21 Till Strauman <strauman@slac.stanford.edu>
PR 456/bsps
* irq/irq.c: Fix race condition when installing an ISR.
Diffstat (limited to 'c/src/lib/libbsp/i386/shared/irq/irq.c')
-rw-r--r-- | c/src/lib/libbsp/i386/shared/irq/irq.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/i386/shared/irq/irq.c b/c/src/lib/libbsp/i386/shared/irq/irq.c index 19de89ae66..2c49a3ab52 100644 --- a/c/src/lib/libbsp/i386/shared/irq/irq.c +++ b/c/src/lib/libbsp/i386/shared/irq/irq.c @@ -235,10 +235,11 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * RATIONALE : to always have the same transition by forcing the user * to get the previous handler before accepting to disconnect. */ + _CPU_ISR_Disable(level); if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) { + _CPU_ISR_Enable(level); return 0; } - _CPU_ISR_Disable(level); /* * store the data provided by user @@ -265,10 +266,14 @@ int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq) int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) { + unsigned int level; + if (!isValidInterrupt(irq->name)) { return 0; } + _CPU_ISR_Disable(level); *irq = rtems_hdl_tbl[irq->name]; + _CPU_ISR_Enable(level); return 1; } @@ -286,10 +291,11 @@ int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) * RATIONALE : to always have the same transition by forcing the user * to get the previous handler before accepting to disconnect. */ + _CPU_ISR_Disable(level); if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) { + _CPU_ISR_Enable(level); return 0; } - _CPU_ISR_Disable(level); /* * disable interrupt at PIC level |