Remove (Abandoned).

4 files changed, 0 insertions, 1099 deletions

diff --git a/c/src/lib/libbsp/i386/i386ex/start/80386ex.h b/c/src/lib/libbsp/i386/i386ex/start/80386ex.h
deleted file mode 100644
index a3ee4c7aba..0000000000
--- a/c/src/lib/libbsp/i386/i386ex/start/80386ex.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- *  Submitted by:
- *
- *    Erik Ivanenko
- *    University of Toronto
- *    erik.ivanenko@utoronto.ca
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-/* REMAP ADDRESSING Registers */
-#define REMAPCFGH	  0x0023
-#define REMAPCFGL	  0x0022
-#define REMAPCFG	  0x0022
-/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
-#define ICW1M	  0xF020
-#define ICW1S	  0xF0A0
-#define ICW2M	  0xF021
-#define ICW2S	  0xF0A1
-#define ICW3M	  0xF021
-#define ICW3S	  0xF0A1
-#define ICW4M	  0xF021
-#define ICW4S	  0xF0A1
-#define OCW1M	  0xF021
-#define OCW1S	  0xF0A1
-#define OCW2M	  0xF020
-#define OCW2S	  0xF0A0
-#define OCW3M	  0xF020
-#define OCW3S	  0xF0A0
-/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
-#define ICW1MDOS	  0x0020
-#define ICW1SDOS	  0x00A0
-#define ICW2MDOS	  0x0021
-#define ICW2SDOS	  0x00A1
-#define ICW3MDOS	  0x0021
-#define ICW3SDOS	  0x00A1
-#define ICW4MDOS	  0x0021
-#define ICW4SDOS	  0x00A1
-#define OCW1MDOS	  0x0021
-#define OCW1SDOS	  0x00A1
-#define OCW2MDOS	  0x0020
-#define OCW2SDOS	  0x00A0
-#define OCW3MDOS	  0x0020
-#define OCW3SDOS	  0x00A0
-
-/* CONFIGURATION Registers */
-#define DMACFG	  0xF830
-#define INTCFG	  0xF832
-#define TMRCFG	  0xF834
-#define SIOCFG	  0xF836
-#define P1CFG	  0xF820
-#define P2CFG	  0xF822
-#define P3CFG	  0xF824
-#define PINCFG	  0xF826
-
-/* WATCHDOG TIMER Registers */
-#define WDTRLDH	  0xF4C0
-#define WDTRLDL	  0xF4C2
-#define WDTCNTH	  0xF4C4
-#define WDTCNTL	  0xF4C6
-#define WDTCLR	  0xF4C8
-#define WDTSTATUS    0xF4CA
-
-/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
-#define TMR0	  0xF040
-#define TMR1	  0xF041
-#define TMR2	  0xF042
-#define TMRCON	  0xF043
-/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
-#define TMR0DOS	  0x0040
-#define TMR1DOS	  0x0041
-#define TMR2DOS	  0x0042
-#define TMRCONDOS    0x0043
-
-/* INPUT/OUTPUT PORT UNIT Registers */
-#define P1PIN	  0xF860
-#define P1LTC	  0xF862
-#define P1DIR	  0xF864
-#define P2PIN	  0xF868
-#define P2LTC	  0xF86A
-#define P2DIR	  0xF86C
-#define P3PIN	  0xF870
-#define P3LTC	  0xF872
-#define P3DIR	  0xF874
-
-/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
-#define RBR0	  0xF4F8
-#define THR0	  0xF4F8
-#define TBR0	  0xF4F8
-#define DLL0	  0xF4F8
-#define IER0	  0xF4F9
-#define DLH0	  0xF4F9
-#define IIR0	  0xF4FA
-#define LCR0	  0xF4FB
-#define MCR0	  0xF4FC
-#define LSR0	  0xF4FD
-#define MSR0	  0xF4FE
-#define SCR0	  0xF4FF
-/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
-#define RBR0DOS	  0x03F8
-#define THR0DOS	  0x03F8
-#define TBR0DOS	  0x03F8
-#define DLL0DOS	  0x03F8
-#define IER0DOS	  0x03F9
-#define DLH0DOS	  0x03F9
-#define IIR0DOS	  0x03FA
-#define LCR0DOS	  0x03FB
-#define MCR0DOS	  0x03FC
-#define LSR0DOS	  0x03FD
-#define MSR0DOS	  0x03FE
-#define SCR0DOS	  0x03FF
-
-/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
-#define RBR1	  0xF8F8
-#define THR1	  0xF8F8
-#define TBR1	  0XF8F8
-#define DLL1	  0xF8F8
-#define IER1	  0xF8F9
-#define DLH1	  0xF8F9
-#define IIR1	  0xF8FA
-#define LCR1	  0xF8FB
-#define MCR1	  0xF8FC
-#define LSR1	  0xF8FD
-#define MSR1	  0xF8FE
-#define SCR1	  0xF8FF
-/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
-#define RBR1DOS	  0x02F8
-#define THR1DOS	  0x02F8
-#define TBR1DOS	  0x02F8
-#define DLL1DOS	  0x02F8
-#define IER1DOS	  0x02F9
-#define DLH1DOS	  0x02F9
-#define IIR1DOS	  0x02FA
-#define LCR1DOS	  0x02FB
-#define MCR1DOS	  0x02FC
-#define LSR1DOS	  0x02FD
-#define MSR1DOS	  0x02FE
-#define SCR1DOS	  0x02FF
-
-/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
-#define SSIOTBUF	  0xF480
-#define SSIORBUF	  0xF482
-#define SSIOBAUD	  0xF484
-#define SSIOCON1	  0xF486
-#define SSIOCON2	  0xF488
-#define SSIOCTR	  0xF48A
-
-/* CHIP SELECT UNIT Registers */
-#define CS0ADL	  0xF400
-#define CS0ADH	  0xF402
-#define CS0MSKL	  0xF404
-#define CS0MSKH	  0xF406
-#define CS1ADL	  0xF408
-#define CS1ADH	  0xF40A
-#define CS1MSKL	  0xF40C
-#define CS1MSKH	  0xF40E
-#define CS2ADL	  0xF410
-#define CS2ADH	  0xF412
-#define CS2MSKL	  0xF414
-#define CS2MSKH	  0xF416
-#define CS3ADL	  0xF418
-#define CS3ADH	  0xF41A
-#define CS3MSKL	  0xF41C
-#define CS3MSKH	  0xF41E
-#define CS4ADL	  0xF420
-#define CS4ADH	  0xF422
-#define CS4MSKL	  0xF424
-#define CS4MSKH	  0xF426
-#define CS5ADL	  0xF428
-#define CS5ADH	  0xF42A
-#define CS5MSKL	  0xF42C
-#define CS5MSKH	  0xF42E
-#define CS6ADL	  0xF430
-#define CS6ADH	  0xF432
-#define CS6MSKL	  0xF434
-#define CS6MSKH	  0xF436
-#define UCSADL	  0xF438
-#define UCSADH	  0xF43A
-#define UCSMSKL	  0xF43C
-#define UCSMSKH	  0xF43E
-
-/* REFRESH CONTROL UNIT Registers */
-
-#define RFSBAD	  0xF4A0
-#define RFSCIR	  0xF4A2
-#define RFSCON	  0xF4A4
-#define RFSADD	  0xF4A6
-
-/* POWER MANAGEMENT CONTROL Registers */
-
-#define PWRCON	  0xF800
-#define CLKPRS	  0xF804
-
-/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
-#define DMA0TAR	  0xF000
-#define DMA0BYC	  0xF001
-#define DMA1TAR	  0xF002
-#define DMA1BYC	  0xF003
-#define DMACMD1	  0xF008
-#define DMASTS	  0xF008
-#define DMASRR	  0xF009
-#define DMAMSK	  0xF00A
-#define DMAMOD1	  0xF00B
-#define DMACLRBP	  0xF00C
-#define DMACLR	  0xF00D
-#define DMACLRMSK    0xF00E
-#define DMAGRPMSK    0xF00F
-#define DMA0REQL	  0xF010
-#define DMA0REQH	  0xF011
-#define DMA1REQL	  0xF012
-#define DMA1REQH	  0xF013
-#define DMABSR	  0xF018
-#define DMACHR	  0xF019
-#define DMAIS	  0xF019
-#define DMACMD2	  0xF01A
-#define DMAMOD2	  0xF01B
-#define DMAIEN	  0xF01C
-#define DMAOVFE	  0xF01D
-#define DMACLRTC	  0xF01E
-#define DMA1TARPL    0xF083
-#define DMA1TARPH    0xF085
-#define DMA0TARPH    0xF086
-#define DMA0TARPL    0xF087
-#define DMA0BYCH	  0xF098
-#define DMA1BYCH	  0xF099
-
-/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
-#define DMA0TARDOS	  0x0000
-#define DMA0BYCDOS	  0x0001
-#define DMA1TARDOS	  0x0002
-#define DMA1BYCDOS	  0x0003
-#define DMACMD1DOS	  0x0008
-#define DMASTSDOS	  0x0008
-#define DMASRRDOS	  0x0009
-#define DMAMSKDOS	  0x000A
-#define DMAMOD1DOS	  0x000B
-#define DMACLRBPDOS  0x000C
-#define DMACLRDOS	  0x000D
-#define DMACLRMSKDOS   0x000E
-#define DMAGRPMSKDOS   0x000F
-#define DMA1TARPLDOS   0x0083
-#define DMA0TARPLDOS   0x0087
-
-/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
-#define PORT92	  0xF092
-/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
-#define PORT92DOS    0x0092
-
diff --git a/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc b/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc
deleted file mode 100644
index bec46baddf..0000000000
--- a/c/src/lib/libbsp/i386/i386ex/start/80386ex.inc
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- *  Submitted by:
- *
- *    Erik Ivanenko
- *    University of Toronto
- *    erik.ivanenko@utoronto.ca
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-/* REMAP ADDRESSING Registers */
-.set REMAPCFGH	 , 0x0023
-.set REMAPCFGL	 , 0x0022
-.set REMAPCFG	 , 0x0022
-/* INTERRUPT CONTROL REGISTERS -- SLOT 15 ADDRESSES */
-.set ICW1M	 , 0xF020
-.set ICW1S	 , 0xF0A0
-.set ICW2M	 , 0xF021
-.set ICW2S	 , 0xF0A1
-.set ICW3M	 , 0xF021
-.set ICW3S	 , 0xF0A1
-.set ICW4M	 , 0xF021
-.set ICW4S	 , 0xF0A1
-.set OCW1M	 , 0xF021
-.set OCW1S	 , 0xF0A1
-.set OCW2M	 , 0xF020
-.set OCW2S	 , 0xF0A0
-.set OCW3M	 , 0xF020
-.set OCW3S	 , 0xF0A0
-/* INTERRUPT CONTROL REGISTERS -- SLOT 0 ADDRESSES */
-.set ICW1MDOS	 , 0x0020
-.set ICW1SDOS	 , 0x00A0
-.set ICW2MDOS	 , 0x0021
-.set ICW2SDOS	 , 0x00A1
-.set ICW3MDOS	 , 0x0021
-.set ICW3SDOS	 , 0x00A1
-.set ICW4MDOS	 , 0x0021
-.set ICW4SDOS	 , 0x00A1
-.set OCW1MDOS	 , 0x0021
-.set OCW1SDOS	 , 0x00A1
-.set OCW2MDOS	 , 0x0020
-.set OCW2SDOS	 , 0x00A0
-.set OCW3MDOS	 , 0x0020
-.set OCW3SDOS	 , 0x00A0
-
-
-/* CONFIGURATION Registers */
-.set DMACFG	 , 0xF830
-.set INTCFG	 , 0xF832
-.set TMRCFG	 , 0xF834
-.set SIOCFG	 , 0xF836
-.set P1CFG	 , 0xF820
-.set P2CFG	 , 0xF822
-.set P3CFG	 , 0xF824
-.set PINCFG	 , 0xF826
-
-/* WATCHDOG TIMER Registers */
-.set WDTRLDH	 , 0xF4C0
-.set WDTRLDL	 , 0xF4C2
-.set WDTCNTH	 , 0xF4C4
-.set WDTCNTL	 , 0xF4C6
-.set WDTCLR	 , 0xF4C8
-.set WDTSTATUS   , 0xF4CA
-
-/* TIMER CONTROL REGISTERS -- SLOT 15 ADDRESSES */
-.set TMR0	 , 0xF040
-.set TMR1	 , 0xF041
-.set TMR2	 , 0xF042
-.set TMRCON	 , 0xF043
-/* TIMER CONTROL REGISTERS -- SLOT 0 ADDRESSES */
-.set TMR0DOS	 , 0x0040
-.set TMR1DOS	 , 0x0041
-.set TMR2DOS	 , 0x0042
-.set TMRCONDOS   , 0x0043
-
-/* INPUT/OUTPUT PORT UNIT Registers */
-.set P1PIN	 , 0xF860
-.set P1LTC	 , 0xF862
-.set P1DIR	 , 0xF864
-.set P2PIN	 , 0xF868
-.set P2LTC	 , 0xF86A
-.set P2DIR	 , 0xF86C
-.set P3PIN	 , 0xF870
-.set P3LTC	 , 0xF872
-.set P3DIR	 , 0xF874
-
-/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 15 ADDRESSES */
-.set RBR0	 , 0xF4F8
-.set THR0	 , 0xF4F8
-.set TBR0	 , 0xF4F8
-.set DLL0	 , 0xF4F8
-.set IER0	 , 0xF4F9
-.set DLH0	 , 0xF4F9
-.set IIR0	 , 0xF4FA
-.set LCR0	 , 0xF4FB
-.set MCR0	 , 0xF4FC
-.set LSR0	 , 0xF4FD
-.set MSR0	 , 0xF4FE
-.set SCR0	 , 0xF4FF
-/* ASYNCHRONOUS SERIAL CHANNEL 0 -- SLOT 0 ADDRESSES */
-.set RBR0DOS	 , 0x03F8
-.set THR0DOS	 , 0x03F8
-.set TBR0DOS	 , 0x03F8
-.set DLL0DOS	 , 0x03F8
-.set IER0DOS	 , 0x03F9
-.set DLH0DOS	 , 0x03F9
-.set IIR0DOS	 , 0x03FA
-.set LCR0DOS	 , 0x03FB
-.set MCR0DOS	 , 0x03FC
-.set LSR0DOS	 , 0x03FD
-.set MSR0DOS	 , 0x03FE
-.set SCR0DOS	 , 0x03FF
-
-/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 15 ADDRESSES */
-.set RBR1	 , 0xF8F8
-.set THR1	 , 0xF8F8
-.set TBR1	 , 0XF8F8
-.set DLL1	 , 0xF8F8
-.set IER1	 , 0xF8F9
-.set DLH1	 , 0xF8F9
-.set IIR1	 , 0xF8FA
-.set LCR1	 , 0xF8FB
-.set MCR1	 , 0xF8FC
-.set LSR1	 , 0xF8FD
-.set MSR1	 , 0xF8FE
-.set SCR1	 , 0xF8FF
-/* ASYNCHRONOUS SERIAL CHANNEL 1 -- SLOT 0 ADDRESSES */
-.set RBR1DOS	 , 0x02F8
-.set THR1DOS	 , 0x02F8
-.set TBR1DOS	 , 0x02F8
-.set DLL1DOS	 , 0x02F8
-.set IER1DOS	 , 0x02F9
-.set DLH1DOS	 , 0x02F9
-.set IIR1DOS	 , 0x02FA
-.set LCR1DOS	 , 0x02FB
-.set MCR1DOS	 , 0x02FC
-.set LSR1DOS	 , 0x02FD
-.set MSR1DOS	 , 0x02FE
-.set SCR1DOS	 , 0x02FF
-
-/* SYNCHRONOUS SERIAL CHANNEL REGISTERS */
-.set SSIOTBUF	 , 0xF480
-.set SSIORBUF	 , 0xF482
-.set SSIOBAUD	 , 0xF484
-.set SSIOCON1	 , 0xF486
-.set SSIOCON2	 , 0xF488
-.set SSIOCTR	 , 0xF48A
-
-/* CHIP SELECT UNIT Registers */
-.set CS0ADL	 , 0xF400
-.set CS0ADH	 , 0xF402
-.set CS0MSKL	 , 0xF404
-.set CS0MSKH	 , 0xF406
-.set CS1ADL	 , 0xF408
-.set CS1ADH	 , 0xF40A
-.set CS1MSKL	 , 0xF40C
-.set CS1MSKH	 , 0xF40E
-.set CS2ADL	 , 0xF410
-.set CS2ADH	 , 0xF412
-.set CS2MSKL	 , 0xF414
-.set CS2MSKH	 , 0xF416
-.set CS3ADL	 , 0xF418
-.set CS3ADH	 , 0xF41A
-.set CS3MSKL	 , 0xF41C
-.set CS3MSKH	 , 0xF41E
-.set CS4ADL	 , 0xF420
-.set CS4ADH	 , 0xF422
-.set CS4MSKL	 , 0xF424
-.set CS4MSKH	 , 0xF426
-.set CS5ADL	 , 0xF428
-.set CS5ADH	 , 0xF42A
-.set CS5MSKL	 , 0xF42C
-.set CS5MSKH	 , 0xF42E
-.set CS6ADL	 , 0xF430
-.set CS6ADH	 , 0xF432
-.set CS6MSKL	 , 0xF434
-.set CS6MSKH	 , 0xF436
-.set UCSADL	 , 0xF438
-.set UCSADH	 , 0xF43A
-.set UCSMSKL	 , 0xF43C
-.set UCSMSKH	 , 0xF43E
-
-/* REFRESH CONTROL UNIT Registers */
-
-.set RFSBAD	 , 0xF4A0
-.set RFSCIR	 , 0xF4A2
-.set RFSCON	 , 0xF4A4
-.set RFSADD	 , 0xF4A6
-
-/* POWER MANAGEMENT CONTROL Registers */
-
-.set PWRCON	 , 0xF800
-.set CLKPRS	 , 0xF804
-
-/* DMA UNIT REGISTERS -- SLOT 15 ADDRESSES */
-.set DMA0TAR	 , 0xF000
-.set DMA0BYC	 , 0xF001
-.set DMA1TAR	 , 0xF002
-.set DMA1BYC	 , 0xF003
-.set DMACMD1	 , 0xF008
-.set DMASTS	 , 0xF008
-.set DMASRR	 , 0xF009
-.set DMAMSK	 , 0xF00A
-.set DMAMOD1	 , 0xF00B
-.set DMACLRBP	 , 0xF00C
-.set DMACLR	 , 0xF00D
-.set DMACLRMSK   , 0xF00E
-.set DMAGRPMSK   , 0xF00F
-.set DMA0REQL	 , 0xF010
-.set DMA0REQH	 , 0xF011
-.set DMA1REQL	 , 0xF012
-.set DMA1REQH	 , 0xF013
-.set DMABSR	 , 0xF018
-.set DMACHR	 , 0xF019
-.set DMAIS	 , 0xF019
-.set DMACMD2	 , 0xF01A
-.set DMAMOD2	 , 0xF01B
-.set DMAIEN	 , 0xF01C
-.set DMAOVFE	 , 0xF01D
-.set DMACLRTC	 , 0xF01E
-.set DMA1TARPL   , 0xF083
-.set DMA1TARPH   , 0xF085
-.set DMA0TARPH   , 0xF086
-.set DMA0TARPL   , 0xF087
-.set DMA0BYCH	 , 0xF098
-.set DMA1BYCH	 , 0xF099
-
-/* DMA UNIT REGISTERS -- SLOT 0 ADDRESSES */
-.set DMA0TARDOS	 , 0x0000
-.set DMA0BYCDOS	 , 0x0001
-.set DMA1TARDOS	 , 0x0002
-.set DMA1BYCDOS	 , 0x0003
-.set DMACMD1DOS	 , 0x0008
-.set DMASTSDOS	 , 0x0008
-.set DMASRRDOS	 , 0x0009
-.set DMAMSKDOS	 , 0x000A
-.set DMAMOD1DOS	 , 0x000B
-.set DMACLRBPDOS , 0x000C
-.set DMACLRDOS	 , 0x000D
-.set DMACLRMSKDOS  , 0x000E
-.set DMAGRPMSKDOS  , 0x000F
-.set DMA1TARPLDOS  , 0x0083
-.set DMA0TARPLDOS  , 0x0087
-
-/* A20GATE AND FAST CPU RESET -- SLOT 15 ADDRESS */
-.set PORT92	 , 0xF092
-/* A20GATE AND FAST CPU RESET -- SLOT 0 ADDRESS */
-.set PORT92DOS   , 0x0092
diff --git a/c/src/lib/libbsp/i386/i386ex/start/macros.inc b/c/src/lib/libbsp/i386/i386ex/start/macros.inc
deleted file mode 100644
index 22b9572f55..0000000000
--- a/c/src/lib/libbsp/i386/i386ex/start/macros.inc
+++ /dev/null
@@ -1,115 +0,0 @@
-/* macros.inc
- *
- * This file assists the board independent startup code
- * by initializing the chip-select channels to 
- * reflect the proper memory configuration.
- *
- * NOTE: No stack has been established when this routine	
- *       is invoked.  It returns to start.s through ldsegs
- *
- *  Submitted by:
- *
- *    Erik Ivanenko
- *    University of Toronto
- *    erik.ivanenko@utoronto.ca
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
- */
-
-.set GDT_CODE_PTR	, 0x10
-.set GDT_DATA_PTR	, 0x18	
-
-.set BOARD_SELECT  , 0x301
-.set BOARD_DATA	   , 0x302
-.set BOARD_LATCH   , 0x303
-
-
-#define SetExRegByte(_register,_value) \
-        movb       $ ## _value, al; \
-	movw	  $ ## _register, dx; \
-        outb       al, dx
-
-#define SetExRegWord(_register,_value) \
-        movw      $ ## _value, ax; \
-	movw      $ ## _register, dx ; \
-        outw      ax, dx
-
-
-#define DESC2(lim_0_15, bas_0_15, bas_16_23, access, gran, bas_24_31) \
- .word lim_0_15 ; \
- .word bas_0_15 ; \
- .byte bas_16_23 ; \
- .byte access ; \
- .byte gran ; \
- .byte bas_24_31
-
-#define DESC3( _base, _limit) \
-.word _limit ; \
-.long _base
-
-/* THE GET_ACCESS IS CHANGED FROM 8E TO 9E */
-
-#define INTERRUPT_GATE( _vector ) \
-	.word   _vector ; \
-	.word	GDT_CODE_PTR ; \
-	.byte   0x0 ; \
-	.byte	0x8E ; \
-	.word	0x0
-
-#define rLOAD_INDEX( _selector, _segment_register) \
-        movl     _selector , _segment_register ; \
-        addb	al, ( eax )
-
-#define rLOAD_SEGMENT( _reg, _segment_register) \
-        mov     _reg , _segment_register ; \
-
-/* #define rLOAD_SEGMENT( _reg, _segment_register) \
-	.code16 ; \
-        mov     _reg , _segment_register ; \
-        .code32 
-*/
-#define pLOAD_SEGMENT( _selector, _segment_register) \
-        movl     $ ##  _selector , eax ; .code16 ; \
-        mov      ax, _segment_register ; .code32 
-
-/* #define MOVE_WORD( _immed32, _reg ) \
-	data16 ; \
-	movl    _immed32, _reg
-*/
-
-#define MOVE_WORD( _immed32, _reg ) \
-	movw    _immed32, _reg
-
-/* #define MOVE_IMMED_WORD( _immed32, _reg ) \
-	data16 ; \
-	mov    $ ## _immed32, _reg
-
-#define CS_OFF( _cs_symbol, _reg ) \
-	data16 ; \
-	mov	_cs_symbol, _reg ; \
-	data16 ;\
-	andl	$0x000ffff, _reg
-
-#define _16_NOPS \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; \
-	nop ; 
-*/
-
diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.S b/c/src/lib/libbsp/i386/i386ex/start/start.S
deleted file mode 100644
index 5867d25c27..0000000000
--- a/c/src/lib/libbsp/i386/i386ex/start/start.S
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- *  This file is the main boot and configuration file for the i386ex.  It is
- *  solely responsible for initializing the internal register set to reflect
- *  the proper board configuration.  This version is the "generic" i386ex
- *  startup:
- *
- *    1) 512K flask ROM @3f80000
- *    2) 1 Mb RAM @ 0x0
- *    3) Timer0 used as RTEMS clock ticker, 1 msec tick rate.
- *    4) READY# is generated by CPU
- *
- *  The file is a multi-section file, with sections as follows:
- *     1) interrupt gates,             in section "ints"
- *     2) interrupt descriptor table,  in section "idt"
- *     3) global descriptor table,     in section "gdt"
- *     4) reset                        in section "reset"
- *     5) and initial boot code        in section " initial"
- *
- *  Submitted by:
- *
- *    Erik Ivanenko
- *    University of Toronto
- *    erik.ivanenko@utoronto.ca
- *
- *  The license and distribution terms for this file may be
- *  found in the file LICENSE in this distribution or at
- *  http://www.rtems.com/license/LICENSE.
- *
- *  $Id$
-
-changes:
-    SetExRegByte(ICW3S  , 0x02 ) # MUST be 0x02 according to intel
-    SetExRegByte(ICW3M  , 0x04 ) # IR2 is cascaded internally: was 0x02 => IR1 is cascaded
-
- */
-
-#include <rtems/asm.h>
-#include "macros.inc"
-#include "80386ex.inc"
-
-/*
- * NEW_GAS Needed for binutils 2.9.1.0.7 and higher
- */
-
-        EXTERN (boot_card)         /* exits to bspstart   */
-	EXTERN (stack_start)       /* defined in startup/linkcmds */
-	EXTERN (Clock_exit)
-
-        PUBLIC (Interrupt_descriptor_table)
-	PUBLIC ( SYM(IDTR) )
-/*	PUBLIC( SYM(_initInternalRegisters) )  */
-
-BEGIN_DATA
-SYM(IDTR):	DESC3( SYM(Interrupt_descriptor_table), 0x07ff );
-
-SYM(Interrupt_descriptor_table):   /* Now in data section */
-	.rept 256
-	.word 0,0,0,0
-	.endr
-
-END_DATA
-
-BEGIN_DATA
-	 PUBLIC (_Global_descriptor_table)
-
-SYM(GDTR):	DESC3( GDT_TABLE, 0x1f ); # one less than the size
-SYM (_Global_descriptor_table):
-SYM(GDT_TABLE):	DESC2(0,0,0,0,0,0);
-SYM(GDT_ALIAS):	DESC2(32,0x1000,0x0,0x93,0,0x0);
-SYM(GDT_CODE):	DESC2(0xffff,0,0x0,0x9B,0xDF,0x00);
-SYM(GDT_DATA):	DESC2(0xffff,0,0x0,0x92,0xDF,0x00); # was CF
-SYM(GDT_END):
-
-END_DATA
-
-/* This section is the section that is used by the interrupt
-   descriptor table.  It is used to provide the IDT with the
-   correct vector offsets.  It is for symbol definition only.
-*/
-
-	.code16
-	.section .reset, "ax"
-		PUBLIC ( SYM(reset) )
-SYM(reset):
-	nop
-	cli
-#ifdef NEW_GAS
-	data32 addr32 jmp     SYM(_initInternalRegisters) /* different section in this file */
-#else
-	jmp     SYM(_initInternalRegisters) /* different section in this file */
-#endif
-/*	.code32                              in case this section moves     */
-	nop                                 /* required by CHIP LAB to pad out size */
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-	nop
-
-	.section .initial, "ax"
-	/* nop */		/* required for linker -- initial jump is to "label - 2"   */
-	/* nop */		/* ie. _initInternalRegisters -2 ( which now == .initial ) */
-/*
- * Enable access to peripheral register at expanded I/O addresses
- */
-SYM(_initInternalRegisters):
-
-	/* .code16 */
-	movw    $0x8000	, ax
-	outb	al	, $REMAPCFGH
-	xchg	al	, ah
-        outb    al,$REMAPCFGL
-	outw    ax,      $REMAPCFG ;
-/*
- * Configure operation of the A20 Address Line
- */
-SYM(A20):
-	movw	$PORT92 , dx
-
-	inb	dx      , al   # clear A20 port reset
-	andb    $0xfe	, al   # b0 Fast Reset(0)=disabled,(1)=reset triggered
-	orb	$0x02	, al   # Bit 1 Fast A20 = 0 (always 0) else enabled.
-	outb	al	, dx
-
-SYM(Watchdog):
-	movw	$WDTSTATUS	, dx    # address the WDT status port
-	inb	dx		, al	# get the WDT status
-	orb	$0x01		, al	# set the CLKDIS bit
-	outb	al		, dx	# disable the clock to the WDT
-
-/*
- * Initialize Refresh Control Unit for:
- *	Refresh Address = 0x0000
-
- *	Refresh gate between rows is 15.6 uSec
- *	Using a CLK2 frequency of 50Mhz ( 25Mhz CPU )
- *	The refresh unit is enabled
- *	The refresh pin is not used.
- */
-
-SYM(InitRCU):
-	SetExRegWord( RFSCIR , 390)	# refresh interval was 390, tried 312
-	SetExRegWord( RFSBAD , 0x0)	# base address
-	SetExRegWord( RFSADD , 0x0)	# address register
-	SetExRegWord( RFSCON , 0x8000)	# enable bit
-
-/*
- * Initialize clock and power mgmt unit for:
- *	Clock Frequency = 50 Mhz
- *	Prescaled clock output = 1 Mhz
- *      Normal halt instructions
- */
-
-SYM(InitClk):
-	SetExRegByte( PWRCON, 0x0 )
-	SetExRegWord( CLKPRS, 0x17)   # 0x13 for 1.19318 MHz.  0x17 for 1MHz.
-
-/**************************************************************
- * Initialize the Pin Configurations
- *************************************************************/
-
-/*
- *	Initialize I/O port 1 for:
- *	PIN 0 = 1,	DCD0# to package pin
- *	PIN 1 = 1,	RTS0# to package pin
- *	PIN 2 = 1,	DTR0# to package pin
- *	PIN 3 = 1,	DSR0# to package pin
- *	PIN 4 = 1,	RI0# to package pin
- *	PIN 5 = 0,	Outport (FLASH Vpp Enable, 0=Enable 1=Disable)
- *	PIN 6 = 0,	Outport (P16_HOLD to 386ex option header JP7 pin 5)
- *	PIN 7 = 0,	Outport (P17_HOLD to 386ex option header JP7 pin 3)
- */
-
-SYM(InitPort1):
-	SetExRegByte( P1LTC	, 0xff )
-	SetExRegByte( P1DIR	, 0x0  )
-	SetExRegByte( P1CFG	, 0x1f)
-
-/*
- *	Initialize I/O port 2 for:
- *	PIN 0 = 0,	Outport (P20_CS0# to 386ex option header JP7 pin 11)
- *	PIN 1 = 0,	Outport (P21_CS1# to 386ex option header JP7 pin 9)
- *	PIN 2 = 1,	CS2# (SMRAM) If not using CS2 can be configured as.?
- *	PIN 3 = 0,	Outport ( no connect )
- *	PIN 4 = 1,	CS#4 (DRAM)
- *	PIN 5 = 1,	RXD0 input. See not for I/0 port 1 pins 1-4
- *	PIN 6 = 1,	TXD0 output.
- *	PIN 7 = 1,	CTS0# input.
- */
-
-SYM(InitPort2):
-	SetExRegByte( P2LTC	, 0xff )
-	SetExRegByte( P2DIR	, 0x0  )
-	SetExRegByte( P2CFG	, 0xfe)
-
-/*
- *	Initialize I/O port 3 P3CFG
- *	PIN 0 = 1,	TMROUT0 to package pin
- *	PIN 1 = 0,	(TMROUT1 to 386ex option header JP7 pin 23)
- *	PIN 2 = 0,	INT0 (IR1) disabled, (P3.2 out to JP7 pin 21)
- *	PIN 3 = 0,	INT1 (IR5) disbled (P3.3  to option header JP7 pin 19)
- *	PIN 4 = 0,	INT2 (IR6) disbled (P3.4 to option header JP7 pin 17)
- *	PIN 5 = 0,	INT2 (IR7) disabled (P3.5 to 386ex header JP7 pin 15)
- *	PIN 6 = 0,	Inport (Debugger Break P3.6/PWRD to package pin )
- *                      P3.6 selected
- *	PIN 7 = 0,	COMCLK output disabled, 1.8432 Mhz OSC1 oscillator.
- *                      ( Debbugger uses COMCLK as the clocking source )
- *                      P3.7 connected to package pin.
- */
-
-SYM(InitPort3):
-	SetExRegByte( P3LTC	, 0xff )
-	SetExRegByte( P3DIR	, 0x41 )
-	SetExRegByte( P3CFG	, 0x09 )  # can check TMROUT0
-/*
- *	Initialize Peripheral Pin Configurations:
- *	PIN 0 = 1,	RTS1# to package pin
- *	PIN 1 = 1,	DTR1# to package pin
- *	PIN 2 = 1,	TXD1 out to package pin
- *	PIN 3 = 0,	EOP#/TC
- *	PIN 4 = 0,	DACK0#
- *	PIN 5 = 1,	Timer2
- *	PIN 6 = 0,	0 => CS6# connected to package pin
- *	PIN 7 = 0,	Don't care
- */
-
-SYM(InitPeriph):
-	SetExRegByte( PINCFG , 0x24)
-
-/*
- *	Initialize the Asynchronous Serial Ports:
- *	BIT 7 = 1,	Internal SIO1 modem signals
- *	BIT 6 = 1,	Internal SIO0 modem signals
- *	BIT 2 = 0,	PSCLK for SSIO clock
- *	BIT 1 = 1,	SERCLK for SIO1 clock
- *	BIT 0 = 1,	SERCLK for SIO0 clock
- */
-
-SYM(InitSIO):
-	SetExRegByte( SIOCFG, 0xC3 ) # SIOn clocked internally
-
-	SetExRegByte( LCR0,	0x80 )  # latch DLL0, DLH0
-	SetExRegByte( DLL0, 0x51 )	# 0x51 sets to 9600 baud, 0x28=19.2k, 0x7 -> 115.2k
-	SetExRegByte( DLH0, 0x00 )  # 0x145 is 2400 baud
-	SetExRegByte( LCR0, 0x03 )  # enable r/w buffers, IER0 accessible
-			            # mode 8-n-1
-	SetExRegByte( IER0, 0x00 )  # was 0x0f All interrupts detected
-
-	SetExRegByte( LCR1, 0x80 )  # latch DLL0, DLH0
-	SetExRegByte( DLL1, 0x51 )  # 0x51 set to 9600 baud, 0x7 = 115200
-	SetExRegByte( DLH1, 0x00 )  # 0x145 is 2400 baud
- 	SetExRegByte( LCR1, 0x03 )  # enable r/w buffers, IER1 accessible
-					# reg 8-n-1
-	SetExRegByte( IER1, 0x00 )  # was 0x0f - All interrupts detected
-
-SYM(InitMCR):
-/*
- *	Initialize Timer for:
- *	BIT 7 = 1,	Timer clocks disabled
- *      BIT 6 = 0,      Reserved
- *	BIT 5 = 1,	TMRCLK2 instead of Vcc to Gate2
- *	BIT 4 = 0,	PSCLK to CLK2
- *	BIT 3 = 1,	TMRCLK1 instead of Vcc to Gate1
- *	BIT 2 = 0,	PSCLK to Gate1
- *	BIT 1 = 0,	Vcc to Gate0
- *	BIT 0 = 0,	PSCLK to Gate0
- */
-
-SYM(InitTimer):
-	SetExRegByte(TMRCFG , 0x80 ) # All counters disabled, Gates 0,1
-	                             # and 2 are set to Vcc
-
-	SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB
-	SetExRegByte(TMR0   , 0x00 ) # sfa
-	SetExRegByte(TMR0   , 0x00 ) # sfa
-
-	SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc
-	SetExRegByte(TMR1   , 0x00 ) # sfa
-	SetExRegByte(TMR1   , 0x00 ) # sfa
-
-	SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc
-	SetExRegByte(TMR2   , 0x00 ) #
-	SetExRegByte(TMR2   , 0x00 ) #
-
-	SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00
-
-/*
- *	Initialize the DMACFG register for:
- *	BIT 7    = 1  ,	Disable DACK#1
- *	BITs 6:4 = 100, TMROUT2 connected to DRQ1
- *	BIT 3    = 1  ,	Disable DACK0#
- *	BIT 2:0  = 000,	Pin is connected to DRQ0
- */
-
-	SetExRegByte(DMACFG , 0xC0  )
-	SetExRegByte(DMACMD1, 0x00 ) # disable both DMA channels
-	SetExRegByte(DMAMOD1, 0x40 )
-/*
- *	Initialize the INTCFG register for:
- *	BIT 7 = 0,	8259 cascade disabled
- *	BIT 3 = 0,	SLAVE IR6 connected to Vss
- *	BIT 2 = 0,	SLAVE IR5 connected to Vss
- *	BIT 1 = 0,	SLAVE IR1 connected to SSIOINT
- *	BIT 0 = 0,	SLAVE IR0 connected to Vss
- */
-
-SYM(InitInt):
-
-	cli				  # !
-/*	SetExRegByte(OCW3S, 0x20)  # address the Slave status port
-	movw	$OCW3S	, dx
-	inb	dx	, al	# Read the IRR.
-
-	SetExRegByte(OCW3M, 0x20)  # address the Master status port
-	movw	$OCW3M	, dx
-	inb	dx	, al	# Read the IRR.
-*/
-
-	SetExRegByte(ICW1S  , 0x11 ) # EDGE TRIGGERED
-	SetExRegByte(ICW2S  , 0x28 ) # Slave base vector after Master
-	SetExRegByte(ICW3S  , 0x02 ) # slave cascaded to IR2 on master
-	SetExRegByte(ICW4S  , 0x01 ) # must be 0x01
-
-	SetExRegByte(ICW1M  , 0x11 ) # edge triggered
-	SetExRegByte(ICW2M  , 0x20 ) # base vector starts at byte 32
-	SetExRegByte(ICW3M  , 0x04)  # IR2 is cascaded internally
-	SetExRegByte(ICW4M  , 0x01 ) # fully nested mode
-
-	SetExRegByte(OCW1M  , 0xde )	# IR0  only = 0xfe.
-					# for IR5 and IR0 active use 0xde
-					# for IR0 and IR2 use 0xfa
-	SetExRegByte(INTCFG , 0x00 )
-
-SYM(SetCS4):
-	SetExRegWord(CS4ADL , 0x702)         #Configure chip select 4
-	SetExRegWord(CS4ADH , 0x00)
-	SetExRegWord(CS4MSKH, 0x03F)
-	SetExRegWord(CS4MSKL, 0xFC01)
-
-SYM(SetUCS1):
- 	SetExRegWord(UCSADL , 0x0304)      # 512K block starting at 0x80000 until 0x3f80000
- 	SetExRegWord(UCSADH , 0x03F8)
-	SetExRegWord(UCSMSKH, 0x03F7)
-	SetExRegWord(UCSMSKL, 0xFC01)     # configure upper chip select
-
-/******************************************************
-* The GDT must be in RAM since it must be writeable,
-* So, move the whole data section down.
-********************************************************/
-
-	movw $ _ram_data_offset	, di
-	movw $ _ram_data_segment, cx
-	mov  cx                 , es
-
-	movw $ _data_size	, cx
-	movw $ _rom_data_segment, ax
-	movw $ _rom_data_offset	, si
-	mov  ax                 , ds
-
-	repne
-	movsb
-
-/*****************************
- * Load the Global Descriptor
- * Table Register
- ****************************/
-
-#ifdef NEW_GAS
-	data32 addr32 lgdt SYM(GDTR) #  location of GDT
-#else
-        lgdt SYM(GDTR) #  location of GDT
-#endif
-
-SYM(SetUCS):
- 	SetExRegWord(UCSADL, 0x0702)      # now 512K starting at 0x3f80000.
- 	SetExRegWord(UCSADH, 0x03f8)
-	SetExRegWord(UCSMSKH, 0x0007)
-	SetExRegWord(UCSMSKL, 0xFC01)     # configure upper chip select
-
-	/*
-	 * SRAM chip select:	 16 bit bus size,starting 16Mb, size 512k,
-	 *			 4 waits
-	 */
-
-#ifdef UT_I386EX
-
-SYM(SetCS1):
-	SetExRegWord(CS1ADL,  0x0000)
-	SetExRegWord(CS1ADH,  0x000E)
-	SetExRegWord(CS1MSKH, 0x0000)
-	SetExRegWord(CS1MSKL, 0x0001)
-
-SYM(SetCS2):
-	SetExRegWord(CS2ADL,  0x0704)
-	SetExRegWord(CS2ADH,  0x0100)
-	SetExRegWord(CS2MSKH, 0x0003)
-	SetExRegWord(CS2MSKL, 0xfc01)
-
-	/*
-	 * Real-time clock:	8 bit bus size, starting@16Mb+512K, size 32k
-	 *                       4 waits
-	 */
-SYM(SetCS3):
-	SetExRegWord(CS3ADL,  0x0504)
-	SetExRegWord(CS3ADH,  0x0108)
-	SetExRegWord(CS3MSKH, 0x0000)
-	SetExRegWord(CS3MSKL, 0x7c01)
-
-#endif
-/***************************
- * Switch to Protected Mode
- ***************************/
-
-	mov	cr0, eax
-	orw	$0x1, ax
-	mov	eax, cr0
-
-/**************************
- * Flush prefetch queue,
- * and load CS selector
- *********************/
-
-	ljmpl $ GDT_CODE_PTR , $  SYM(_load_segment_registers) # sets the code selector
-
-/*
- * Load the segment registers
- */
-SYM(_load_segment_registers):
-	.code32
-	pLOAD_SEGMENT( GDT_DATA_PTR, fs)
-	pLOAD_SEGMENT( GDT_DATA_PTR, gs)
-	pLOAD_SEGMENT( GDT_DATA_PTR, ss)
-	pLOAD_SEGMENT( GDT_DATA_PTR, ds)
-	pLOAD_SEGMENT( GDT_DATA_PTR, es)
-
-/*
- *  Set up the stack
- */
-
-SYM(lidtr):
-	lidt	SYM(IDTR)
-
-SYM (_establish_stack):
-	movl	$end, eax               # stack starts right after bss
-	movl	$stack_origin, esp      # this is the high starting address
-	movl	$stack_origin, ebp
-
-/*
- *  Zero out the BSS segment
- */
-SYM (zero_bss):
-        cld                             # make direction flag count up
-        movl    $ SYM (end),ecx        # find end of .bss
-        movl    $ SYM (_bss_start),edi # edi = beginning of .bss
-        subl    edi,ecx               # ecx = size of .bss in bytes
-        shrl    ecx                    # size of .bss in longs
-        shrl    ecx
-        xorl    eax,eax               # value to clear out memory
-        repne                           # while ecx != 0
-        stosl                           #   clear a long in the bss
-
-/*
- *  Transfer control to User's Board Support Package
- */
-        pushl   $0                       # command line
-
-	movw    $0xFFFB, SYM(i8259s_cache)	# ICU mask values reflect
-						# initial ICU state
-	call SYM(boot_card)
-        addl    $12,esp
-
-	cli                              # stops interrupts from being processed after hlt!
-	hlt                              # shutdown
-
-END