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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-04-20 20:20:47 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2011-04-20 20:20:47 +0000 |
| commit | cb4c90b227661280d5da48ecae0aa62890b55494 (patch) | |
| tree | 06bda5f63f8a254bc508573c835245d4a1a48cae /c/src/lib/libbsp/bfin | |
| parent | 2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu> (diff) | |
| download | rtems-cb4c90b227661280d5da48ecae0aa62890b55494.tar.bz2 | |
2011-04-20 Rohan Kangralkar <rkangral@ece.neu.edu>
PR 1781/bsps
* bf52x/include: Added additional MMR.
* bf52x/interrupt: The BF52X processors have a different
System interrupt controller than present in the 53X range of
processors. The 52X have 8 interrupt assignment registers. The
implementation uses tables to increase predictability.
* serial/uart.?: Added DMA based and interrupt based transfer
support. The uart code used a single ISR for TX and RX and tried
to identify and multiplex inside the ISR. In the new code the
type of interrupt is identified by the central ISR dispatcher
bf52x/interrupt or interrupt/. This simplifies the UART ISR.
Diffstat (limited to 'c/src/lib/libbsp/bfin')
0 files changed, 0 insertions, 0 deletions