diff options
author | Daniel Ramirez <javamonn@gmail.com> | 2013-12-24 04:14:15 -0600 |
---|---|---|
committer | Gedare Bloom <gedare@rtems.org> | 2013-12-24 09:50:09 -0500 |
commit | 0c09ccf3d50ab8df241b2e8f74817b6abc9c26ff (patch) | |
tree | 4eb2ea45dbeae005575e20da4a3d0ebe8a27a412 /c/src/lib/libbsp/bfin | |
parent | cpukit/capture: Print the uptime and diff in ctrace. (diff) | |
download | rtems-0c09ccf3d50ab8df241b2e8f74817b6abc9c26ff.tar.bz2 |
bfin_TLL6527: added new doxygen
Diffstat (limited to 'c/src/lib/libbsp/bfin')
-rw-r--r-- | c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h | 78 | ||||
-rw-r--r-- | c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h | 15 | ||||
-rw-r--r-- | c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h | 15 | ||||
-rw-r--r-- | c/src/lib/libbsp/bfin/shared/doxygen.h | 11 |
4 files changed, 96 insertions, 23 deletions
diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h b/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h index 4314743289..40964c6e7c 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h +++ b/c/src/lib/libbsp/bfin/TLL6527M/include/bsp.h @@ -1,4 +1,10 @@ /** + * @file + * @ingroup bfin_tll6527m + * @brief Global BSP definitions. + */ + +/** *@file bsp.h * * This include file contains all board IO definitions for TLL6527M. @@ -29,8 +35,14 @@ extern "C" { #include <rtems/bfin/bf52x.h> #include <bf52x.h> +/** + * @defgroup bfin_tll6527m TLL6527M Support + * @ingroup bsp_bfin + * @brief TLL6527M Support Package + * @{ + */ -/* +/* * PLL and clock setup values: */ @@ -44,33 +56,53 @@ extern "C" { * SCLK = 130 MHz */ -#define PLL_CSEL 0x0000 /* CCLK = VCO */ -#define PLL_SSEL 0x0003 /* SCLK = CCLK/3 */ -#define PLL_MSEL 0x3A00 /* VCO = 29xCLKIN */ -#define PLL_DF 0x0001 /* CLKIN = XTL/2 */ +/** + * @name PLL Configuration + * @{ + */ -#define CLKIN (25000000) /* Input clock to the PLL */ -#define CCLK (600000000) /* CORE CLOCK */ -#define SCLK (100000000) /* SYSTEM CLOCK */ +#define PLL_CSEL 0x0000 ///< @brief CCLK = VCO */ +#define PLL_SSEL 0x0003 ///< @brief SCLK = CCLK/3 */ +#define PLL_MSEL 0x3A00 ///< @brief VCO = 29xCLKIN */ +#define PLL_DF 0x0001 ///< @brief CLKIN = XTL/2 */ -/* - * UART setup values +/** @} */ + +/** + * @name Clock setup values + * @{ + */ + +#define CLKIN (25000000) ///< @brief Input clock to the PLL */ +#define CCLK (600000000) ///< @brief CORE CLOCK */ +#define SCLK (100000000) ///< @brief SYSTEM CLOCK */ + +/** @} */ + +/** + * @name UART setup values + * @{ */ -#define BAUDRATE 57600 /* Console Baudrate */ -#define WORD_5BITS 0x00 /* 5 bits word */ -#define WORD_6BITS 0x01 /* 6 bits word */ -#define WORD_7BITS 0x02 /* 7 bits word */ -#define WORD_8BITS 0x03 /* 8 bits word */ -#define EVEN_PARITY 0x18 /* Enable EVEN parity */ -#define ODD_PARITY 0x08 /* Enable ODD parity */ -#define TWO_STP_BIT 0x04 /* 2 stop bits */ - -rtems_isr_entry set_vector( /* returns old vector */ - rtems_isr_entry handler, /* isr routine */ - rtems_vector_number vector, /* vector number */ - int type /* RTEMS or RAW intr */ + +#define BAUDRATE 57600 ///< @brief Console Baudrate */ +#define WORD_5BITS 0x00 ///< @brief 5 bits word */ +#define WORD_6BITS 0x01 ///< @brief 6 bits word */ +#define WORD_7BITS 0x02 ///< @brief 7 bits word */ +#define WORD_8BITS 0x03 ///< @brief 8 bits word */ +#define EVEN_PARITY 0x18 ///< @brief Enable EVEN parity */ +#define ODD_PARITY 0x08 ///< @brief Enable ODD parity */ +#define TWO_STP_BIT 0x04 ///< @brief 2 stop bits */ + +/** @} */ + +rtems_isr_entry set_vector( ///< @brief returns old vector */ + rtems_isr_entry handler, ///< @brief isr routine */ + rtems_vector_number vector, ///< @brief vector number */ + int type ///< @brief RTEMS or RAW intr */ ); +/** @} */ + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h b/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h index 7c07a32820..483798695e 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h +++ b/c/src/lib/libbsp/bfin/TLL6527M/include/cplb.h @@ -1,3 +1,9 @@ +/** + * @file + * @ingroup tll6527m_cplb + * @brief CPLB configurations. + */ + /* cplb.h * * Copyright (c) 2006 by Atos Automacao Industrial Ltda. @@ -10,6 +16,13 @@ #ifndef _CPLB_H #define _CPLB_H +/** + * @defgroup tll6527m_cplb CPLB Configuration + * @ingroup bfin_tll6527m + * @brief CPLB Configuration + * @{ + */ + /* CPLB configurations */ #define CPLB_DEF_CACHE_WT CPLB_L1_CHBL | CPLB_WT #define CPLB_DEF_CACHE_WB CPLB_L1_CHBL @@ -29,4 +42,6 @@ #define CPLB_DDOCACHE_WT CPLB_DNOCACHE | CPLB_DEF_CACHE_WT #define CPLB_DDOCACHE_WB CPLB_DNOCACHE | CPLB_DEF_CACHE_WB +/** @} */ + #endif /* _CPLB_H */ diff --git a/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h b/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h index 33dd91f820..449bd08622 100644 --- a/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h +++ b/c/src/lib/libbsp/bfin/TLL6527M/include/tm27.h @@ -1,3 +1,9 @@ +/** + * @file + * @ingroup tll6527m_tm27 + * @brief Interrupt mechanisms for tm27 test. + */ + /* * tm27.h * @@ -15,6 +21,13 @@ #ifndef __tm27_h #define __tm27_h +/** + * @defgroup tll6527m_tm27 TM27 Test Support + * @ingroup bfin_tll6527m + * @brief Interrupt Mechanisms for TM27 + * @{ + */ + /* * Define the interrupt mechanism for Time Test 27 */ @@ -32,4 +45,6 @@ #define Lower_tm27_intr() /* empty */ +/** @} */ + #endif diff --git a/c/src/lib/libbsp/bfin/shared/doxygen.h b/c/src/lib/libbsp/bfin/shared/doxygen.h new file mode 100644 index 0000000000..752b513868 --- /dev/null +++ b/c/src/lib/libbsp/bfin/shared/doxygen.h @@ -0,0 +1,11 @@ + /** + * @defgroup bsp_bfin Blackfin + * @ingroup bsp_kit + * @brief Blackfin Board Support Packages + */ + + /** + * @defgroup bfin_shared Blackfin Shared Modules + * @ingroup bsp_bfin + * @brief Blackfin Shared Modules + */ |