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authorJoel Sherrill <joel.sherrill@OARcorp.com>2008-09-10 20:32:27 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2008-09-10 20:32:27 +0000
commit018e3821cc0c85913d68855f8770231be760cb9a (patch)
tree479c8eab826bda441380411f04198cf11941a091 /c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c
parentRemove. (diff)
downloadrtems-018e3821cc0c85913d68855f8770231be760cb9a.tar.bz2
2008-09-10 Joel Sherrill <joel.sherrill@oarcorp.com>
* Makefile.am, configure.ac, startup/bspstart.c, startup/linkcmds: Split out bsp_get_work_area() into its own file and user BSP Framework to perform more initialization.
Diffstat (limited to 'c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c')
-rw-r--r--c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c169
1 files changed, 61 insertions, 108 deletions
diff --git a/c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c b/c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c
index 2da422b9ed..57ebb4138b 100644
--- a/c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c
+++ b/c/src/lib/libbsp/bfin/eZKit533/startup/bspstart.c
@@ -26,56 +26,49 @@
#include <libcpu/interrupt.h>
const unsigned int dcplbs_table[16][2] = {
- { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
- { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */
- { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */
- { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
-
- { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 3 */
- { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 2 (Secnd) */
- { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 1 (Prim B) */
- { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 (Prim A) */
-
- { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
- { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
- { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
- { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
- { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
- { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
-
- { 0xffffffff, 0xffffffff } /* end of section - termination */
-
- }
-;
+ { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) },
+ { 0xFF900000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data B */
+ { 0xFF800000, (PAGE_SIZE_1MB | CPLB_D_PAGE_MGMT | CPLB_WT) }, /* L1 Data A */
+ { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) },
+ { 0x20300000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 3 */
+ { 0x20200000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 2 (Secnd) */
+ { 0x20100000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 1 (Prim B) */
+ { 0x20000000, (PAGE_SIZE_1MB | CPLB_DNOCACHE) }, /* Async Memory Bank 0 (Prim A) */
+
+ { 0x02400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x02000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00C00000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00800000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00400000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0x00000000, (PAGE_SIZE_4MB | CPLB_DNOCACHE) },
+ { 0xffffffff, 0xffffffff } /* end of section - termination */
+
+};
const unsigned int _icplbs_table[16][2] = {
- { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, /* L1 Code */
- { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
- { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
-
- { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 3 */
- { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 2 (Secnd) */
- { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 1 (Prim B) */
- { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 0 (Prim A) */
-
- { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
- { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
- { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
- { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
- { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
- { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
-
- { 0xffffffff, 0xffffffff } /* end of section - termination */
-
- }
-;
+ { 0xFFA00000, (PAGE_SIZE_1MB | CPLB_I_PAGE_MGMT | CPLB_I_PAGE_MGMT | 0x4) }, /* L1 Code */
+ { 0xEF000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* AREA DE BOOT */
+ { 0xFFB00000, (PAGE_SIZE_1MB | CPLB_INOCACHE) },
+ { 0x20300000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 3 */
+ { 0x20200000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 2 (Secnd) */
+ { 0x20100000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 1 (Prim B) */
+ { 0x20000000, (PAGE_SIZE_1MB | CPLB_INOCACHE) }, /* Async Memory Bank 0 (Prim A) */
+
+ { 0x02400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x02000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00C00000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00800000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00400000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0x00000000, (PAGE_SIZE_4MB | CPLB_INOCACHE) },
+ { 0xffffffff, 0xffffffff } /* end of section - termination */
+
+};
/*
* Use the shared implementations of the following routines
*/
-void bsp_libc_init( void *, uint32_t, int );
void Init_PLL (void);
void Init_EBIU (void);
void Init_Flags(void);
@@ -84,29 +77,13 @@ void Init_RTC (void);
void null_isr(void);
/*
- * Function: bsp_pretasking_hook
- * Created: 95/03/10
- *
- * Description:
* BSP pretasking hook. Called just before drivers are initialized.
* Used to setup libc and install any BSP extensions.
- *
- * NOTES:
- * Must not use libc (to do io) from here, since drivers are
- * not yet initialized.
- *
*/
void bsp_pretasking_hook(void)
{
- extern int HeapBase;
- extern int HeapSize;
- void *heapStart = &HeapBase;
- unsigned long heapSize = (unsigned long)&HeapSize;
-
- bfin_interrupt_init();
-
- bsp_libc_init(heapStart, heapSize, 0);
+ bfin_interrupt_init();
}
/*
@@ -117,48 +94,26 @@ void bsp_pretasking_hook(void)
void bsp_start( void )
{
-
- extern void * _WorkspaceBase;
-
/* BSP Hardware Initialization*/
Init_RTC(); /* Blackfin Real Time Clock initialization */
Init_PLL(); /* PLL initialization */
Init_EBIU(); /* EBIU initialization */
Init_Flags(); /* GPIO initialization */
- /*
- * Allocate the memory for the RTEMS Work Space. This can come from
- * a variety of places: hard coded address, malloc'ed from outside
- * RTEMS world (e.g. simulator or primitive memory manager), or (as
- * typically done by stock BSPs) by subtracting the required amount
- * of work space from the last physical address on the CPU board.
- */
-
- /*
- * Need to "allocate" the memory for the RTEMS Workspace and
- * tell the RTEMS configuration where it is. This memory is
- * not malloc'ed. It is just "pulled from the air".
- */
-
- Configuration.work_space_start = (void *) &_WorkspaceBase;
-
int i=0;
for (i=5;i<16;i++) {
set_vector((rtems_isr_entry)null_isr, i, 1);
}
-
}
- /*
- * Init_PLL
- *
- * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL.
- * See "../eZKit533/include/bsp.h" for more information.
- */
-
+/*
+ * Init_PLL
+ *
+ * Routine to initialize the PLL. The Ezkit uses a 27 Mhz XTAL.
+ * See "../eZKit533/include/bsp.h" for more information.
+ */
void Init_PLL (void)
{
-
unsigned int n;
/* Configure PLL registers */
@@ -173,7 +128,6 @@ void Init_PLL (void)
/* Delay for PLL stabilization */
for (n=0; n<200; n++) {}
-
}
/*
@@ -196,11 +150,11 @@ void Init_EBIU (void)
*/
}
- /*
- * Init_Flags
- *
- * Enable LEDs port
- */
+/*
+ * Init_Flags
+ *
+ * Enable LEDs port
+ */
void Init_Flags(void)
{
*((uint16_t*)FIO_INEN) = 0x0100;
@@ -229,20 +183,19 @@ uint8_t getLED (void)
return *((uint8_t*)FlashA_PortB_Data);
}
-void initCPLB() {
-
- int i = 0;
- unsigned int *addr;
- unsigned int *data;
+void initCPLB()
+{
+ int i = 0;
+ unsigned int *addr;
+ unsigned int *data;
- addr = (unsigned int *)0xffe00100;
- data = (unsigned int *)0xffe00200;
-
- while ( dcplbs_table[i][0] != 0xffffffff ) {
- *addr = dcplbs_table[i][0];
- *data = dcplbs_table[i][1];
-
- addr++;
- data++;
- }
+ addr = (unsigned int *)0xffe00100;
+ data = (unsigned int *)0xffe00200;
+
+ while ( dcplbs_table[i][0] != 0xffffffff ) {
+ *addr = dcplbs_table[i][0];
+ *data = dcplbs_table[i][1];
+ addr++;
+ data++;
+ }
}