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| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-02-17 10:22:16 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:10:54 +0100 |
| commit | 9fcd1b355617135dda95fd7b8bb243bacf0bdc3f (patch) | |
| tree | 95216c0e0aaa499537344d5950b5f504f3205108 /c/src/lib/libbsp/arm/xilinx-zynq | |
| parent | bsp/arm: Add SCU errata handling for L2C-310 cache (diff) | |
| download | rtems-9fcd1b355617135dda95fd7b8bb243bacf0bdc3f.tar.bz2 | |
bsp/arm: Add handling for level 2 L2C-310 cache controller
arm-l2c-310/cache_.h contains the handling for the L2C-310
level 2 cache controller from arm. It references the arm
level 1 cache handling in the new file arm-cache-l1.h.
Diffstat (limited to 'c/src/lib/libbsp/arm/xilinx-zynq')
0 files changed, 0 insertions, 0 deletions