bsp/xilinx-zynq: New BSP

5 files changed, 367 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
new file mode 100644
index 0000000000..0934800146
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_BSP_H
+#define LIBBSP_ARM_XILINX_ZYNQ_BSP_H
+
+#include <bspopts.h>
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/console.h>
+#include <rtems/clockdrv.h>
+
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_ARM_MMU_CLIENT_DOMAIN 15U
+
+#define BSP_ARM_MMU_READ_ONLY \
+  ((BSP_ARM_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
+    | ARM_MMU_SECT_AP_0 \
+    | ARM_MMU_SECT_AP_2 \
+    | ARM_MMU_SECT_DEFAULT)
+
+#define BSP_ARM_MMU_READ_ONLY_CACHED \
+  (BSP_ARM_MMU_READ_ONLY | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
+
+#define BSP_ARM_MMU_READ_WRITE \
+  ((BSP_ARM_MMU_CLIENT_DOMAIN << ARM_MMU_SECT_DOMAIN_SHIFT) \
+    | ARM_MMU_SECT_AP_0 \
+    | ARM_MMU_SECT_DEFAULT)
+
+#define BSP_ARM_MMU_READ_WRITE_CACHED \
+  (BSP_ARM_MMU_READ_WRITE | ARM_MMU_SECT_C | ARM_MMU_SECT_B)
+
+#define BSP_ARM_MMU_READ_WRITE_DATA \
+  BSP_ARM_MMU_READ_WRITE_CACHED
+
+#define BSP_ARM_MMU_READ_ONLY_DATA \
+  BSP_ARM_MMU_READ_ONLY_CACHED
+
+#define BSP_ARM_MMU_CODE BSP_ARM_MMU_READ_ONLY_CACHED
+
+#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
+
+typedef enum {
+  BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL,
+  BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE
+} zynq_fatal_code;
+
+void zynq_fatal(zynq_fatal_code code) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_BSP_H */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h
new file mode 100644
index 0000000000..97817681c3
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
+#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
+
+#ifndef ASM
+
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#include <bsp/arm-a9mpcore-irq.h>
+#include <bsp/arm-gic-irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define ZYNQ_IRQ_CPU_0 32
+#define ZYNQ_IRQ_CPU_1 33
+#define ZYNQ_IRQ_L2_CACHE 34
+#define ZYNQ_IRQ_OCM 35
+#define ZYNQ_IRQ_PMU_0 37
+#define ZYNQ_IRQ_PMU_1 38
+#define ZYNQ_IRQ_XADC 39
+#define ZYNQ_IRQ_DVI 40
+#define ZYNQ_IRQ_SWDT 41
+#define ZYNQ_IRQ_TTC_0_0 42
+#define ZYNQ_IRQ_TTC_1_0 43
+#define ZYNQ_IRQ_TTC_2_0 44
+#define ZYNQ_IRQ_DMAC_ABORT 45
+#define ZYNQ_IRQ_DMAC_0 46
+#define ZYNQ_IRQ_DMAC_1 47
+#define ZYNQ_IRQ_DMAC_2 48
+#define ZYNQ_IRQ_DMAC_3 49
+#define ZYNQ_IRQ_SMC 50
+#define ZYNQ_IRQ_QUAD_SPI 51
+#define ZYNQ_IRQ_GPIO 52
+#define ZYNQ_IRQ_USB_0 53
+#define ZYNQ_IRQ_ETHERNET_0 54
+#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
+#define ZYNQ_IRQ_SDIO_0 56
+#define ZYNQ_IRQ_I2C_0 57
+#define ZYNQ_IRQ_SPI_0 58
+#define ZYNQ_IRQ_UART_0 59
+#define ZYNQ_IRQ_CAN_0 60
+#define ZYNQ_IRQ_FPGA_0 61
+#define ZYNQ_IRQ_FPGA_1 62
+#define ZYNQ_IRQ_FPGA_2 63
+#define ZYNQ_IRQ_FPGA_3 64
+#define ZYNQ_IRQ_FPGA_4 65
+#define ZYNQ_IRQ_FPGA_5 66
+#define ZYNQ_IRQ_FPGA_6 67
+#define ZYNQ_IRQ_FPGA_7 68
+#define ZYNQ_IRQ_TTC_0_1 69
+#define ZYNQ_IRQ_TTC_1_1 70
+#define ZYNQ_IRQ_TTC_2_1 71
+#define ZYNQ_IRQ_DMAC_4 72
+#define ZYNQ_IRQ_DMAC_5 73
+#define ZYNQ_IRQ_DMAC_6 74
+#define ZYNQ_IRQ_DMAC_7 75
+#define ZYNQ_IRQ_USB_1 76
+#define ZYNQ_IRQ_ETHERNET_1 77
+#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
+#define ZYNQ_IRQ_SDIO_1 79
+#define ZYNQ_IRQ_I2C_1 80
+#define ZYNQ_IRQ_SPI_1 81
+#define ZYNQ_IRQ_UART_1 82
+#define ZYNQ_IRQ_CAN_1 83
+#define ZYNQ_IRQ_FPGA_8 84
+#define ZYNQ_IRQ_FPGA_9 85
+#define ZYNQ_IRQ_FPGA_10 86
+#define ZYNQ_IRQ_FPGA_11 87
+#define ZYNQ_IRQ_FPGA_12 88
+#define ZYNQ_IRQ_FPGA_13 89
+#define ZYNQ_IRQ_FPGA_14 90
+#define ZYNQ_IRQ_FPGA_15 91
+#define ZYNQ_IRQ_PARITY 92
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 92
+
+#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
+
+#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h
new file mode 100644
index 0000000000..96ab469033
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/tm27.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <bsp/arm-gic-tm27.h>
+
+#endif /* __tm27_h */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h
new file mode 100644
index 0000000000..07be4ce5c4
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart-regs.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
+#define LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+	uint32_t control;
+#define ZYNQ_UART_CONTROL_STPBRK BSP_BIT32(8)
+#define ZYNQ_UART_CONTROL_STTBRK BSP_BIT32(7)
+#define ZYNQ_UART_CONTROL_RSTTO BSP_BIT32(6)
+#define ZYNQ_UART_CONTROL_TXDIS BSP_BIT32(5)
+#define ZYNQ_UART_CONTROL_TXEN BSP_BIT32(4)
+#define ZYNQ_UART_CONTROL_RXDIS BSP_BIT32(3)
+#define ZYNQ_UART_CONTROL_RXEN BSP_BIT32(2)
+#define ZYNQ_UART_CONTROL_TXRES BSP_BIT32(1)
+#define ZYNQ_UART_CONTROL_RXRES BSP_BIT32(0)
+	uint32_t mode;
+#define ZYNQ_UART_MODE_CHMODE(val) BSP_FLD32(val, 8, 9)
+#define ZYNQ_UART_MODE_CHMODE_GET(reg) BSP_FLD32GET(reg, 8, 9)
+#define ZYNQ_UART_MODE_CHMODE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
+#define ZYNQ_UART_MODE_CHMODE_NORMAL 0x00U
+#define ZYNQ_UART_MODE_CHMODE_AUTO_ECHO 0x01U
+#define ZYNQ_UART_MODE_CHMODE_LOCAL_LOOPBACK 0x02U
+#define ZYNQ_UART_MODE_CHMODE_REMOTE_LOOPBACK 0x03U
+#define ZYNQ_UART_MODE_NBSTOP(val) BSP_FLD32(val, 6, 7)
+#define ZYNQ_UART_MODE_NBSTOP_GET(reg) BSP_FLD32GET(reg, 6, 7)
+#define ZYNQ_UART_MODE_NBSTOP_SET(reg, val) BSP_FLD32SET(reg, val, 6, 7)
+#define ZYNQ_UART_MODE_NBSTOP_STOP_1 0x00U
+#define ZYNQ_UART_MODE_NBSTOP_STOP_1_5 0x01U
+#define ZYNQ_UART_MODE_NBSTOP_STOP_2 0x02U
+#define ZYNQ_UART_MODE_PAR(val) BSP_FLD32(val, 3, 5)
+#define ZYNQ_UART_MODE_PAR_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define ZYNQ_UART_MODE_PAR_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define ZYNQ_UART_MODE_PAR_EVEN 0x00U
+#define ZYNQ_UART_MODE_PAR_ODD 0x01U
+#define ZYNQ_UART_MODE_PAR_SPACE 0x02U
+#define ZYNQ_UART_MODE_PAR_MARK 0x03U
+#define ZYNQ_UART_MODE_PAR_NONE 0x04U
+#define ZYNQ_UART_MODE_CHRL(val) BSP_FLD32(val, 1, 2)
+#define ZYNQ_UART_MODE_CHRL_GET(reg) BSP_FLD32GET(reg, 1, 2)
+#define ZYNQ_UART_MODE_CHRL_SET(reg, val) BSP_FLD32SET(reg, val, 1, 2)
+#define ZYNQ_UART_MODE_CHRL_8 0x00U
+#define ZYNQ_UART_MODE_CHRL_7 0x02U
+#define ZYNQ_UART_MODE_CHRL_6 0x03U
+#define ZYNQ_UART_MODE_CLKS BSP_BIT32(0)
+	uint32_t irq_en;
+	uint32_t irq_dis;
+	uint32_t irq_mask;
+	uint32_t irq_sts;
+#define ZYNQ_UART_TOVR BSP_BIT32(12)
+#define ZYNQ_UART_TNFUL BSP_BIT32(11)
+#define ZYNQ_UART_TTRIG BSP_BIT32(10)
+#define ZYNQ_UART_DMSI BSP_BIT32(9)
+#define ZYNQ_UART_TIMEOUT BSP_BIT32(8)
+#define ZYNQ_UART_PARE BSP_BIT32(7)
+#define ZYNQ_UART_FRAME BSP_BIT32(6)
+#define ZYNQ_UART_ROVR BSP_BIT32(5)
+#define ZYNQ_UART_TFUL BSP_BIT32(4)
+#define ZYNQ_UART_TEMPTY BSP_BIT32(3)
+#define ZYNQ_UART_RFUL BSP_BIT32(2)
+#define ZYNQ_UART_REMPTY BSP_BIT32(1)
+#define ZYNQ_UART_RTRIG BSP_BIT32(0)
+	uint32_t baud_rate_gen;
+#define ZYNQ_UART_BAUD_RATE_GEN_CD(val) BSP_FLD32(val, 0, 15)
+#define ZYNQ_UART_BAUD_RATE_GEN_CD_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define ZYNQ_UART_BAUD_RATE_GEN_CD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+	uint32_t rx_timeout;
+#define ZYNQ_UART_RX_TIMEOUT_RTO(val) BSP_FLD32(val, 0, 7)
+#define ZYNQ_UART_RX_TIMEOUT_RTO_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define ZYNQ_UART_RX_TIMEOUT_RTO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+	uint32_t rx_fifo_trg_lvl;
+#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(val) BSP_FLD32(val, 0, 5)
+#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+	uint32_t modem_ctrl;
+#define ZYNQ_UART_MODEM_CTRL_FCM BSP_BIT32(5)
+#define ZYNQ_UART_MODEM_CTRL_RTS BSP_BIT32(1)
+#define ZYNQ_UART_MODEM_CTRL_DTR BSP_BIT32(0)
+	uint32_t modem_sts;
+#define ZYNQ_UART_MODEM_STS_FCMS BSP_BIT32(8)
+#define ZYNQ_UART_MODEM_STS_DCD BSP_BIT32(7)
+#define ZYNQ_UART_MODEM_STS_RI BSP_BIT32(6)
+#define ZYNQ_UART_MODEM_STS_DSR BSP_BIT32(5)
+#define ZYNQ_UART_MODEM_STS_CTS BSP_BIT32(4)
+#define ZYNQ_UART_MODEM_STS_DDCD BSP_BIT32(3)
+#define ZYNQ_UART_MODEM_STS_TERI BSP_BIT32(2)
+#define ZYNQ_UART_MODEM_STS_DDSR BSP_BIT32(1)
+#define ZYNQ_UART_MODEM_STS_DCTS BSP_BIT32(0)
+	uint32_t channel_sts;
+#define ZYNQ_UART_CHANNEL_STS_TNFUL BSP_BIT32(14)
+#define ZYNQ_UART_CHANNEL_STS_TTRIG BSP_BIT32(13)
+#define ZYNQ_UART_CHANNEL_STS_FDELT BSP_BIT32(12)
+#define ZYNQ_UART_CHANNEL_STS_TACTIVE BSP_BIT32(11)
+#define ZYNQ_UART_CHANNEL_STS_RACTIVE BSP_BIT32(10)
+#define ZYNQ_UART_CHANNEL_STS_TFUL BSP_BIT32(4)
+#define ZYNQ_UART_CHANNEL_STS_TEMPTY BSP_BIT32(3)
+#define ZYNQ_UART_CHANNEL_STS_RFUL BSP_BIT32(2)
+#define ZYNQ_UART_CHANNEL_STS_REMPTY BSP_BIT32(1)
+#define ZYNQ_UART_CHANNEL_STS_RTRIG BSP_BIT32(0)
+	uint32_t tx_rx_fifo;
+#define ZYNQ_UART_TX_RX_FIFO_FIFO(val) BSP_FLD32(val, 0, 7)
+#define ZYNQ_UART_TX_RX_FIFO_FIFO_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define ZYNQ_UART_TX_RX_FIFO_FIFO_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+	uint32_t baud_rate_div;
+#define ZYNQ_UART_BAUD_RATE_DIV_BDIV(val) BSP_FLD32(val, 0, 7)
+#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define ZYNQ_UART_BAUD_RATE_DIV_BDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+	uint32_t flow_delay;
+#define ZYNQ_UART_FLOW_DELAY_FDEL(val) BSP_FLD32(val, 0, 5)
+#define ZYNQ_UART_FLOW_DELAY_FDEL_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define ZYNQ_UART_FLOW_DELAY_FDEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+	uint32_t reserved_3c[2];
+	uint32_t tx_fifo_trg_lvl;
+#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG(val) BSP_FLD32(val, 0, 5)
+#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define ZYNQ_UART_TX_FIFO_TRG_LVL_TTRIG_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+} zynq_uart;
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_REGS_H */
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart.h b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart.h
new file mode 100644
index 0000000000..5eae1f479b
--- /dev/null
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/include/zynq-uart.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_UART_H
+#define LIBBSP_ARM_XILINX_ZYNQ_UART_H
+
+#include <libchip/serial.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+extern const console_fns zynq_uart_fns;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_UART_H */