diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-09-13 13:45:05 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-09-13 13:45:05 +0000 |
commit | 456456632d24d9a7ca068d9f8f93f3c50f93e705 (patch) | |
tree | b1bead1e51711bee065a6eb802f5af762059d141 /c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c | |
parent | 2000-09-13 Ralf Corsepius <corsepiu@faw.uni-ulm.de> (diff) | |
download | rtems-456456632d24d9a7ca068d9f8f93f3c50f93e705.tar.bz2 |
2000-09-13 Emmanuel Raguet <raguet@crf.canon.fr>
* vegaplus BSP submitted by Emmanuel Raguet <raguet@crf.canon.fr> and
Eric Valette <valette@crf.canon.fr>.
* vegaplus/bsp_specs, configure.in, console/Makefile.am,
include/Makefile.am, include/bsp.h, include/registers.h,
irq/Makefile.am, irq/bsp_irq_asm.S, irq/bsp_irq_init.c, irq/irq.c,
irq/irq.h, start/Makefile.am, start/start.S, startup/Makefile.am,
startup/bspstart.c, startup/exit.c, startup/linkcmds,
wrapup/Makefile.am: New files.
Diffstat (limited to 'c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c')
-rw-r--r-- | c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c b/c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c new file mode 100644 index 0000000000..08da02f9f5 --- /dev/null +++ b/c/src/lib/libbsp/arm/vegaplus/irq/bsp_irq_init.c @@ -0,0 +1,39 @@ +/* irq_init.c + * + * This file contains the implementation of rtems initialization + * related to interrupt handling. + * + * CopyRight (C) 2000 Canon Research Centre France SA. + * Emmanuel Raguet, mailto:raguet@crf.canon.fr + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +#include <irq.h> +#include <bsp.h> +#include <registers.h> + + +void BSP_rtems_irq_mngt_init() { + + /* Initialize the vector table address in internal RAM */ + Regs[INTTAB] = VECTOR_TABLE; + + /* Initialize the GLOBAL INT CONTROL register */ + Regs[INTGCNTL] = 0x00; + + /* Mask all the interrupts */ + Regs[INTMASK] = 0xFFFF; + + /* Unmask the 2 arm interrupts IRQ and FIQ on the INT controller */ + Regs[INTMASKALL] = 0x0; + + /* Ack pending interrupt */ + while ( ( Regs[INTSTAT] & 0xF433 ) != 0 ) { + Regs[INTACK] = 0xFFFF; + Regs[INTEOI] = EOI; + } +} |