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author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-09-22 09:50:59 +0200 |
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committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 11:31:19 +0200 |
commit | 8671786934eab0d2894809014f99c005f2c8d22a (patch) | |
tree | 1f039a873ba5f1f05e7e9553a4d4d574e81ad7ac /c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c | |
parent | arm/tms570: define base addresses of all TMS570LS3137 SPI interfaces. (diff) | |
download | rtems-8671786934eab0d2894809014f99c005f2c8d22a.tar.bz2 |
arm/tms570: include hardware initialization and selftest based on Ti HalCoGen generated files.
The configuration is specific for TMS570LS3137 based HDK.
Pins configuration can be easily changed in
rtems/c/src/lib/libbsp/arm/tms570/hwinit/init_pinmux.c
file.
The list tms570_selftest_par_list in the file
rtems/c/src/lib/libbsp/arm/tms570/hwinit/bspstarthooks-hwinit.c
specifies peripherals which health status is examined
by parity self-test at BSP start-up. It can be easily
modified for other TMS570 family members variants same
as the selection of other tests in bspstarthooks-hwinit.c.
Diffstat (limited to 'c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c')
-rw-r--r-- | c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c | 62 |
1 files changed, 62 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c b/c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c new file mode 100644 index 0000000000..23989d2026 --- /dev/null +++ b/c/src/lib/libbsp/arm/tms570/hwinit/init_esm.c @@ -0,0 +1,62 @@ +/** + * @file init_esm.c + * + * @ingroup tms570 + * + * @brief Error signaling module initialization + */ + +#include <stdint.h> +#include <bsp/tms570.h> +#include "tms570_hwinit.h" + +/** + * @brief Error signaling module initialization (HCG:esmInit) + * + */ +void tms570_esm_init( void ) +{ + /** - Disable error pin channels */ + TMS570_ESM.DEPAPR1 = 0xFFFFFFFFU; + TMS570_ESM.IEPCR4 = 0xFFFFFFFFU; + + /** - Disable interrupts */ + TMS570_ESM.IECR1 = 0xFFFFFFFFU; + TMS570_ESM.IECR4 = 0xFFFFFFFFU; + + /** - Clear error status flags */ + TMS570_ESM.SR[0U] = 0xFFFFFFFFU; + TMS570_ESM.SR[1U] = 0xFFFFFFFFU; + TMS570_ESM.SSR2 = 0xFFFFFFFFU; + TMS570_ESM.SR[2U] = 0xFFFFFFFFU; + TMS570_ESM.SR4 = 0xFFFFFFFFU; + + /** - Setup LPC preload */ + TMS570_ESM.LTCPR = 16384U - 1U; + + /** - Reset error pin */ + if (TMS570_ESM.EPSR == 0U) { + TMS570_ESM.EKR = 0x00000005U; + } else { + TMS570_ESM.EKR = 0x00000000U; + } + + /** - Clear interrupt level */ + TMS570_ESM.ILCR1 = 0xFFFFFFFFU; + TMS570_ESM.ILCR4 = 0xFFFFFFFFU; + + /** - Set interrupt level */ + TMS570_ESM.ILSR1 = 0x00000000; + + TMS570_ESM.ILSR4 = 0x00000000; + + /** - Enable error pin channels */ + TMS570_ESM.EEPAPR1 = 0x00000000; + + TMS570_ESM.IEPSR4 = 0x00000000; + + /** - Enable interrupts */ + TMS570_ESM.IESR1 = 0x00000000; + + TMS570_ESM.IESR4 = 0x00000000; +} |