diff options
| author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
| commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
| tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /c/src/lib/libbsp/arm/stm32f4 | |
| parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
| download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 | |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'c/src/lib/libbsp/arm/stm32f4')
26 files changed, 9 insertions, 3395 deletions
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am index b2e4544314..98abdc3415 100644 --- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am +++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am @@ -4,66 +4,25 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp - ############################################################################### # Data # ############################################################################### -dist_project_lib_DATA = bsp_specs +dist_project_lib_DATA = startup/bsp_specs EXTRA_DIST += ../shared/start/start.S start.$(OBJEXT): ../shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -project_lib_DATA += startup/linkcmds - -EXTRA_DIST += startup/linkcmds.stm32f4 -EXTRA_DIST += startup/linkcmds.stm32f105rc +project_lib_DATA += linkcmds +dist_project_lib_DATA += startup/linkcmds.stm32f105rc +dist_project_lib_DATA += startup/linkcmds.stm32f4 ############################################################################### # Header # ############################################################################### -include_HEADERS = -include_HEADERS += include/tm27.h -include_HEADERS += include/bsp.h - -nodist_include_HEADERS = -nodist_include_HEADERS += include/bspopts.h - -nodist_include_bsp_HEADERS = -nodist_include_bsp_HEADERS += ../../shared/include/bootcard.h - -include_bsp_HEADERS = -include_bsp_HEADERS += ../../shared/include/utility.h -include_bsp_HEADERS += ../../shared/include/irq-generic.h -include_bsp_HEADERS += ../../shared/include/irq-info.h -include_bsp_HEADERS += ../../shared/include/stackalloc.h -include_bsp_HEADERS += ../shared/include/start.h -include_bsp_HEADERS += ../shared/armv7m/include/armv7m-irq.h -include_bsp_HEADERS += include/irq.h -include_bsp_HEADERS += include/usart.h -include_bsp_HEADERS += include/stm32f4.h -include_bsp_HEADERS += include/stm32f10xxx_gpio.h -include_bsp_HEADERS += include/stm32f10xxx_rcc.h -include_bsp_HEADERS += include/stm32f10xxx_exti.h -include_bsp_HEADERS += include/stm32f4xxxx_adc.h -include_bsp_HEADERS += include/stm32f4xxxx_exti.h -include_bsp_HEADERS += include/stm32f4xxxx_gpio.h -include_bsp_HEADERS += include/stm32f4xxxx_rcc.h -include_bsp_HEADERS += include/stm32f4xxxx_pwr.h -include_bsp_HEADERS += include/stm32f4xxxx_syscfg.h -include_bsp_HEADERS += include/stm32f4xxxx_tim.h -include_bsp_HEADERS += include/stm32f4xxxx_flash.h -include_bsp_HEADERS += include/stm32f4xxxx_otgfs.h -include_bsp_HEADERS += include/stm32_i2c.h -include_bsp_HEADERS += include/i2c.h -include_bsp_HEADERS += include/stm32_usart.h -include_bsp_HEADERS += include/io.h -include_bsp_HEADERS += include/rcc.h - ############################################################################### # LibBSP # ############################################################################### @@ -71,7 +30,7 @@ include_bsp_HEADERS += include/rcc.h noinst_LIBRARIES = libbsp.a libbsp_a_SOURCES = -libbsp_a_CPPFLAGS = +libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) libbsp_a_LIBADD = # Shared @@ -136,5 +95,5 @@ libbsp_a_CPPFLAGS += -I$(srcdir)/../../../libcpu/arm/shared/include DISTCLEANFILES = include/bspopts.h -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/arm/stm32f4/headers.am diff --git a/c/src/lib/libbsp/arm/stm32f4/configure.ac b/c/src/lib/libbsp/arm/stm32f4/configure.ac index 4bf5871765..980a2acf79 100644 --- a/c/src/lib/libbsp/arm/stm32f4/configure.ac +++ b/c/src/lib/libbsp/arm/stm32f4/configure.ac @@ -2,6 +2,9 @@ AC_PREREQ([2.69]) AC_INIT([rtems-c-src-lib-libbsp-arm-stm32f4],[_RTEMS_VERSION],[https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/stm32f4.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) @@ -68,7 +71,6 @@ RTEMS_BSPOPTS_SET([STM32F4_ENABLE_I2C2],[*],[]) RTEMS_BSPOPTS_HELP([STM32F4_ENABLE_I2C2],[enable I2C 2]) RTEMS_BSP_CLEANUP_OPTIONS -RTEMS_BSP_LINKCMDS AC_CONFIG_FILES([Makefile]) AC_OUTPUT diff --git a/c/src/lib/libbsp/arm/stm32f4/include/bsp.h b/c/src/lib/libbsp/arm/stm32f4/include/bsp.h deleted file mode 100644 index 50052bc810..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/bsp.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * @file - * @ingroup arm_stm34f4 - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/** - * @defgroup arm_stm32f4 STM32F4 Support - * @ingroup bsp_arm - * @brief STM32f4 Support Package - * @{ - */ - -#ifndef LIBBSP_ARM_STM32F4_BSP_H -#define LIBBSP_ARM_STM32F4_BSP_H - -#include <bspopts.h> -#include <bsp/default-initial-extension.h> - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define BSP_FEATURE_IRQ_EXTENSION - -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT (13 << 4) - -#define BSP_ARMV7M_SYSTICK_PRIORITY (14 << 4) - -#define BSP_ARMV7M_SYSTICK_FREQUENCY STM32F4_HCLK - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_BSP_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/i2c.h b/c/src/lib/libbsp/arm/stm32f4/include/i2c.h deleted file mode 100644 index fa18b1f92f..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/i2c.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file - * @ingroup stm32f4_i2c I2C Support - * @brief I2C-module. - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -/* The I2C-module can not run with libi2c. The reason for this is, that libi2c - * needs a possibility to generate a stop condition separately. This controller - * wants to generate the condition automatically when sending or receiving data. - */ - -#ifndef LIBBSP_ARM_STM32F4_I2C_H -#define LIBBSP_ARM_STM32F4_I2C_H - -#include <rtems.h> - -#include <bsp/io.h> -#include <bsp/stm32f4.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup stm32f4_i2c I2C Support - * @ingroup arm_stm32f4 - * @brief I2C Module - * @{ - */ - -typedef struct { - /** - * @brief The address of the slave without the read write bit. - * A 7-Bit address should be placed in the bits [6..0] - */ - uint16_t addr; - /** @brief Read (true) or write (false) data */ - bool read; - /** @brief Size of data to read or write */ - size_t len; - /** @brief Buffer for data */ - uint8_t *buf; -} stm32f4_i2c_message; - -typedef struct { - volatile stm32f4_i2c *regs; - size_t index; - rtems_vector_number vector; - rtems_id mutex; - rtems_id task_id; - uint8_t *data; - uint8_t *last; - size_t len; - bool read; - uint8_t addr_with_rw; -} stm32f4_i2c_bus_entry; - -/** @brief Initialise the i2c module. */ -rtems_status_code stm32f4_i2c_init(stm32f4_i2c_bus_entry *e); - -/** @brief Process a i2c message */ -rtems_status_code stm32f4_i2c_process_message( - stm32f4_i2c_bus_entry *e, - stm32f4_i2c_message *msg -); - -/** @brief Set another baud rate than the default one */ -rtems_status_code stm32f4_i2c_set_bitrate( - stm32f4_i2c_bus_entry *e, - uint32_t br -); - -extern stm32f4_i2c_bus_entry *const stm32f4_i2c1; -extern stm32f4_i2c_bus_entry *const stm32f4_i2c2; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_I2C_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/io.h b/c/src/lib/libbsp/arm/stm32f4/include/io.h deleted file mode 100644 index b7f8669cba..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/io.h +++ /dev/null @@ -1,416 +0,0 @@ -/** - * @file - * @ingroup stm32f4_io - * @brief IO support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_IO_H -#define LIBBSP_ARM_STM32F4_IO_H - -#include <stdbool.h> -#include <stdint.h> -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup stm32f4_io IO Support - * @ingroup arm_stm32f4 - * @brief IO Support - * @{ - */ - -#define STM32F4_GPIO_PIN(port, index) ((((port) << 4) | (index)) & 0xff) - -#define STM32F4_GPIO_PORT_OF_PIN(pin) (((pin) >> 4) & 0xf) - -#define STM32F4_GPIO_INDEX_OF_PIN(pin) ((pin) & 0xf) - -#ifdef STM32F4_FAMILY_F4XXXX - -/** - * @name Family F4XXXX - * @{ - */ - -typedef enum { - STM32F4_GPIO_MODE_INPUT, - STM32F4_GPIO_MODE_OUTPUT, - STM32F4_GPIO_MODE_AF, - STM32F4_GPIO_MODE_ANALOG -} stm32f4_gpio_mode; - -typedef enum { - STM32F4_GPIO_OTYPE_PUSH_PULL, - STM32F4_GPIO_OTYPE_OPEN_DRAIN -} stm32f4_gpio_otype; - -typedef enum { - STM32F4_GPIO_OSPEED_2_MHZ, - STM32F4_GPIO_OSPEED_25_MHZ, - STM32F4_GPIO_OSPEED_50_MHZ, - STM32F4_GPIO_OSPEED_100_MHZ -} stm32f4_gpio_ospeed; - -typedef enum { - STM32F4_GPIO_NO_PULL, - STM32F4_GPIO_PULL_UP, - STM32F4_GPIO_PULL_DOWN -} stm32f4_gpio_pull; - -typedef enum { - STM32F4_GPIO_AF_SYSTEM = 0, - STM32F4_GPIO_AF_TIM1 = 1, - STM32F4_GPIO_AF_TIM2 = 1, - STM32F4_GPIO_AF_TIM3 = 2, - STM32F4_GPIO_AF_TIM4 = 2, - STM32F4_GPIO_AF_TIM5 = 2, - STM32F4_GPIO_AF_TIM8 = 3, - STM32F4_GPIO_AF_TIM9 = 3, - STM32F4_GPIO_AF_TIM10 = 3, - STM32F4_GPIO_AF_TIM11 = 3, - STM32F4_GPIO_AF_I2C1 = 4, - STM32F4_GPIO_AF_I2C2 = 4, - STM32F4_GPIO_AF_I2C3 = 4, - STM32F4_GPIO_AF_SPI1 = 5, - STM32F4_GPIO_AF_SPI2 = 5, - STM32F4_GPIO_AF_SPI3 = 6, - STM32F4_GPIO_AF_USART1 = 7, - STM32F4_GPIO_AF_USART2 = 7, - STM32F4_GPIO_AF_USART3 = 7, - STM32F4_GPIO_AF_UART4 = 8, - STM32F4_GPIO_AF_UART5 = 8, - STM32F4_GPIO_AF_USART6 = 8, - STM32F4_GPIO_AF_CAN1 = 9, - STM32F4_GPIO_AF_CAN2 = 9, - STM32F4_GPIO_AF_TIM12 = 9, - STM32F4_GPIO_AF_TIM13 = 9, - STM32F4_GPIO_AF_TIM14 = 9, - STM32F4_GPIO_AF_OTG_FS = 10, - STM32F4_GPIO_AF_OTG_HS = 10, - STM32F4_GPIO_AF_ETH = 11, - STM32F4_GPIO_AF_FSMC = 12, - STM32F4_GPIO_AF_OTG_HS_FS = 12, - STM32F4_GPIO_AF_SDIO = 12, - STM32F4_GPIO_AF_DCMI = 13, - STM32F4_GPIO_AF_EVENTOUT = 15 -} stm32f4_gpio_af; - -typedef union { - struct { - uint32_t pin_first : 8; - uint32_t pin_last : 8; - uint32_t mode : 2; - uint32_t otype : 1; - uint32_t ospeed : 2; - uint32_t pupd : 2; - uint32_t output : 1; - uint32_t af : 4; - uint32_t reserved : 4; - } fields; - - uint32_t value; -} stm32f4_gpio_config; - -#define STM32F4_GPIO_CONFIG_TERMINAL \ - { { 0xff, 0xff, 0x3, 0x1, 0x3, 0x3, 0x1, 0xf, 0xf } } - -/** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ -#ifdef STM32F4_FAMILY_F10XXX - -/** - * @name Family F10XXX - * @{ - */ - -typedef enum { - STM32F4_GPIO_MODE_INPUT, - STM32F4_GPIO_MODE_OUTPUT_10MHz, - STM32F4_GPIO_MODE_OUTPUT_2MHz, - STM32F4_GPIO_MODE_OUTPUT_50MHz -} stm32f4_gpio_mode; - -typedef enum { - STM32F4_GPIO_CNF_IN_ANALOG = 0, - STM32F4_GPIO_CNF_IN_FLOATING = 1, - STM32F4_GPIO_CNF_IN_PULL_UPDOWN = 2, - - STM32F4_GPIO_CNF_OUT_GPIO_PP = 0, - STM32F4_GPIO_CNF_OUT_GPIO_OD = 1, - STM32F4_GPIO_CNF_OUT_AF_PP = 2, - STM32F4_GPIO_CNF_OUT_AF_OD = 3, -} stm32f4_gpio_cnf; - -typedef enum { - STM32F4_GPIO_REMAP_DONT_CHANGE, - STM32F4_GPIO_REMAP_SPI1_0, - STM32F4_GPIO_REMAP_SPI1_1, - STM32F4_GPIO_REMAP_I2C1_0, - STM32F4_GPIO_REMAP_I2C1_1, - STM32F4_GPIO_REMAP_USART1_0, - STM32F4_GPIO_REMAP_USART1_1, - STM32F4_GPIO_REMAP_USART2_0, - STM32F4_GPIO_REMAP_USART2_1, - STM32F4_GPIO_REMAP_USART3_0, - STM32F4_GPIO_REMAP_USART3_1, - STM32F4_GPIO_REMAP_USART3_3, - STM32F4_GPIO_REMAP_TIM1_0, - STM32F4_GPIO_REMAP_TIM1_1, - STM32F4_GPIO_REMAP_TIM1_3, - STM32F4_GPIO_REMAP_TIM2_0, - STM32F4_GPIO_REMAP_TIM2_1, - STM32F4_GPIO_REMAP_TIM2_2, - STM32F4_GPIO_REMAP_TIM2_3, - STM32F4_GPIO_REMAP_TIM3_0, - STM32F4_GPIO_REMAP_TIM3_2, - STM32F4_GPIO_REMAP_TIM3_3, - STM32F4_GPIO_REMAP_TIM4_0, - STM32F4_GPIO_REMAP_TIM4_1, - STM32F4_GPIO_REMAP_CAN1_0, - STM32F4_GPIO_REMAP_CAN1_2, - STM32F4_GPIO_REMAP_CAN1_3, - STM32F4_GPIO_REMAP_PD01_0, - STM32F4_GPIO_REMAP_PD01_1, - STM32F4_GPIO_REMAP_TIM5CH4_0, - STM32F4_GPIO_REMAP_TIM5CH4_1, - STM32F4_GPIO_REMAP_ADC1_ETRGINJ_0, - STM32F4_GPIO_REMAP_ADC1_ETRGINJ_1, - STM32F4_GPIO_REMAP_ADC1_ETRGREG_0, - STM32F4_GPIO_REMAP_ADC1_ETRGREG_1, - STM32F4_GPIO_REMAP_ADC2_ETRGINJ_0, - STM32F4_GPIO_REMAP_ADC2_ETRGINJ_1, - STM32F4_GPIO_REMAP_ADC2_ETRGREG_0, - STM32F4_GPIO_REMAP_ADC2_ETRGREG_1, - STM32F4_GPIO_REMAP_ETH_0, - STM32F4_GPIO_REMAP_ETH_1, - STM32F4_GPIO_REMAP_CAN2_0, - STM32F4_GPIO_REMAP_CAN2_1, - STM32F4_GPIO_REMAP_MII_RMII_0, - STM32F4_GPIO_REMAP_MII_RMII_1, - STM32F4_GPIO_REMAP_SWJ_0, - STM32F4_GPIO_REMAP_SWJ_1, - STM32F4_GPIO_REMAP_SWJ_2, - STM32F4_GPIO_REMAP_SWJ_4, - STM32F4_GPIO_REMAP_SPI3_0, - STM32F4_GPIO_REMAP_SPI3_1, - STM32F4_GPIO_REMAP_TIM2ITR1_0, - STM32F4_GPIO_REMAP_TIM2ITR1_1, - STM32F4_GPIO_REMAP_PTP_PPS_0, - STM32F4_GPIO_REMAP_PTP_PPS_1, - STM32F4_GPIO_REMAP_TIM15_0, - STM32F4_GPIO_REMAP_TIM15_1, - STM32F4_GPIO_REMAP_TIM16_0, - STM32F4_GPIO_REMAP_TIM16_1, - STM32F4_GPIO_REMAP_TIM17_0, - STM32F4_GPIO_REMAP_TIM17_1, - STM32F4_GPIO_REMAP_CEC_0, - STM32F4_GPIO_REMAP_CEC_1, - STM32F4_GPIO_REMAP_TIM1_DMA_0, - STM32F4_GPIO_REMAP_TIM1_DMA_1, - STM32F4_GPIO_REMAP_TIM9_0, - STM32F4_GPIO_REMAP_TIM9_1, - STM32F4_GPIO_REMAP_TIM10_0, - STM32F4_GPIO_REMAP_TIM10_1, - STM32F4_GPIO_REMAP_TIM11_0, - STM32F4_GPIO_REMAP_TIM11_1, - STM32F4_GPIO_REMAP_TIM13_0, - STM32F4_GPIO_REMAP_TIM13_1, - STM32F4_GPIO_REMAP_TIM14_0, - STM32F4_GPIO_REMAP_TIM14_1, - STM32F4_GPIO_REMAP_FSMC_0, - STM32F4_GPIO_REMAP_FSMC_1, - STM32F4_GPIO_REMAP_TIM67_DAC_DMA_0, - STM32F4_GPIO_REMAP_TIM67_DAC_DMA_1, - STM32F4_GPIO_REMAP_TIM12_0, - STM32F4_GPIO_REMAP_TIM12_1, - STM32F4_GPIO_REMAP_MISC_0, - STM32F4_GPIO_REMAP_MISC_1, -} stm32f4_gpio_remap; - -typedef union { - struct { - uint32_t pin_first : 8; - uint32_t pin_last : 8; - uint32_t mode : 2; - uint32_t cnf : 2; - uint32_t output : 1; - uint32_t remap : 8; - uint32_t reserved : 3; - } fields; - - uint32_t value; -} stm32f4_gpio_config; - -#define STM32F4_GPIO_CONFIG_TERMINAL \ - { { 0xff, 0xff, 0x3, 0x3, 0x1, 0xff, 0x7 } } - -/** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ - -extern const stm32f4_gpio_config stm32f4_start_config_gpio []; - -void stm32f4_gpio_set_clock(int pin, bool set); - -void stm32f4_gpio_set_config(const stm32f4_gpio_config *config); - -/** - * @brief Sets the GPIO configuration of an array terminated by - * STM32F4_GPIO_CONFIG_TERMINAL. - */ -void stm32f4_gpio_set_config_array(const stm32f4_gpio_config *configs); - -void stm32f4_gpio_set_output(int pin, bool set); - -bool stm32f4_gpio_get_input(int pin); - -#ifdef STM32F4_FAMILY_F4XXXX - -/** - * @name Family F4XXXX - * @{ - */ - -#define STM32F4_PIN_USART(port, idx, altfunc) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_AF, \ - .otype = STM32F4_GPIO_OTYPE_PUSH_PULL, \ - .ospeed = STM32F4_GPIO_OSPEED_2_MHZ, \ - .pupd = STM32F4_GPIO_PULL_UP, \ - .af = altfunc \ - } \ - } - -#define STM32F4_PIN_USART1_TX_PA9 STM32F4_PIN_USART(0, 9, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_TX_PB6 STM32F4_PIN_USART(1, 6, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_RX_PA10 STM32F4_PIN_USART(0, 10, STM32F4_GPIO_AF_USART1) -#define STM32F4_PIN_USART1_RX_PB7 STM32F4_PIN_USART(1, 7, STM32F4_GPIO_AF_USART1) - -#define STM32F4_PIN_USART2_TX_PA2 STM32F4_PIN_USART(0, 2, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_TX_PD5 STM32F4_PIN_USART(3, 5, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_RX_PA3 STM32F4_PIN_USART(0, 3, STM32F4_GPIO_AF_USART2) -#define STM32F4_PIN_USART2_RX_PD6 STM32F4_PIN_USART(3, 6, STM32F4_GPIO_AF_USART2) - -#define STM32F4_PIN_USART3_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_TX_PD8 STM32F4_PIN_USART(3, 8, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_USART3) -#define STM32F4_PIN_USART3_RX_PD9 STM32F4_PIN_USART(3, 9, STM32F4_GPIO_AF_USART3) - -#define STM32F4_PIN_UART4_TX_PA0 STM32F4_PIN_USART(0, 0, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_TX_PC10 STM32F4_PIN_USART(2, 10, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_RX_PA1 STM32F4_PIN_USART(0, 1, STM32F4_GPIO_AF_UART4) -#define STM32F4_PIN_UART4_RX_PC11 STM32F4_PIN_USART(2, 11, STM32F4_GPIO_AF_UART4) - -#define STM32F4_PIN_UART5_TX_PC12 STM32F4_PIN_USART(2, 12, STM32F4_GPIO_AF_UART5) -#define STM32F4_PIN_UART5_RX_PD2 STM32F4_PIN_USART(3, 2, STM32F4_GPIO_AF_UART5) - -#define STM32F4_PIN_USART6_TX_PC6 STM32F4_PIN_USART(2, 6, STM32F4_GPIO_AF_USART6) -#define STM32F4_PIN_USART6_RX_PC7 STM32F4_PIN_USART(2, 7, STM32F4_GPIO_AF_USART6) - -/** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ -#ifdef STM32F4_FAMILY_F10XXX - -/** - * @name Family F10XXX - * @{ - */ - -#define STM32F4_PIN_USART_TX(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ - .cnf = STM32F4_GPIO_CNF_OUT_AF_PP, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_USART_RX(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_INPUT, \ - .cnf = STM32F4_GPIO_CNF_IN_FLOATING, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_USART1_TX_MAP_0 STM32F4_PIN_USART_TX(0, 9, STM32F4_GPIO_REMAP_USART1_0) -#define STM32F4_PIN_USART1_RX_MAP_0 STM32F4_PIN_USART_RX(0, 10, STM32F4_GPIO_REMAP_USART1_0) -#define STM32F4_PIN_USART1_TX_MAP_1 STM32F4_PIN_USART_TX(1, 6, STM32F4_GPIO_REMAP_USART1_1) -#define STM32F4_PIN_USART1_RX_MAP_1 STM32F4_PIN_USART_RX(1, 7, STM32F4_GPIO_REMAP_USART1_1) - -#define STM32F4_PIN_USART2_TX_MAP_0 STM32F4_PIN_USART_TX(0, 2, STM32F4_GPIO_REMAP_USART2_0) -#define STM32F4_PIN_USART2_RX_MAP_0 STM32F4_PIN_USART_RX(0, 3, STM32F4_GPIO_REMAP_USART2_0) -#define STM32F4_PIN_USART2_TX_MAP_1 STM32F4_PIN_USART_TX(3, 5, STM32F4_GPIO_REMAP_USART2_1) -#define STM32F4_PIN_USART2_RX_MAP_1 STM32F4_PIN_USART_RX(3, 6, STM32F4_GPIO_REMAP_USART2_1) - -#define STM32F4_PIN_USART3_TX_MAP_0 STM32F4_PIN_USART_TX(1, 10, STM32F4_GPIO_REMAP_USART3_0) -#define STM32F4_PIN_USART3_RX_MAP_0 STM32F4_PIN_USART_RX(1, 11, STM32F4_GPIO_REMAP_USART3_0) -#define STM32F4_PIN_USART3_TX_MAP_1 STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_USART3_1) -#define STM32F4_PIN_USART3_RX_MAP_1 STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_USART3_1) -#define STM32F4_PIN_USART3_TX_MAP_3 STM32F4_PIN_USART_TX(3, 8, STM32F4_GPIO_REMAP_USART3_3) -#define STM32F4_PIN_USART3_RX_MAP_3 STM32F4_PIN_USART_RX(3, 9, STM32F4_GPIO_REMAP_USART3_3) - -#define STM32F4_PIN_UART4_TX STM32F4_PIN_USART_TX(2, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_UART4_RX STM32F4_PIN_USART_RX(2, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) - -#define STM32F4_PIN_UART5_TX STM32F4_PIN_USART_TX(2, 12, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_UART5_RX STM32F4_PIN_USART_RX(3, 2, STM32F4_GPIO_REMAP_DONT_CHANGE) - -#define STM32F4_PIN_I2C(port, idx, remapvalue) \ - { \ - { \ - .pin_first = STM32F4_GPIO_PIN(port, idx), \ - .pin_last = STM32F4_GPIO_PIN(port, idx), \ - .mode = STM32F4_GPIO_MODE_OUTPUT_2MHz, \ - .cnf = STM32F4_GPIO_CNF_OUT_AF_OD, \ - .output = 0, \ - .remap = remapvalue \ - } \ - } - -#define STM32F4_PIN_I2C1_SCL_MAP0 STM32F4_PIN_I2C(1, 6, STM32F4_GPIO_REMAP_I2C1_0) -#define STM32F4_PIN_I2C1_SDA_MAP0 STM32F4_PIN_I2C(1, 7, STM32F4_GPIO_REMAP_I2C1_0) -#define STM32F4_PIN_I2C1_SCL_MAP1 STM32F4_PIN_I2C(1, 8, STM32F4_GPIO_REMAP_I2C1_1) -#define STM32F4_PIN_I2C1_SDA_MAP1 STM32F4_PIN_I2C(1, 9, STM32F4_GPIO_REMAP_I2C1_1) - -#define STM32F4_PIN_I2C2_SCL STM32F4_PIN_I2C(1, 10, STM32F4_GPIO_REMAP_DONT_CHANGE) -#define STM32F4_PIN_I2C2_SDA STM32F4_PIN_I2C(1, 11, STM32F4_GPIO_REMAP_DONT_CHANGE) - -/** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_IO_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/irq.h b/c/src/lib/libbsp/arm/stm32f4/include/irq.h deleted file mode 100644 index 4771f521fe..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/irq.h +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file - * @ingroup stm32f4_interrupt - * @brief Interrupt definitions. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_IRQ_H -#define LIBBSP_ARM_STM32F4_IRQ_H - -#ifndef ASM - -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -/** - * @defgroup stm32f4_interrupt Interrupt Support - * @ingroup arm_stm32f4 - * @brief Interrupt Support - * @{ - */ - -#define STM32F4_IRQ_WWDG 0 -#define STM32F4_IRQ_PVD 1 -#define STM32F4_IRQ_TAMP_STAMP 2 -#define STM32F4_IRQ_RTC_WKUP 3 -#define STM32F4_IRQ_FLASH 4 -#define STM32F4_IRQ_RCC 5 -#define STM32F4_IRQ_EXTI0 6 -#define STM32F4_IRQ_EXTI1 7 -#define STM32F4_IRQ_EXTI2 8 -#define STM32F4_IRQ_EXTI3 9 -#define STM32F4_IRQ_EXTI4 10 -#define STM32F4_IRQ_DMA1_STREAM0 11 -#define STM32F4_IRQ_DMA1_STREAM1 12 -#define STM32F4_IRQ_DMA1_STREAM2 13 -#define STM32F4_IRQ_DMA1_STREAM3 14 -#define STM32F4_IRQ_DMA1_STREAM4 15 -#define STM32F4_IRQ_DMA1_STREAM5 16 -#define STM32F4_IRQ_DMA1_STREAM6 17 -#define STM32F4_IRQ_ADC 18 -#define STM32F4_IRQ_CAN1_TX 19 -#define STM32F4_IRQ_CAN1_RX0 20 -#define STM32F4_IRQ_CAN1_RX1 21 -#define STM32F4_IRQ_CAN1_SCE 22 -#define STM32F4_IRQ_EXTI9_5 23 -#define STM32F4_IRQ_TIM1_BRK_TIM9 24 -#define STM32F4_IRQ_TIM1_UP_TIM10 25 -#define STM32F4_IRQ_TIM1_TRG_COM_TIM11 26 -#define STM32F4_IRQ_TIM1_CC 27 -#define STM32F4_IRQ_TIM2 28 -#define STM32F4_IRQ_TIM3 29 -#define STM32F4_IRQ_TIM4 30 -#define STM32F4_IRQ_I2C1_EV 31 -#define STM32F4_IRQ_I2C1_ER 32 -#define STM32F4_IRQ_I2C2_EV 33 -#define STM32F4_IRQ_I2C2_ER 34 -#define STM32F4_IRQ_SPI1 35 -#define STM32F4_IRQ_SPI2 36 -#define STM32F4_IRQ_USART1 37 -#define STM32F4_IRQ_USART2 38 -#define STM32F4_IRQ_USART3 39 -#define STM32F4_IRQ_EXTI15_10 40 -#define STM32F4_IRQ_RTC_ALARM 41 -#define STM32F4_IRQ_OTG_FS_WKUP 42 -#define STM32F4_IRQ_TIM8_BRK_TIM12 43 -#define STM32F4_IRQ_TIM8_UP_TIM13 44 -#define STM32F4_IRQ_TIM8_TRG_COM_TIM14 45 -#define STM32F4_IRQ_TIM8_CC 46 -#define STM32F4_IRQ_DMA1_STREAM7 47 -#define STM32F4_IRQ_FSMC 48 -#define STM32F4_IRQ_SDIO 49 -#define STM32F4_IRQ_TIM5 50 -#define STM32F4_IRQ_SPI3 51 -#define STM32F4_IRQ_UART4 52 -#define STM32F4_IRQ_UART5 53 -#define STM32F4_IRQ_TIM6_DAC 54 -#define STM32F4_IRQ_TIM7 55 -#define STM32F4_IRQ_DMA2_STREAM0 56 -#define STM32F4_IRQ_DMA2_STREAM1 57 -#define STM32F4_IRQ_DMA2_STREAM2 58 -#define STM32F4_IRQ_DMA2_STREAM3 59 -#define STM32F4_IRQ_DMA2_STREAM4 60 -#define STM32F4_IRQ_ETH 61 -#define STM32F4_IRQ_ETH_WKUP 62 -#define STM32F4_IRQ_CAN2_TX 63 -#define STM32F4_IRQ_CAN2_RX0 64 -#define STM32F4_IRQ_CAN2_RX1 65 -#define STM32F4_IRQ_CAN2_SCE 66 -#define STM32F4_IRQ_OTG_FS 67 -#define STM32F4_IRQ_DMA2_STREAM5 68 -#define STM32F4_IRQ_DMA2_STREAM6 69 -#define STM32F4_IRQ_DMA2_STREAM7 70 -#define STM32F4_IRQ_USART6 71 -#define STM32F4_IRQ_I2C3_EV 72 -#define STM32F4_IRQ_I2C3_ER 73 -#define STM32F4_IRQ_OTG_HS_EP1_OUT 74 -#define STM32F4_IRQ_OTG_HS_EP1_IN 75 -#define STM32F4_IRQ_OTG_HS_WKUP 76 -#define STM32F4_IRQ_OTG_HS 77 -#define STM32F4_IRQ_DCMI 78 -#define STM32F4_IRQ_CRYP 79 -#define STM32F4_IRQ_HASH_RNG 80 -#define STM32F4_IRQ_FPU 81 - -#define STM32F4_IRQ_PRIORITY_VALUE_MIN 0 -#define STM32F4_IRQ_PRIORITY_VALUE_MAX 15 -#define STM32F4_IRQ_PRIORITY_COUNT (STM32F4_IRQ_PRIORITY_VALUE_MAX + 1) -#define STM32F4_IRQ_PRIORITY_HIGHEST STM32F4_IRQ_PRIORITY_VALUE_MIN -#define STM32F4_IRQ_PRIORITY_LOWEST STM32F4_IRQ_PRIORITY_VALUE_MAX - -#define BSP_INTERRUPT_VECTOR_MIN 0 -#define BSP_INTERRUPT_VECTOR_MAX 81 - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h deleted file mode 100644 index f1bd7d173c..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h +++ /dev/null @@ -1,196 +0,0 @@ -/** - * @file - * @ingroup stm32f4_rcc - * @brief RCC support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_RCC_H -#define LIBBSP_ARM_STM32F4_RCC_H - -#include <stdbool.h> -#include <bspopts.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup stm32f4_rcc RCC Support - * @ingroup arm_stm32f4 - * @brief RCC Support - * @{ - */ - -#define STM32F4_RCC_INDEX(reg, idx) (((reg) << 5) | (idx)) - -typedef enum { -#ifdef STM32F4_FAMILY_F4XXXX - - /** - * @name Family F4XXXX - * @{ - */ - - STM32F4_RCC_OTGHS = STM32F4_RCC_INDEX(0, 29), - STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 25), - STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 22), - STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 21), - STM32F4_RCC_CRC = STM32F4_RCC_INDEX(0, 12), - STM32F4_RCC_GPIOI = STM32F4_RCC_INDEX(0, 8), - STM32F4_RCC_GPIOH = STM32F4_RCC_INDEX(0, 7), - STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(0, 6), - STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(0, 5), - STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(0, 4), - STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(0, 3), - STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(0, 2), - STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(0, 1), - STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(0, 0), - - STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(1, 7), - STM32F4_RCC_RNG = STM32F4_RCC_INDEX(1, 6), - STM32F4_RCC_HASH = STM32F4_RCC_INDEX(1, 5), - STM32F4_RCC_CRYP = STM32F4_RCC_INDEX(1, 4), - STM32F4_RCC_DCMI = STM32F4_RCC_INDEX(1, 0), - - STM32F4_RCC_FSMCR = STM32F4_RCC_INDEX(2, 0), - - STM32F4_RCC_DAC = STM32F4_RCC_INDEX(4, 29), - STM32F4_RCC_PWR = STM32F4_RCC_INDEX(4, 28), - STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(4, 26), - STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(4, 25), - STM32F4_RCC_I2C3 = STM32F4_RCC_INDEX(4, 23), - STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(4, 22), - STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(4, 21), - STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(4, 20), - STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(4, 19), - STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(4, 18), - STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(4, 17), - STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(4, 15), - STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(4, 14), - STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(4, 11), - STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(4, 8), - STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(4, 7), - STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(4, 6), - STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(4, 5), - STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(4, 4), - STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(4, 3), - STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(4, 2), - STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(4, 1), - STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(4, 0), - - STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(5, 18), - STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(5, 17), - STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(5, 16), - STM32F4_RCC_SYSCFG = STM32F4_RCC_INDEX(5, 14), - STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(5, 12), - STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(5, 11), - STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(5, 10), - STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(5, 9), - STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(5, 8), - STM32F4_RCC_USART6 = STM32F4_RCC_INDEX(5, 5), - STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(5, 4), - STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(5, 1), - STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(5, 0), - - /** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ -#ifdef STM32F4_FAMILY_F10XXX - - /** - * @name Family F10 - * @{ - */ - - STM32F4_RCC_DMA1 = STM32F4_RCC_INDEX(0, 0), - STM32F4_RCC_DMA2 = STM32F4_RCC_INDEX(0, 1), - STM32F4_RCC_SRAM = STM32F4_RCC_INDEX(0, 2), - STM32F4_RCC_FLITF = STM32F4_RCC_INDEX(0, 4), - STM32F4_RCC_CRCEN = STM32F4_RCC_INDEX(0, 6), - STM32F4_RCC_FSMC = STM32F4_RCC_INDEX(0, 8), - STM32F4_RCC_SDIO = STM32F4_RCC_INDEX(0, 10), - STM32F4_RCC_OTGFS = STM32F4_RCC_INDEX(0, 12), - STM32F4_RCC_ETHMAC = STM32F4_RCC_INDEX(0, 14), - STM32F4_RCC_ETHMACTX = STM32F4_RCC_INDEX(0, 15), - STM32F4_RCC_ETHMACRX = STM32F4_RCC_INDEX(0, 16), - - STM32F4_RCC_AFIO = STM32F4_RCC_INDEX(1, 0), - STM32F4_RCC_GPIOA = STM32F4_RCC_INDEX(1, 2), - STM32F4_RCC_GPIOB = STM32F4_RCC_INDEX(1, 3), - STM32F4_RCC_GPIOC = STM32F4_RCC_INDEX(1, 4), - STM32F4_RCC_GPIOD = STM32F4_RCC_INDEX(1, 5), - STM32F4_RCC_GPIOE = STM32F4_RCC_INDEX(1, 6), - STM32F4_RCC_GPIOF = STM32F4_RCC_INDEX(1, 7), - STM32F4_RCC_GPIOG = STM32F4_RCC_INDEX(1, 8), - STM32F4_RCC_ADC1 = STM32F4_RCC_INDEX(1, 9), - STM32F4_RCC_ADC2 = STM32F4_RCC_INDEX(1, 10), - STM32F4_RCC_TIM1 = STM32F4_RCC_INDEX(1, 11), - STM32F4_RCC_SPI1 = STM32F4_RCC_INDEX(1, 12), - STM32F4_RCC_TIM8 = STM32F4_RCC_INDEX(1, 13), - STM32F4_RCC_USART1 = STM32F4_RCC_INDEX(1, 14), - STM32F4_RCC_ADC3 = STM32F4_RCC_INDEX(1, 15), - STM32F4_RCC_TIM9 = STM32F4_RCC_INDEX(1, 19), - STM32F4_RCC_TIM10 = STM32F4_RCC_INDEX(1, 20), - STM32F4_RCC_TIM11 = STM32F4_RCC_INDEX(1, 21), - - STM32F4_RCC_TIM2 = STM32F4_RCC_INDEX(2, 0), - STM32F4_RCC_TIM3 = STM32F4_RCC_INDEX(2, 1), - STM32F4_RCC_TIM4 = STM32F4_RCC_INDEX(2, 2), - STM32F4_RCC_TIM5 = STM32F4_RCC_INDEX(2, 3), - STM32F4_RCC_TIM6 = STM32F4_RCC_INDEX(2, 4), - STM32F4_RCC_TIM7 = STM32F4_RCC_INDEX(2, 5), - STM32F4_RCC_TIM12 = STM32F4_RCC_INDEX(2, 6), - STM32F4_RCC_TIM13 = STM32F4_RCC_INDEX(2, 7), - STM32F4_RCC_TIM14 = STM32F4_RCC_INDEX(2, 8), - STM32F4_RCC_WWDG = STM32F4_RCC_INDEX(2, 11), - STM32F4_RCC_SPI2 = STM32F4_RCC_INDEX(2, 14), - STM32F4_RCC_SPI3 = STM32F4_RCC_INDEX(2, 15), - STM32F4_RCC_USART2 = STM32F4_RCC_INDEX(2, 17), - STM32F4_RCC_USART3 = STM32F4_RCC_INDEX(2, 18), - STM32F4_RCC_UART4 = STM32F4_RCC_INDEX(2, 19), - STM32F4_RCC_UART5 = STM32F4_RCC_INDEX(2, 20), - STM32F4_RCC_I2C1 = STM32F4_RCC_INDEX(2, 21), - STM32F4_RCC_I2C2 = STM32F4_RCC_INDEX(2, 22), - STM32F4_RCC_USB = STM32F4_RCC_INDEX(2, 23), - STM32F4_RCC_CAN1 = STM32F4_RCC_INDEX(2, 24), - STM32F4_RCC_CAN2 = STM32F4_RCC_INDEX(2, 25), - STM32F4_RCC_BKP = STM32F4_RCC_INDEX(2, 27), - STM32F4_RCC_PWR = STM32F4_RCC_INDEX(2, 28), - STM32F4_RCC_DAC = STM32F4_RCC_INDEX(2, 29), - - /** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ -} stm32f4_rcc_index; - -void stm32f4_rcc_reset(stm32f4_rcc_index index); - -void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set); - -void stm32f4_rcc_set_clock(stm32f4_rcc_index index, bool set); - -#ifdef STM32F4_FAMILY_F4XXXX -void stm32f4_rcc_set_low_power_clock(stm32f4_rcc_index index, bool set); -#endif /* STM32F4_FAMILY_F4XXXX */ - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_RCC_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32_i2c.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32_i2c.h deleted file mode 100644 index 21d9b34ed1..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32_i2c.h +++ /dev/null @@ -1,113 +0,0 @@ -/** - * @file - * @ingroup stm32_i2c - * @brief STM32 I2C support. - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32_I2C_H -#define LIBBSP_ARM_STM32F4_STM32_I2C_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32_i2c STM32 I2C Support - * @ingroup stm32f4_i2c - * @brief STM32 I2C Support - * @{ - */ - -typedef struct { - uint32_t cr1; -#define STM32F4_I2C_CR1_SWRST BSP_BIT32(15) -#define STM32F4_I2C_CR1_ALERT BSP_BIT32(13) -#define STM32F4_I2C_CR1_PEC BSP_BIT32(12) -#define STM32F4_I2C_CR1_POS BSP_BIT32(11) -#define STM32F4_I2C_CR1_ACK BSP_BIT32(10) -#define STM32F4_I2C_CR1_STOP BSP_BIT32(9) -#define STM32F4_I2C_CR1_START BSP_BIT32(8) -#define STM32F4_I2C_CR1_NOSTRETCH BSP_BIT32(7) -#define STM32F4_I2C_CR1_ENGC BSP_BIT32(6) -#define STM32F4_I2C_CR1_ENPEC BSP_BIT32(5) -#define STM32F4_I2C_CR1_ENARP BSP_BIT32(4) -#define STM32F4_I2C_CR1_SMBTYPE BSP_BIT32(3) -#define STM32F4_I2C_CR1_SMBUS BSP_BIT32(1) -#define STM32F4_I2C_CR1_PE BSP_BIT32(0) - uint32_t cr2; -#define STM32F4_I2C_CR2_LAST BSP_BIT32(12) -#define STM32F4_I2C_CR2_DMAEN BSP_BIT32(11) -#define STM32F4_I2C_CR2_ITBUFEN BSP_BIT32(10) -#define STM32F4_I2C_CR2_ITEVTEN BSP_BIT32(9) -#define STM32F4_I2C_CR2_ITERREN BSP_BIT32(8) -#define STM32F4_I2C_CR2_FREQ(val) BSP_FLD32(val, 0, 5) -#define STM32F4_I2C_CR2_FREQ_GET(reg) BSP_FLD32GET(reg, 0, 5) -#define STM32F4_I2C_CR2_FREQ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) - uint32_t oar1; -#define STM32F4_I2C_OAR1_ADDMODE BSP_BIT32(15) -#define STM32F4_I2C_OAR1_ADD(val) BSP_FLD32(val, 0, 9) -#define STM32F4_I2C_OAR1_ADD_GET(reg) BSP_FLD32GET(reg, 0, 9) -#define STM32F4_I2C_OAR1_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) - uint32_t oar2; -#define STM32F4_I2C_OAR2_ADD2(val) BSP_FLD32(val, 1, 7) -#define STM32F4_I2C_OAR2_ADD2_GET(reg) BSP_FLD32GET(reg, 1, 7) -#define STM32F4_I2C_OAR2_ADD2_SET(reg, val) BSP_FLD32SET(reg, val, 1, 7) -#define STM32F4_I2C_OAR2_ENDUAL BSP_BIT32(0) - uint32_t dr; -#define STM32F4_I2C_DR(val) BSP_FLD32(val, 0, 7) -#define STM32F4_I2C_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) -#define STM32F4_I2C_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) - uint32_t sr1; -#define STM32F4_I2C_SR1_SMBALERT BSP_BIT32(15) -#define STM32F4_I2C_SR1_TIMEOUT BSP_BIT32(14) -#define STM32F4_I2C_SR1_PECERR BSP_BIT32(12) -#define STM32F4_I2C_SR1_OVR BSP_BIT32(11) -#define STM32F4_I2C_SR1_AF BSP_BIT32(10) -#define STM32F4_I2C_SR1_ARLO BSP_BIT32(9) -#define STM32F4_I2C_SR1_BERR BSP_BIT32(8) -#define STM32F4_I2C_SR1_TxE BSP_BIT32(7) -#define STM32F4_I2C_SR1_RxNE BSP_BIT32(6) -#define STM32F4_I2C_SR1_STOPF BSP_BIT32(4) -#define STM32F4_I2C_SR1_ADD10 BSP_BIT32(3) -#define STM32F4_I2C_SR1_BTF BSP_BIT32(2) -#define STM32F4_I2C_SR1_ADDR BSP_BIT32(1) -#define STM32F4_I2C_SR1_SB BSP_BIT32(0) - uint32_t sr2; -#define STM32F4_I2C_SR2_PEC(val) BSP_FLD32(val, 8, 15) -#define STM32F4_I2C_SR2_PEC_GET(reg) BSP_FLD32GET(reg, 8, 15) -#define STM32F4_I2C_SR2_PEC_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) -#define STM32F4_I2C_SR2_DUALF BSP_BIT32(7) -#define STM32F4_I2C_SR2_SMBHOST BSP_BIT32(6) -#define STM32F4_I2C_SR2_SMBDEFAULT BSP_BIT32(5) -#define STM32F4_I2C_SR2_GENCALL BSP_BIT32(4) -#define STM32F4_I2C_SR2_TRA BSP_BIT32(2) -#define STM32F4_I2C_SR2_BUSY BSP_BIT32(1) -#define STM32F4_I2C_SR2_MSL BSP_BIT32(0) - uint32_t ccr; -#define STM32F4_I2C_CCR_FS BSP_BIT32(15) -#define STM32F4_I2C_CCR_DUTY BSP_BIT32(14) -#define STM32F4_I2C_CCR_CCR(val) BSP_FLD32(val, 0, 11) -#define STM32F4_I2C_CCR_CCR_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define STM32F4_I2C_CCR_CCR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) -#define STM32F4_I2C_CCR_CCR_MAX STM32F4_I2C_CCR_CCR_GET(BSP_MSK32(0, 11)) - uint32_t trise; -#define STM32F4_I2C_TRISE(val) BSP_FLD32(val, 0, 5) -#define STM32F4_I2C_TRISE_GET(reg) BSP_FLD32GET(reg, 0, 5) -#define STM32F4_I2C_TRISE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) -} stm32f4_i2c; - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_STM32_I2C_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h deleted file mode 100644 index c9c269533f..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32_usart.h +++ /dev/null @@ -1,110 +0,0 @@ -/** - * @file - * @ingroup stm32_usart - * @brief STM32 USART support - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32_USART_H -#define LIBBSP_ARM_STM32F4_STM32_USART_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32_usart STM32 USART Support - * @ingroup stm32f4_usart - * @brief STM32 USART Support - * @{ - */ - -typedef struct { - uint32_t sr; -#define STM32F4_USART_SR_CTS BSP_BIT32(9) -#define STM32F4_USART_SR_LBD BSP_BIT32(8) -#define STM32F4_USART_SR_TXE BSP_BIT32(7) -#define STM32F4_USART_SR_TC BSP_BIT32(6) -#define STM32F4_USART_SR_RXNE BSP_BIT32(5) -#define STM32F4_USART_SR_IDLE BSP_BIT32(4) -#define STM32F4_USART_SR_ORE BSP_BIT32(3) -#define STM32F4_USART_SR_NF BSP_BIT32(2) -#define STM32F4_USART_SR_FE BSP_BIT32(1) -#define STM32F4_USART_SR_PE BSP_BIT32(0) - uint32_t dr; -#define STM32F4_USART_DR(val) BSP_FLD32(val, 0, 7) -#define STM32F4_USART_DR_GET(reg) BSP_FLD32GET(reg, 0, 7) -#define STM32F4_USART_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) - uint32_t bbr; -#define STM32F4_USART_BBR_DIV_MANTISSA(val) BSP_FLD32(val, 4, 15) -#define STM32F4_USART_BBR_DIV_MANTISSA_GET(reg) BSP_FLD32GET(reg, 4, 15) -#define STM32F4_USART_BBR_DIV_MANTISSA_SET(reg, val) BSP_FLD32SET(reg, val, 4, 15) -#define STM32F4_USART_BBR_DIV_FRACTION(val) BSP_FLD32(val, 0, 3) -#define STM32F4_USART_BBR_DIV_FRACTION_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_USART_BBR_DIV_FRACTION_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) - uint32_t cr1; -#define STM32F4_USART_CR1_OVER8 BSP_BIT32(15) -#define STM32F4_USART_CR1_UE BSP_BIT32(13) -#define STM32F4_USART_CR1_M BSP_BIT32(12) -#define STM32F4_USART_CR1_WAKE BSP_BIT32(11) -#define STM32F4_USART_CR1_PCE BSP_BIT32(10) -#define STM32F4_USART_CR1_PS BSP_BIT32(9) -#define STM32F4_USART_CR1_PEIE BSP_BIT32(8) -#define STM32F4_USART_CR1_TXEIE BSP_BIT32(7) -#define STM32F4_USART_CR1_TCIE BSP_BIT32(6) -#define STM32F4_USART_CR1_RXNEIE BSP_BIT32(5) -#define STM32F4_USART_CR1_IDLEIE BSP_BIT32(4) -#define STM32F4_USART_CR1_TE BSP_BIT32(3) -#define STM32F4_USART_CR1_RE BSP_BIT32(2) -#define STM32F4_USART_CR1_RWU BSP_BIT32(1) -#define STM32F4_USART_CR1_SBK BSP_BIT32(0) - uint32_t cr2; -#define STM32F4_USART_CR2_LINEN BSP_BIT32(14) -#define STM32F4_USART_CR2_STOP(val) BSP_FLD32(val, 12, 13) -#define STM32F4_USART_CR2_STOP_GET(reg) BSP_FLD32GET(reg, 12, 13) -#define STM32F4_USART_CR2_STOP_SET(reg, val) BSP_FLD32SET(reg, val, 12, 13) -#define STM32F4_USART_CR2_CLKEN BSP_BIT32(11) -#define STM32F4_USART_CR2_CPOL BSP_BIT32(10) -#define STM32F4_USART_CR2_CPHA BSP_BIT32(9) -#define STM32F4_USART_CR2_LBCL BSP_BIT32(8) -#define STM32F4_USART_CR2_LBDIE BSP_BIT32(6) -#define STM32F4_USART_CR2_LBDL BSP_BIT32(5) -#define STM32F4_USART_CR2_ADD(val) BSP_FLD32(val, 0, 3) -#define STM32F4_USART_CR2_ADD_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_USART_CR2_ADD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) - uint32_t cr3; -#define STM32F4_USART_CR3_ONEBIT BSP_BIT32(11) -#define STM32F4_USART_CR3_CTSIE BSP_BIT32(10) -#define STM32F4_USART_CR3_CTSE BSP_BIT32(9) -#define STM32F4_USART_CR3_RTSE BSP_BIT32(8) -#define STM32F4_USART_CR3_DMAT BSP_BIT32(7) -#define STM32F4_USART_CR3_DMAR BSP_BIT32(6) -#define STM32F4_USART_CR3_SCEN BSP_BIT32(5) -#define STM32F4_USART_CR3_NACK BSP_BIT32(4) -#define STM32F4_USART_CR3_HDSEL BSP_BIT32(3) -#define STM32F4_USART_CR3_IRLP BSP_BIT32(2) -#define STM32F4_USART_CR3_IREN BSP_BIT32(1) -#define STM32F4_USART_CR3_EIE BSP_BIT32(0) - uint32_t gtpr; -#define STM32F4_USART_GTPR_GT(val) BSP_FLD32(val, 8, 15) -#define STM32F4_USART_GTPR_GT_GET(reg) BSP_FLD32GET(reg, 8, 15) -#define STM32F4_USART_GTPR_GT_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) -#define STM32F4_USART_GTPR_PSC(val) BSP_FLD32(val, 0, 7) -#define STM32F4_USART_GTPR_PSC_GET(reg) BSP_FLD32GET(reg, 0, 7) -#define STM32F4_USART_GTPR_PSC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) -} stm32f4_usart; - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_STM32_USART_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_exti.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_exti.h deleted file mode 100644 index ecb4bb900c..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_exti.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file - * @ingroup stm32f4_exti - * @brief STM32F10XXX EXTI support - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H -#define LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32f4_exti EXTI Support - * @ingroup arm_stm32f4 - * @brief STM32F10XXX EXTI Support - * @{ - */ - -typedef struct { - uint32_t imr; -#define STM32F4_EXTI_IMR(line) BSP_BIT32(line) - uint32_t emr; -#define STM32F4_EXTI_EMR(line) BSP_BIT32(line) - uint32_t rtsr; -#define STM32F4_EXTI_RTSR(line) BSP_BIT32(line) - uint32_t ftsr; -#define STM32F4_EXTI_FTSR(line) BSP_BIT32(line) - uint32_t swier; -#define STM32F4_EXTI_SWIER(line) BSP_BIT32(line) - uint32_t pr; -#define STM32F4_EXTI_PR(line) BSP_BIT32(line) -} stm32f4_exti; - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_EXTI_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h deleted file mode 100644 index ec7e675844..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_gpio.h +++ /dev/null @@ -1,51 +0,0 @@ -/** - * @file - * @ingroup stm32f4_gpio - * @brief STM32F10XXX GPIO support. - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H -#define LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32f4_gpio GPIO Support - * @ingroup stm32f4_io - * @brief GPIO Support - * @{ - */ - -typedef struct { - uint32_t cr[2]; - uint32_t idr; - uint32_t odr; - uint32_t bsrr; - uint32_t brr; - uint32_t lckr; -} stm32f4_gpio; - -typedef struct { - uint32_t evcr; - uint32_t mapr; - uint32_t exticr[4]; - uint32_t mapr2; -} stm32f4_afio; - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_GPIO_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h deleted file mode 100644 index c1c6629810..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f10xxx_rcc.h +++ /dev/null @@ -1,48 +0,0 @@ -/** - * @file - * @ingroup stm32f10xxx_rcc - * @brief STM32F10XXX RCC support. - */ - -/* - * Copyright (c) 2013 Christian Mauderer. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H -#define LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32f10xxx_rcc STM32F10XXX RCC Support - * @ingroup stm32f4_rcc - * @brief STM32F10XXX RCC Support - * @{ - */ - -typedef struct { - uint32_t cr; - uint32_t cfgr; - uint32_t cir; - uint32_t apbrstr [2]; - uint32_t ahbenr [1]; - uint32_t apbenr [2]; - uint32_t bdcr; - uint32_t csr; - uint32_t ahbstr; - uint32_t cfgr2; -} stm32f4_rcc; - -/** @} */ - -#endif /* LIBBSP_ARM_STM32F4_STM32F10XXX_RCC_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h deleted file mode 100644 index 154d4f6d7b..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h +++ /dev/null @@ -1,258 +0,0 @@ -/** - * @file - * @ingroup stm32f4_reg - * @brief Register definitions. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4_H -#define LIBBSP_ARM_STM32F4_STM32F4_H - -#include <bsp/utility.h> -#include <bspopts.h> - -#define STM32F4_BASE 0x00 - -#ifdef STM32F4_FAMILY_F4XXXX - -/** - * @defgroup stm32f4_reg Register Defintions - * @ingroup arm_stm32f4 - * @brief Register Definitions - * @{ - */ - -#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000) -#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000) -#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000) -#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000) - -/** - * @name STM32f4XXXX GPIO - * @{ - */ - -#include <bsp/stm32f4xxxx_gpio.h> -#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i)) - -/** @} */ - -/** - * @name STM32F4XXXX RCC - * @{ - */ - -#include <bsp/stm32f4xxxx_rcc.h> -#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800)) - -/** @} */ - -/** - * @name STM32F4XXXX FLASH - * @{ - */ - -#include <bsp/stm32f4xxxx_flash.h> -#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_BASE + 0x40023C00)) - -/** @} */ - -#include <bsp/stm32_i2c.h> - -/** - * @name STM32 I2C - * @{ - */ - -#define STM32F4_I2C3 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005C00)) -#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) -#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) - -/** @} */ - -/** - * @name STM32 USART - * @{ - */ - -#include <bsp/stm32_usart.h> -#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011000)) -#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) -#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) -#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) -#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) -#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400)) - -/** @} */ - -/** - * @name STM32f4XXXX PWR - * @{ - */ - -#include <bsp/stm32f4xxxx_pwr.h> -#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000)) - -/** @} */ - -/** - * @name STM32f4XXXX EXTI - * @{ - */ - -#include <bsp/stm32f4xxxx_exti.h> -#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00)) - -/** @} */ - -/** - * @name STM32f4XXXX SYSCFG - * @{ - */ - -#include <bsp/stm32f4xxxx_syscfg.h> -#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800)) - -/** @} */ - -/** - * @name STM32f4XXXX FLASH - * @{ - */ - -#include <bsp/stm32f4xxxx_flash.h> -#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00)) - -/** @} */ - -/** - * @name STM32f4XXXX TIM - * @{ - */ - -#include <bsp/stm32f4xxxx_tim.h> -#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000)) -#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000)) -#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400)) -#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800)) -#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00)) -#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000)) -#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400)) -#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400)) -#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000)) -#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400)) -#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800)) -#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800)) -#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00)) -#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000)) - -/** @} */ - -/** - * @name STM32f4XXXX ADC - * @{ - */ - -#include <bsp/stm32f4xxxx_adc.h> -#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000)) -#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100)) -#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200)) -#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300)) - -/** @} */ - -/** - * @name STM32f4XXXX OTGFS - * @{ - */ - -#include <bsp/stm32f4xxxx_otgfs.h> -#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000) -#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000)) -#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800)) -#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900)) -#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00)) -#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00)) - -#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE) - -/** @} */ - -#endif /* STM32F4_FAMILY_F4XXXX */ - -#ifdef STM32F4_FAMILY_F10XXX - -/** - * @name STM32F10 EXTI - * @{ - */ - -#include <bsp/stm32f10xxx_exti.h> -#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_BASE + 0x40010400)) - -/** @} */ - -/** - * @name STM32F10XXX GPIO - * @{ - */ - -#include <bsp/stm32f10xxx_gpio.h> -#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40010800 + i * 0x400)) -#define STM32F4_AFIO ((volatile stm32f4_afio *) (STM32F4_BASE + 0x40010000)) - -/** @} */ - -/** - * @name STM32F10XXX RCC - * @{ - */ - -#include <bsp/stm32f10xxx_rcc.h> -#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40021000)) - -/** @} */ - -/** - * @name STM32 I2C - * @{ - */ - -#include <bsp/stm32_i2c.h> -#define STM32F4_I2C2 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005800)) -#define STM32F4_I2C1 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005400)) - -/** @} */ - -/** - * @name STM32 USART - * @{ - */ - -#include <bsp/stm32_usart.h> -#define STM32F4_USART_1 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40013800)) -#define STM32F4_USART_2 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004400)) -#define STM32F4_USART_3 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004800)) -#define STM32F4_USART_4 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40004c00)) -#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000)) - -/** @} */ - -/** @} */ - -#endif /* STM32F4_FAMILY_F10XXX */ - -#endif /* LIBBSP_ARM_STM32F4_STM32F4_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h deleted file mode 100644 index b9c1f9d5be..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * Copyright (c) 2014 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H - -#include <bsp/utility.h> - -struct stm32f4_adc_chan_s { - uint32_t sr; // 0x00: Status register -#define STM32F4_ADC_SR_OVR BSP_BIT32(5) // Overrun -#define STM32F4_ADC_SR_STRT BSP_BIT32(4) // Regular channel start flag -#define STM32F4_ADC_SR_JSTRT BSP_BIT32(3) // Injected channel start flag -#define STM32F4_ADC_SR_JEOC BSP_BIT32(2) // Injected channel end of conversion -#define STM32F4_ADC_SR_EOC BSP_BIT32(1) // Regular channel end of conversion -#define STM32F4_ADC_SR_AWD BSP_BIT32(0) // Analog watchdog flag - - uint32_t cr1; // 0x04: Control register 1 -#define STM32F4_ADC_CR1_OVRIE BSP_BIT32(26) // Overrun interrupt enable -#define STM32F4_ADC_CR1_RES(val) BSP_FLD32(val, 24, 25) // Resolution -#define STM32F4_ADC_CR1_RES_GET(reg) BSP_FLD32GET(reg, 24, 25) -#define STM32F4_ADC_CR1_RES_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) -#define ADC_CR1_RES_12BIT 0 -#define ADC_CR1_RES_10BIT 1 -#define ADC_CR1_RES_8BIT 2 -#define ADC_CR1_RES_6BIT 3 -#define STM32F4_ADC_CR1_AWDEN BSP_BIT32(23) // Analog watchdog enable on regular channels -#define STM32F4_ADC_CR1_JAWDEN BSP_BIT32(22) // Analog watchdog enable on injected channels -#define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count -#define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15) -#define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) -#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels -#define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels -#define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion -#define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode -#define STM32F4_ADC_CR1_SCAN BSP_BIT32(8) // Scan mode -#define STM32F4_ADC_CR1_JEOCIE BSP_BIT32(7) // Interrupt enable for injected channels -#define STM32F4_ADC_CR1_AWDIE BSP_BIT32(6) // Analog watchdog interrupt enable -#define STM32F4_ADC_CR1_EOCIE BSP_BIT32(5) // Interrupt enable for EOC -#define STM32F4_ADC_CR1_AWDCH(val) BSP_FLD32(val, 0, 4) // Analog watchdog channel select bits -#define STM32F4_ADC_CR1_AWDCH_GET(reg) BSP_FLD32GET(reg, 0, 4) -#define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) - - uint32_t cr2; // 0x08: Control register 2 -#define STM32F4_ADC_CR2_SWSTART BSP_BIT32(30) // Start conversion of regular channels -#define STM32F4_ADC_CR2_EXTEN(val) BSP_FLD32(val, 28, 29) // External trigger enable for regular channels -#define STM32F4_ADC_CR2_EXTEN_GET(reg) BSP_FLD32GET(reg, 28, 29) -#define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29) -#define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21) // External trigger enable for injected channels -#define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21) -#define STM32F4_ADC_CR2_JEXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) -#define ADC_CR2_TRIGGER_DISABLE 0 -#define ADC_CR2_TRIGGER_RISING 1 -#define ADC_CR2_TRIGGER_FALLING 2 -#define ADC_CR2_TRIGGER_BOTH 3 -#define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27) // External event select for regular group -#define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27) -#define STM32F4_ADC_CR2_EXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) -#define ADC_CR2_EVT_TIMER1_CC1 0x0 -#define ADC_CR2_EVT_TIMER1_CC2 0x1 -#define ADC_CR2_EVT_TIMER1_CC3 0x2 -#define ADC_CR2_EVT_TIMER2_CC2 0x3 -#define ADC_CR2_EVT_TIMER2_CC3 0x4 -#define ADC_CR2_EVT_TIMER2_CC4 0x5 -#define ADC_CR2_EVT_TIMER2_TRGO 0x6 -#define ADC_CR2_EVT_TIMER3_CC1 0x7 -#define ADC_CR2_EVT_TIMER3_TRGO 0x8 -#define ADC_CR2_EVT_TIMER4_CC1 0x9 -#define ADC_CR2_EVT_TIMER5_CC1 0xa -#define ADC_CR2_EVT_TIMER5_CC2 0xb -#define ADC_CR2_EVT_TIMER5_CC3 0xc -#define ADC_CR2_EVT_TIMER8_CC1 0xd -#define ADC_CR2_EVT_TIMER8_TRGO 0xe -#define ADC_CR2_EVT_EXTI_11 0xf -#define STM32F4_ADC_CR2_JSWSTART BSP_BIT32(22) // Start conversion of injected channels -#define STM32F4_ADC_CR2_JEXTSEL(val) BSP_FLD32(val, 16, 19) // External event select for injected group -#define STM32F4_ADC_CR2_JEXTSEL_GET(reg) BSP_FLD32GET(reg, 16, 19) -#define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) -#define ADC_CR2_JEVT_TIMER1_CC4 0x0 -#define ADC_CR2_JEVT_TIMER1_TRGO 0x1 -#define ADC_CR2_JEVT_TIMER2_CC1 0x2 -#define ADC_CR2_JEVT_TIMER2_TRGO 0x3 -#define ADC_CR2_JEVT_TIMER3_CC2 0x4 -#define ADC_CR2_JEVT_TIMER3_CC4 0x5 -#define ADC_CR2_JEVT_TIMER4_CC1 0x6 -#define ADC_CR2_JEVT_TIMER4_CC2 0x7 -#define ADC_CR2_JEVT_TIMER4_CC3 0x8 -#define ADC_CR2_JEVT_TIMER4_TRGO 0x9 -#define ADC_CR2_JEVT_TIMER5_CC4 0xa -#define ADC_CR2_JEVT_TIMER5_TRGO 0xb -#define ADC_CR2_JEVT_TIMER8_CC2 0xc -#define ADC_CR2_JEVT_TIMER8_CC3 0xd -#define ADC_CR2_JEVT_TIMER8_CC4 0xe -#define ADC_CR2_JEVT_EXTI_15 0xf -#define STM32F4_ADC_CR2_ALIGN BSP_BIT32(11) // Data alignment -#define STM32F4_ADC_CR2_ALIGN_RIGHT 0 -#define STM32F4_ADC_CR2_ALIGN_LEFT STM32F4_ADC_CR2_ALIGN -#define STM32F4_ADC_CR2_EOCS BSP_BIT32(10) // End of conversion selection -#define STM32F4_ADC_CR2_DDS BSP_BIT32(9) // DMA disable selection (single ADC mode) -#define STM32F4_ADC_CR2_DMA BSP_BIT32(8) // DMA access mode (single ADC) -#define STM32F4_ADC_CR2_CONT BSP_BIT32(1) // Continuous conversion -#define STM32F4_ADC_CR2_ADON BSP_BIT32(0) // A/D converter ON - - uint32_t smpr1; // 0x0C: Sample time register 1 -#define ADC_SAMPLE_3CYCLE 0 -#define ADC_SAMPLE_15CYCLE 1 -#define ADC_SAMPLE_28CYCLE 2 -#define ADC_SAMPLE_56CYCLE 3 -#define ADC_SAMPLE_84CYCLE 4 -#define ADC_SAMPLE_112CYCLE 5 -#define ADC_SAMPLE_144CYCLE 6 -#define ADC_SAMPLE_480CYCLE 7 -#define STM32F4_ADC_SMP18(val) BSP_FLD32(val, 24, 26) // Channel 18 sampling time selection -#define STM32F4_ADC_SMP18_GET(reg) BSP_FLD32GET(reg, 24, 26) -#define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) -#define STM32F4_ADC_SMP17(val) BSP_FLD32(val, 21, 23) // Channel 17 sampling time selection -#define STM32F4_ADC_SMP17_GET(reg) BSP_FLD32GET(reg, 21, 23) -#define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) -#define STM32F4_ADC_SMP16(val) BSP_FLD32(val, 18, 20) // Channel 16 sampling time selection -#define STM32F4_ADC_SMP16_GET(reg) BSP_FLD32GET(reg, 18, 20) -#define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) -#define STM32F4_ADC_SMP15(val) BSP_FLD32(val, 15, 17) // Channel 15 sampling time selection -#define STM32F4_ADC_SMP15_GET(reg) BSP_FLD32GET(reg, 15, 17) -#define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) -#define STM32F4_ADC_SMP14(val) BSP_FLD32(val, 12, 14) // Channel 14 sampling time selection -#define STM32F4_ADC_SMP14_GET(reg) BSP_FLD32GET(reg, 12, 14) -#define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) -#define STM32F4_ADC_SMP13(val) BSP_FLD32(val, 9, 11) // Channel 13 sampling time selection -#define STM32F4_ADC_SMP13_GET(reg) BSP_FLD32GET(reg, 9, 11) -#define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) -#define STM32F4_ADC_SMP12(val) BSP_FLD32(val, 6, 8) // Channel 12 sampling time selection -#define STM32F4_ADC_SMP12_GET(reg) BSP_FLD32GET(reg, 6, 8) -#define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) -#define STM32F4_ADC_SMP11(val) BSP_FLD32(val, 3, 5) // Channel 11 sampling time selection -#define STM32F4_ADC_SMP11_GET(reg) BSP_FLD32GET(reg, 3, 5) -#define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) -#define STM32F4_ADC_SMP10(val) BSP_FLD32(val, 0, 2) // Channel 10 sampling time selection -#define STM32F4_ADC_SMP10_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - - uint32_t smpr2; // 0x10: Sample time register 2 -#define STM32F4_ADC_SMP9(val) BSP_FLD32(val, 27, 29) // Channel 9 sampling time selection -#define STM32F4_ADC_SMP9_GET(reg) BSP_FLD32GET(reg, 27, 29) -#define STM32F4_ADC_SMP9_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) -#define STM32F4_ADC_SMP8(val) BSP_FLD32(val, 24, 26) // Channel 8 sampling time selection -#define STM32F4_ADC_SMP8_GET(reg) BSP_FLD32GET(reg, 24, 26) -#define STM32F4_ADC_SMP8_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) -#define STM32F4_ADC_SMP7(val) BSP_FLD32(val, 21, 23) // Channel 7 sampling time selection -#define STM32F4_ADC_SMP7_GET(reg) BSP_FLD32GET(reg, 21, 23) -#define STM32F4_ADC_SMP7_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23) -#define STM32F4_ADC_SMP6(val) BSP_FLD32(val, 18, 20) // Channel 6 sampling time selection -#define STM32F4_ADC_SMP6_GET(reg) BSP_FLD32GET(reg, 18, 20) -#define STM32F4_ADC_SMP6_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20) -#define STM32F4_ADC_SMP5(val) BSP_FLD32(val, 15, 17) // Channel 5 sampling time selection -#define STM32F4_ADC_SMP5_GET(reg) BSP_FLD32GET(reg, 15, 17) -#define STM32F4_ADC_SMP5_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17) -#define STM32F4_ADC_SMP4(val) BSP_FLD32(val, 12, 14) // Channel 4 sampling time selection -#define STM32F4_ADC_SMP4_GET(reg) BSP_FLD32GET(reg, 12, 14) -#define STM32F4_ADC_SMP4_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14) -#define STM32F4_ADC_SMP3(val) BSP_FLD32(val, 9, 11) // Channel 3 sampling time selection -#define STM32F4_ADC_SMP3_GET(reg) BSP_FLD32GET(reg, 9, 11) -#define STM32F4_ADC_SMP3_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11) -#define STM32F4_ADC_SMP2(val) BSP_FLD32(val, 6, 8) // Channel 2 sampling time selection -#define STM32F4_ADC_SMP2_GET(reg) BSP_FLD32GET(reg, 6, 8) -#define STM32F4_ADC_SMP2_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8) -#define STM32F4_ADC_SMP1(val) BSP_FLD32(val, 3, 5) // Channel 1 sampling time selection -#define STM32F4_ADC_SMP1_GET(reg) BSP_FLD32GET(reg, 3, 5) -#define STM32F4_ADC_SMP1_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) -#define STM32F4_ADC_SMP0(val) BSP_FLD32(val, 0, 2) // Channel 0 sampling time selection -#define STM32F4_ADC_SMP0_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define STM32F4_ADC_SMP0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - - uint32_t jofr[4]; // 0x14-0x20: Injected channel data offset registers -#define STM32F4_ADC_JOFFSET(val) BSP_FLD32(val, 0, 11) // Data offset for injected channel -#define STM32F4_ADC_JOFFSET_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define STM32F4_ADC_JOFFSET_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) - - uint32_t htr; // 0x24: Watchdog higher threshold register -#define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11) // Analog watchdog higher threshold -#define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define STM32F4_ADC_HT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) - - uint32_t ltr; // 0x28: Watchdog lower threshold register -#define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11) // Analog watchdog lower threshold -#define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11) -#define STM32F4_ADC_LT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) - - uint32_t sqr[3]; // 0x2c-0x34: Regular sequence registers -#define STM32F4_ADC_SQR_L(val) BSP_FLD32(val, 20, 23) // Regular channel sequence length -#define STM32F4_ADC_SQR_L_GET(reg) BSP_FLD32GET(reg, 20, 23) -#define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23) - - uint32_t jsqr; // 0x38: Injected sequence register -#define STM32F4_ADC_JSQR_JL(val) BSP_FLD32(val, 20, 21) // Injected sequence length -#define STM32F4_ADC_JSQR_JL_GET(reg) BSP_FLD32GET(reg, 20, 21) -#define STM32F4_ADC_JSQR_JL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21) -#define STM32F4_ADC_JSQR_JSQ4(val) BSP_FLD32(val, 15, 19) // 4th conversion in injected sequence -#define STM32F4_ADC_JSQR_JSQ4_GET(reg) BSP_FLD32GET(reg, 15, 19) -#define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19) -#define STM32F4_ADC_JSQR_JSQ3(val) BSP_FLD32(val, 10, 14) // 3rd conversion in injected sequence -#define STM32F4_ADC_JSQR_JSQ3_GET(reg) BSP_FLD32GET(reg, 10, 14) -#define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14) -#define STM32F4_ADC_JSQR_JSQ2(val) BSP_FLD32(val, 5, 9) // 2nd conversion in injected sequence -#define STM32F4_ADC_JSQR_JSQ2_GET(reg) BSP_FLD32GET(reg, 5, 9) -#define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9) -#define STM32F4_ADC_JSQR_JSQ1(val) BSP_FLD32(val, 0, 4) // 1st conversion in injected sequence -#define STM32F4_ADC_JSQR_JSQ1_GET(reg) BSP_FLD32GET(reg, 0, 4) -#define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) - - uint32_t jdr[4]; // 0x3c-0x48: Injected data registers -#define STM32F4_ADC_JDATA(val) BSP_FLD32(val, 0, 15) // Injected data -#define STM32F4_ADC_JDATA_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t dr; // 0x4c: Regular data register -#define STM32F4_ADC_DATA(val) BSP_FLD32(val, 0, 15) // Regular data -#define STM32F4_ADC_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_ADC_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - -} __attribute__ ((packed)); -typedef struct stm32f4_adc_chan_s stm32f4_adc_chan; - -struct stm32f4_adc_com_s { - uint32_t csr; // 0x00: Common status register -#define STM32F4_ADC_CSR_OVR3 BSP_BIT32(21) // Overrun flag ADC3 -#define STM32F4_ADC_CSR_STRT3 BSP_BIT32(20) // Regular start flag ADC3 -#define STM32F4_ADC_CSR_JSTRT3 BSP_BIT32(19) // Injected start flag ADC3 -#define STM32F4_ADC_CSR_JEOC3 BSP_BIT32(18) // Injected channel end of conversion flag ADC3 -#define STM32F4_ADC_CSR_EOC3 BSP_BIT32(17) // Channel end of conversion flag ADC3 -#define STM32F4_ADC_CSR_AWD3 BSP_BIT32(16) // Analog watchdog flag ADC3 -#define STM32F4_ADC_CSR_OVR2 BSP_BIT32(13) // Overrun flag ADC2 -#define STM32F4_ADC_CSR_STRT2 BSP_BIT32(12) // Regular start flag ADC2 -#define STM32F4_ADC_CSR_JSTRT2 BSP_BIT32(11) // Injected start flag ADC2 -#define STM32F4_ADC_CSR_JEOC2 BSP_BIT32(10) // Injected channel end of conversion flag ADC2 -#define STM32F4_ADC_CSR_EOC2 BSP_BIT32(9) // Channel end of conversion flag ADC2 -#define STM32F4_ADC_CSR_AWD2 BSP_BIT32(8) // Analog watchdog flag ADC2 -#define STM32F4_ADC_CSR_OVR1 BSP_BIT32(5) // Overrun flag ADC1 -#define STM32F4_ADC_CSR_STRT1 BSP_BIT32(4) // Regular start flag ADC1 -#define STM32F4_ADC_CSR_JSTRT1 BSP_BIT32(3) // Injected start flag ADC1 -#define STM32F4_ADC_CSR_JEOC1 BSP_BIT32(2) // Injected channel end of conversion flag ADC1 -#define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1 -#define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1 - - uint32_t ccr; // 0x00: Common control register -#define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable -#define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable -#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar -#define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17) -#define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) -#define ADC_ADCPRE_PCLK2_2 0 -#define ADC_ADCPRE_PCLK2_4 1 -#define ADC_ADCPRE_PCLK2_6 2 -#define ADC_ADCPRE_PCLK2_8 3 -#define STM32F4_ADC_CCR_DMA(val) BSP_FLD32(val, 14, 15) // DMA access mode for multi ADC -#define STM32F4_ADC_CCR_DMA_GET(reg) BSP_FLD32GET(reg, 14, 15) -#define STM32F4_ADC_CCR_DMA_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15) -#define ADC_DMA_DISABLE 0 -#define ADC_DMA_MODE1 1 -#define ADC_DMA_MODE2 2 -#define ADC_DMA_MODE3 3 -#define STM32F4_ADC_CCR_DDS BSP_BIT32(13) // DMA disable selection -#define STM32F4_ADC_CCR_DELAY(val) BSP_FLD32(val, 8, 11) // Delay between sampling phases -#define STM32F4_ADC_CCR_DELAY_GET(reg) BSP_FLD32GET(reg, 8, 11) -#define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) -#define ADC_DELAY_5T 0 -#define ADC_DELAY_6T 1 -#define ADC_DELAY_7T 2 -#define ADC_DELAY_8T 3 -#define ADC_DELAY_9T 4 -#define ADC_DELAY_10T 5 -#define ADC_DELAY_11T 6 -#define ADC_DELAY_12T 7 -#define ADC_DELAY_13T 8 -#define ADC_DELAY_14T 9 -#define ADC_DELAY_15T 10 -#define ADC_DELAY_16T 11 -#define ADC_DELAY_17T 12 -#define ADC_DELAY_18T 13 -#define ADC_DELAY_19T 14 -#define ADC_DELAY_20T 15 -#define STM32F4_ADC_CCR_MULTI(val) BSP_FLD32(val, 0, 4) // Multi ADC mode -#define STM32F4_ADC_CCR_MULTI_GET(reg) BSP_FLD32GET(reg, 0, 4) -#define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) -#define ADC_MULTI_INDEPENDENT 0x00 -#define ADC_MULTI_DUAL_REG_INJ 0x01 -#define ADC_MULTI_DUAL_REG_ALT 0x02 -#define ADC_MULTI_DUAL_INJ 0x05 -#define ADC_MULTI_DUAL_REG 0x06 -#define ADC_MULTI_DUAL_INTRL 0x07 -#define ADC_MULTI_DUAL_ALT_TRIG 0x09 -#define ADC_MULTI_TRIPLE_REG_INJ 0x11 -#define ADC_MULTI_TRIPLE_REG_ALT 0x12 -#define ADC_MULTI_TRIPLE_INJ 0x15 -#define ADC_MULTI_TRIPLE_REG 0x16 -#define ADC_MULTI_TRIPLE_INTRL 0x17 -#define ADC_MULTI_TRIPLE_ALT_TRIG 0x19 - - uint32_t cdr; // 0x00: Common regular data register -#define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item -#define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31) -#define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) -#define STM32F4_ADC_CDR_DATA1(val) BSP_FLD32(val, 0, 15) // 1st data item -#define STM32F4_ADC_CDR_DATA1_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - -} __attribute__ ((packed)); -typedef struct stm32f4_adc_com_s stm32f4_adc_com; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h deleted file mode 100644 index df44ad56e8..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h +++ /dev/null @@ -1,64 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H - -#include <bsp/utility.h> - -#define EXTI_PORTA 0 -#define EXTI_PORTB 1 -#define EXTI_PORTC 2 -#define EXTI_PORTD 3 -#define EXTI_PORTE 4 -#define EXTI_PORTF 5 -#define EXTI_PORTG 6 -#define EXTI_PORTH 7 -#define EXTI_PORTI 8 - -#define STM32F4_EXTI_LINE22 BSP_BIT32(21) -#define STM32F4_EXTI_LINE21 BSP_BIT32(21) -#define STM32F4_EXTI_LINE20 BSP_BIT32(20) -#define STM32F4_EXTI_LINE19 BSP_BIT32(19) -#define STM32F4_EXTI_LINE18 BSP_BIT32(18) -#define STM32F4_EXTI_LINE17 BSP_BIT32(17) -#define STM32F4_EXTI_LINE16 BSP_BIT32(16) -#define STM32F4_EXTI_LINE15 BSP_BIT32(15) -#define STM32F4_EXTI_LINE14 BSP_BIT32(14) -#define STM32F4_EXTI_LINE13 BSP_BIT32(13) -#define STM32F4_EXTI_LINE12 BSP_BIT32(12) -#define STM32F4_EXTI_LINE11 BSP_BIT32(11) -#define STM32F4_EXTI_LINE10 BSP_BIT32(10) -#define STM32F4_EXTI_LINE9 BSP_BIT32(9) -#define STM32F4_EXTI_LINE8 BSP_BIT32(8) -#define STM32F4_EXTI_LINE7 BSP_BIT32(7) -#define STM32F4_EXTI_LINE6 BSP_BIT32(6) -#define STM32F4_EXTI_LINE5 BSP_BIT32(5) -#define STM32F4_EXTI_LINE4 BSP_BIT32(4) -#define STM32F4_EXTI_LINE3 BSP_BIT32(3) -#define STM32F4_EXTI_LINE2 BSP_BIT32(2) -#define STM32F4_EXTI_LINE1 BSP_BIT32(1) -#define STM32F4_EXTI_LINE0 BSP_BIT32(0) - -struct stm32f4_exti_s { - uint32_t imr; // Interrupt mask - uint32_t emr; // Event mask - uint32_t rtsr; // Rising trigger selection - uint32_t ftsr; // Falling trigger selection - uint32_t swier; // Software interrupt event - uint32_t pr; // Pending -} __attribute__ ((packed)); -typedef struct stm32f4_exti_s stm32f4_exti; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h deleted file mode 100755 index f81b19cd40..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H - -#include <bsp/utility.h> - -struct stm32f4_flash_s { - - uint32_t acr; // Access and control register -#define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset -#define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset -#define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable -#define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable -#define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable -#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency -#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - - uint32_t keyr; // Key register -#define STM32F4_FLASH_KEYR_KEY1 0x45670123 -#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB - - uint32_t optkeyr; // Option key register -#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B -#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F - - uint32_t sr; // Status register -#define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy -#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error -#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error -#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error -#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error -#define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error -#define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation - - uint32_t cr; // Control register -#define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock -#define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable -#define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable -#define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start -#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size -#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9) -#define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9) -#define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number -#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6) -#define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6) -#define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase -#define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase -#define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming - - uint32_t optcr; // Option control register -#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect -#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27) -#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27) -#define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect -#define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15) -#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) -#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes -#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7) -#define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) -#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level -#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3) -#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) -#define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start -#define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock - -} __attribute__ ((packed)); -typedef struct stm32f4_flash_s stm32f4_flash; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h deleted file mode 100644 index b129c23595..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/** - * @file - * @ingroup stm32f4_gpio - * @brief STM32F4XXXX GPIO support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H - -#include <bsp/utility.h> - -typedef struct { - uint32_t moder; - uint32_t otyper; - uint32_t ospeedr; - uint32_t pupdr; - uint32_t idr; - uint32_t odr; - uint32_t bsrr; - uint32_t lckr; - uint32_t afr [2]; - uint32_t reserved_28 [246]; -} stm32f4_gpio; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_GPIO_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h deleted file mode 100755 index cc2eb90c4c..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h +++ /dev/null @@ -1,445 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H - -#include <bsp/utility.h> - -#define USB_OTG_NUM_EPS 4 -#define USB_OTG_MAX_TX_FIFOS 4 - -#define USB_FIFO_BASE 0x1000 -#define USB_FIFO_OFFS 0x1000 - -struct stm32f4_otgfs_s { - uint32_t gotgctl; // 0x00: Control and status register -#define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid -#define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid -#define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time -#define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status -#define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable -#define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable -#define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request -#define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status -#define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request -#define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success - - uint32_t gotgint; // 0x04: Interrupt register -#define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done -#define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change -#define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected -#define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change -#define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change -#define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected - - uint32_t gahbcfg; // 0x08: AHB configuration register -#define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level -#define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level -#define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask - - uint32_t gusbcfg; // 0x0C: USB configuration register -#define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet -#define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode -#define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode -#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time -#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13) -#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13) -#define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable -#define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable -#define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select -#define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration -#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2) -#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) - - uint32_t grstctl; // 0x10: Reset register -#define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle -#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number -#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10) -#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10) -#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10) -#define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush -#define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush -#define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset -#define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset -#define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset - - uint32_t gintsts; // 0x14: Core interrupt register -#define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt -#define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt -#define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt -#define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change -#define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty -#define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt -#define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt -#define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer -#define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer -#define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer -#define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt -#define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt -#define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt -#define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt -#define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done -#define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset -#define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend -#define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend -#define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective -#define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective -#define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty -#define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty -#define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame -#define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt -#define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt -#define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation - - uint32_t gintmsk; // 0x18: Interrupt mask register - - uint32_t grxstsr; // 0x1C: Receive status debug read - - uint32_t grxstsp; // 0x20: OTG status read and pop -#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number -#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24) -#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24) -#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status -#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20) -#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20) -#define PKTSTS_IN_DATA (0x2) -#define PKTSTS_IN_COMPLETE (0x3) -#define PKTSTS_TOGGLE_ERR (0x5) -#define PKTSTS_HALTED (0x7) -#define PKTSTS_OUTNAK (0x1) -#define PKTSTS_OUT_DATA (0x2) -#define PKTSTS_OUT_COMPLETE (0x3) -#define PKTSTS_SETUP_COMPLETE (0x4) -#define PKTSTS_SETUP_DATA (0x6) -#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID -#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16) -#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16) -#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0) -#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1) -#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2) -#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3) -#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count -#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14) -#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14) -#define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number -#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -#define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number -#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) - - uint32_t grxfsiz; // 0x24: Receive FIFO size register -#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15) -#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) -#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16 -#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256 - - uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size -#define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31) -#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31) -#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) -#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16 -#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256 -#define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15) -#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t resv2C; - - uint32_t gi2cctl; // 0x30 - uint32_t resv34; // 0x34 - - uint32_t gccfg; // 0x38: General core configuration register -#define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable -#define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable -#define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device -#define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device -#define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down - - uint32_t cid; // 0x3C: Product ID - - uint32_t resv40[48]; // 0x40 - 0x9C - - uint32_t hptxfsiz; // 0x100 - - uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104 - -} __attribute__ ((packed)); -typedef struct stm32f4_otgfs_s stm32f4_otgfs; - -struct stm32f4_otgfs_dregs_s { - uint32_t dcfg; // 0x800 -#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval -#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12) -#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12) -#define PFIVL_80 0 -#define PFIVL_85 1 -#define PFIVL_90 2 -#define PFIVL_95 3 -#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address -#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10) -#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10) -#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake -#define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed -#define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1) -#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) -#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3) - - uint32_t dctl; // 0x804 -#define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done -#define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK -#define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK -#define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK -#define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK -#define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control -#define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6) -#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6) -#define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status -#define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status -#define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect -#define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling - - uint32_t dsts; // 0x808 -#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF -#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21) -#define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error -#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed -#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2) -#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3) -#define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status - - uint32_t unused4; // 0x80C - - uint32_t diepmsk; // 0x810 - - uint32_t doepmsk; // 0x814 - - uint32_t daint; // 0x818 -#define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt -#define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt -#define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt - - uint32_t daintmsk; // 0x81C -#define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask -#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31) -#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31) -#define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask -#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t unused5[2]; // 0x820 - 0x824 - - uint32_t dvbusdis; // 0x828 -#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time -#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t dvbuspulse; // 0x82C -#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time -#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15) -#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t unused6; // 0x830 - - uint32_t diepempmsk; // 0x834 -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask -#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask - -} __attribute__ ((packed)); -typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs; - -struct stm32f4_otgfs_inepregs_s { - uint32_t diepctl; // 0x900 -#define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable -#define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable -#define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame -#define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame -#define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame -#define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK -#define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK -#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number -#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25) -#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25) -#define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake -#define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt -#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) -#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) -#define EPTYPE_CTRL 0 -#define EPTYPE_ISOC 1 -#define EPTYPE_BULK 2 -#define EPTYPE_INTR 3 -#define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status -#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame -#define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes) -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1) -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) -#define EP0_MPSIZ_8 3 -#define EP0_MPSIZ_16 2 -#define EP0_MPSIZ_32 1 -#define EP0_MPSIZ_64 0 -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8) -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16) -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32) -#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64) -#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) -#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) -#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) - - uint32_t reserved_04; - - uint32_t diepint; // 0x908 -#define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty -#define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective -#define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty -#define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition -#define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled -#define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete - - uint32_t reserved_0C; - - uint32_t dieptsiz; // 0x910 -#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count -#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20) -#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20) -#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size -#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) -#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) -#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count -#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) -#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) -#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count -#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) -#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) -#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size -#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) -#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) - - uint32_t reserved_14; - - uint32_t dtxfsts; // 0x918 -#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available -#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15) -#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) - - uint32_t reserved_1C; - -} __attribute__ ((packed)); -typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs; - -struct stm32f4_otgfs_outepregs_s { - uint32_t doepctl; // 0xBx0: Endpoint control register -#define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable -#define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable -#define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame -#define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame -#define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK -#define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK -#define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake -#define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode -#define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt -#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19) -#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19) -#define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status -#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame -#define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint -#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes) -#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10) -#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10) - - uint32_t resv04; - - uint32_t doepint; // 0xBx8: Endpoint interrupt register -#define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received -#define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled -#define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done -#define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt -#define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete - - uint32_t doeptsiz; // 0xBy0 -#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count -#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30) -#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) -#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count -#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size -#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6) -#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6) -#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID -#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30) -#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30) -#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count -#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28) -#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28) -#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size -#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18) -#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18) - - uint32_t resv14[3]; -} __attribute__ ((packed)); -typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs; - -struct stm32f4_otgfs_pwrctlregs_s { - uint32_t pcgcctl; // 0xE00: Power and clock gating control register -#define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend -#define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK -#define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk -} __attribute__ ((packed)); -typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h deleted file mode 100755 index 85af10738f..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H - -#include <bsp/utility.h> - -struct stm32f4_pwr_s { - - uint32_t cr; // Control register -#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection -#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode -#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection -#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection -#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7) -#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) -#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable -#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag -#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag -#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep -#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep - - uint32_t csr; // Control / status register -#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit -#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable -#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin -#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready -#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output -#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag -#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag - -} __attribute__ ((packed)); -typedef struct stm32f4_pwr_s stm32f4_pwr; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h deleted file mode 100755 index 5c004328d7..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - * @file - * @ingroup stm32f4xxxx_rcc - * @brief STM32F4XXXX RCC support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H - -#include <bsp/utility.h> - -/** - * @defgroup stm32f4xxxx_rcc STM32F4XXXX RCC Support - * @ingroup stm32f4_rcc - * @brief STM32F4XXXX RCC Support - * @{ - */ - -typedef struct { - uint32_t cr; -#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag -#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable -#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag -#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable -#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable -#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass -#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag -#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable -#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag -#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable - - uint32_t pllcfgr; -#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27) -#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27) -#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27) -#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source -#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC -#define STM32F4_RCC_PLLCFGR_SRC_HSI 0 -#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17) -#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17) -#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17) -#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0) -#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1) -#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2) -#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3) -#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14) -#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14) -#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14) -#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5) -#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5) -#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) - - uint32_t cfgr; -#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2 -#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31) -#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31) -#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0) -#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1) -#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2) -#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3) -#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar -#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29) -#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29) -#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0) -#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4) -#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5) -#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6) -#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7) -#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar -#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26) -#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26) -#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0) -#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4) -#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5) -#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6) -#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7) -#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection -#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1 -#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22) -#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22) -#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0) -#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1) -#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2) -#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3) -#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock -#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20) -#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20) -#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2) -#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15) -#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15) -#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0) -#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4) -#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5) -#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6) -#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7) -#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1) -#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12) -#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) -#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0) -#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4) -#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5) -#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6) -#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7) -#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar -#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7) -#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) -#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0) -#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8) -#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9) -#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10) -#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11) -#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12) -#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13) -#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14) -#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15) -#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status -#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3) -#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3) -#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0) -#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1) -#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2) -#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch -#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1) -#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) -#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0) -#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1) -#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2) - - uint32_t cir; - - uint32_t ahbrstr [3]; - - uint32_t reserved_1c; - - uint32_t apbrstr [2]; - - uint32_t reserved_28 [2]; - - uint32_t ahbenr [3]; - - uint32_t reserved_3c; - - uint32_t apbenr [2]; - - uint32_t reserved_48 [2]; - - uint32_t ahblpenr [3]; - - uint32_t reserved_5c; - - uint32_t apblpenr [2]; - - uint32_t reserved_68 [2]; - - uint32_t bdcr; - - uint32_t csr; - - uint32_t reserved_78 [2]; - - uint32_t sscgr; - - uint32_t plli2scfgr; - -} stm32f4_rcc; - -/** @} */ - -#define RCC_CR_HSION BSP_BIT32( 0 ) -#define RCC_CR_HSIRDY BSP_BIT32( 1 ) -#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 ) -#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 ) -#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 ) -#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 ) -#define RCC_CR_HSEON BSP_BIT32( 16 ) -#define RCC_CR_HSERDY BSP_BIT32( 17 ) -#define RCC_CR_HSEBYP BSP_BIT32( 18 ) -#define RCC_CR_CSSON BSP_BIT32( 19 ) -#define RCC_CR_PLLON BSP_BIT32( 24 ) -#define RCC_CR_PLLRDY BSP_BIT32( 25 ) -#define RCC_CR_PLLI2SON BSP_BIT32( 26 ) -#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 ) - -#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 ) -#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 ) -#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 ) -#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 ) - -#define RCC_PLLCFGR_PLLP 16 -#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 ) -#define RCC_PLLCFGR_PLLP_BY_2 0 -#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 ) -#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 ) -#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 ) - -#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 ) -#define RCC_PLLCFGR_PLLSRC_HSI 0 - -#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 ) -#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 ) - -#define RCC_CFGR_SW 0 -#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 ) -#define RCC_CFGR_SW_HSI 0 -#define RCC_CFGR_SW_HSE 1 -#define RCC_CFGR_SW_PLL 2 - -#define RCC_CFGR_SWS 2 -#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 ) -#define RCC_CFGR_SWS_HSI 0 -#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 ) -#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 ) - -#define RCC_CFGR_HPRE 4 -#define RCC_CFGR_HPRE_BY_1 0 -#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 ) -#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 ) -#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 ) -#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 ) -#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 ) -#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 ) -#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 ) -#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 ) - -#define RCC_CFGR_PPRE1 10 -#define RCC_CFGR_PPRE1_BY_1 0 -#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 ) -#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 ) -#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 ) -#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 ) - -#define RCC_CFGR_PPRE2 13 -#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 ) -#define RCC_CFGR_PPRE2_BY_1 0 -#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 ) -#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 ) -#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 ) -#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 ) - -#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 ) -#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 ) - -#define RCC_CFGR_MCO1 21 -#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 ) -#define RCC_CFGR_MCO1_HSI 0 -#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 ) -#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 ) -#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 ) - -#define RCC_CFGR_I2SSRC BSP_BIT32( 23 ) - -#define RCC_CFGR_MCO1PRE 24 -#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 ) -#define RCC_CFGR_MCO1PRE_BY_1 0 -#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 ) -#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 ) -#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 ) -#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 ) - -#define RCC_CFGR_MCO2PRE 27 -#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 ) -#define RCC_CFGR_MCO2PRE_BY_1 0 -#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 ) -#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 ) -#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 ) -#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 ) - -#define RCC_CFGR_MCO2 30 -#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 ) -#define RCC_CFGR_MCO2_SYSCLK 0 -#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 ) -#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 ) -#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 ) - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h deleted file mode 100755 index 5249363cef..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h +++ /dev/null @@ -1,108 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H - -#include <bsp/utility.h> - -#define EXTI_PORTA 0 -#define EXTI_PORTB 1 -#define EXTI_PORTC 2 -#define EXTI_PORTD 3 -#define EXTI_PORTE 4 -#define EXTI_PORTF 5 -#define EXTI_PORTG 6 -#define EXTI_PORTH 7 -#define EXTI_PORTI 8 - -struct stm32f4_syscfg_s { - uint32_t memrmp; // Memory remap -#define STM32F4_SYSCFG_MEM_MODE(val) BSP_FLD32(val, 0, 1) -#define STM32F4_SYSCFG_MEM_MODE_GET(reg) BSP_FLD32GET(reg, 0, 1) -#define STM32F4_SYSCFG_MEM_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) - uint32_t pmc; // Peripheral mode configuration -#define STM32F4_SYSCFG_RMII_SEL BSP_BIT32(23) - uint32_t exticr[4]; // External interrupt configuration -#define STM32F4_SYSCFG_EXTI0_IDX 0 -#define STM32F4_SYSCFG_EXTI0(val) BSP_FLD32(val, 0, 3) -#define STM32F4_SYSCFG_EXTI0_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_SYSCFG_EXTI0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -#define STM32F4_SYSCFG_EXTI1_IDX 0 -#define STM32F4_SYSCFG_EXTI1(val) BSP_FLD32(val, 4, 7) -#define STM32F4_SYSCFG_EXTI1_GET(reg) BSP_FLD32GET(reg, 4, 7) -#define STM32F4_SYSCFG_EXTI1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) -#define STM32F4_SYSCFG_EXTI2_IDX 0 -#define STM32F4_SYSCFG_EXTI2(val) BSP_FLD32(val, 8, 11) -#define STM32F4_SYSCFG_EXTI2_GET(reg) BSP_FLD32GET(reg, 8, 11) -#define STM32F4_SYSCFG_EXTI2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) -#define STM32F4_SYSCFG_EXTI3_IDX 0 -#define STM32F4_SYSCFG_EXTI3(val) BSP_FLD32(val, 12, 15) -#define STM32F4_SYSCFG_EXTI3_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define STM32F4_SYSCFG_EXTI3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) -#define STM32F4_SYSCFG_EXTI4_IDX 1 -#define STM32F4_SYSCFG_EXTI4(val) BSP_FLD32(val, 0, 3) -#define STM32F4_SYSCFG_EXTI4_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_SYSCFG_EXTI4_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -#define STM32F4_SYSCFG_EXTI5_IDX 1 -#define STM32F4_SYSCFG_EXTI5(val) BSP_FLD32(val, 4, 7) -#define STM32F4_SYSCFG_EXTI5_GET(reg) BSP_FLD32GET(reg, 4, 7) -#define STM32F4_SYSCFG_EXTI5_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) -#define STM32F4_SYSCFG_EXTI6_IDX 1 -#define STM32F4_SYSCFG_EXTI6(val) BSP_FLD32(val, 8, 11) -#define STM32F4_SYSCFG_EXTI6_GET(reg) BSP_FLD32GET(reg, 8, 11) -#define STM32F4_SYSCFG_EXTI6_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) -#define STM32F4_SYSCFG_EXTI7_IDX 1 -#define STM32F4_SYSCFG_EXTI7(val) BSP_FLD32(val, 12, 15) -#define STM32F4_SYSCFG_EXTI7_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define STM32F4_SYSCFG_EXTI7_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) -#define STM32F4_SYSCFG_EXTI8_IDX 2 -#define STM32F4_SYSCFG_EXTI8(val) BSP_FLD32(val, 0, 3) -#define STM32F4_SYSCFG_EXTI8_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_SYSCFG_EXTI8_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -#define STM32F4_SYSCFG_EXTI9_IDX 2 -#define STM32F4_SYSCFG_EXTI9(val) BSP_FLD32(val, 4, 7) -#define STM32F4_SYSCFG_EXTI9_GET(reg) BSP_FLD32GET(reg, 4, 7) -#define STM32F4_SYSCFG_EXTI9_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) -#define STM32F4_SYSCFG_EXTI10_IDX 2 -#define STM32F4_SYSCFG_EXTI10(val) BSP_FLD32(val, 8, 11) -#define STM32F4_SYSCFG_EXTI10_GET(reg) BSP_FLD32GET(reg, 8, 11) -#define STM32F4_SYSCFG_EXTI10_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) -#define STM32F4_SYSCFG_EXTI11_IDX 2 -#define STM32F4_SYSCFG_EXTI11(val) BSP_FLD32(val, 12, 15) -#define STM32F4_SYSCFG_EXTI11_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define STM32F4_SYSCFG_EXTI11_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) -#define STM32F4_SYSCFG_EXTI12_IDX 3 -#define STM32F4_SYSCFG_EXTI12(val) BSP_FLD32(val, 0, 3) -#define STM32F4_SYSCFG_EXTI12_GET(reg) BSP_FLD32GET(reg, 0, 3) -#define STM32F4_SYSCFG_EXTI12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) -#define STM32F4_SYSCFG_EXTI13_IDX 3 -#define STM32F4_SYSCFG_EXTI13(val) BSP_FLD32(val, 4, 7) -#define STM32F4_SYSCFG_EXTI13_GET(reg) BSP_FLD32GET(reg, 4, 7) -#define STM32F4_SYSCFG_EXTI13_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) -#define STM32F4_SYSCFG_EXTI14_IDX 3 -#define STM32F4_SYSCFG_EXTI14(val) BSP_FLD32(val, 8, 11) -#define STM32F4_SYSCFG_EXTI14_GET(reg) BSP_FLD32GET(reg, 8, 11) -#define STM32F4_SYSCFG_EXTI14_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) -#define STM32F4_SYSCFG_EXTI15_IDX 3 -#define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15) -#define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15) -#define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) - uint32_t cmpcr; // Compensation cell control register -#define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8) -#define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0) -} __attribute__ ((packed)); -typedef struct stm32f4_syscfg_s stm32f4_syscfg; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h deleted file mode 100755 index 45038945b8..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h +++ /dev/null @@ -1,206 +0,0 @@ -/* - * Copyright (c) 2013 Chris Nott. All rights reserved. - * - * Virtual Logic - * 21-25 King St. - * Rockdale NSW 2216 - * Australia - * <rtems@vl.com.au> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H -#define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H - -#include <bsp/utility.h> - -struct stm32f4_tim_s { - uint16_t cr1; // Control register 1 -#define STM32F4_TIMER_CR1_CKD_DIV 0x0300 -#define STM32F4_TIMER_CR1_CKD_DIV1 0x0000 -#define STM32F4_TIMER_CR1_CKD_DIV2 0x0100 -#define STM32F4_TIMER_CR1_CKD_DIV3 0x0200 -#define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7) -#define STM32F4_TIMER_CR1_CMS 0x0060 -#define STM32F4_TIMER_CR1_CMS_EDGE 0x0000 -#define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020 -#define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040 -#define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060 -#define STM32F4_TIMER_CR1_DIR BSP_BIT16(4) -#define STM32F4_TIMER_CR1_DIR_UP 0x0000 -#define STM32F4_TIMER_CR1_DIR_DOWN 0x0010 -#define STM32F4_TIMER_CR1_DIR_OPM 0x0008 -#define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000 -#define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008 -#define STM32F4_TIMER_CR1_DIR_URS 0x0004 -#define STM32F4_TIMER_CR1_DIR_UDIS 0x0002 -#define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000 -#define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002 -#define STM32F4_TIMER_CR1_CEN 0x0001 - uint16_t reserved_02; - uint16_t cr2; // Control register 2 - uint16_t reserved_06; - uint16_t smcr; // Slave mode control register - uint16_t reserved_0a; - uint16_t dier; // DMA / interrupt enable register -#define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable -#define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable -#define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable -#define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable -#define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable -#define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable -#define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable -#define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable -#define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable -#define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable -#define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable -#define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable - - uint16_t reserved_0e; - uint16_t sr; // Status register -#define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag -#define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag -#define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag -#define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag -#define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag -#define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag -#define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag -#define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag -#define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag -#define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag - uint16_t reserved_12; - uint16_t egr; // Event generation register -#define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event -#define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event -#define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation) -#define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation) -#define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation) -#define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event - uint16_t reserved_16; - uint16_t ccmr1; // Capture / compare mode register 1 -#define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable -#define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14) -#define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14) -#define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) -#define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0) -#define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1) -#define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2) -#define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3) -#define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4) -#define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5) -#define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6) -#define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7) -#define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable -#define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable -#define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9) -#define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9) -#define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) -#define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0) -#define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1) -#define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2) -#define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3) -#define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable -#define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6) -#define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6) -#define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) -#define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0) -#define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1) -#define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2) -#define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3) -#define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4) -#define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5) -#define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6) -#define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7) -#define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable -#define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable -#define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1) -#define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1) -#define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) -#define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0) -#define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1) -#define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2) -#define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3) - uint16_t reserved_1a; - uint16_t ccmr2; // Capture / compare mode register 2 -#define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable -#define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14) -#define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14) -#define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14) -#define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0) -#define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1) -#define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2) -#define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3) -#define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4) -#define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5) -#define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6) -#define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7) -#define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable -#define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable -#define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9) -#define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9) -#define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9) -#define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0) -#define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1) -#define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2) -#define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3) -#define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable -#define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6) -#define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6) -#define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6) -#define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0) -#define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1) -#define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2) -#define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3) -#define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4) -#define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5) -#define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6) -#define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7) -#define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable -#define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable -#define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1) -#define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1) -#define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1) -#define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0) -#define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1) -#define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2) -#define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3) - uint16_t reserved_1e; - uint16_t ccer; // Capture / compare enable register -#define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity -#define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity -#define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable -#define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity -#define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity -#define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable -#define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity -#define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity -#define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable -#define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity -#define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity -#define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable - uint16_t reserved_22; - uint32_t cnt; // Counter register -#define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31) -#define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31) -#define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31) - uint16_t psc; // Prescalar - uint16_t reserved_2a; - uint32_t arr; // Auto-reload register - uint16_t rcr; // Repetition counter register - uint16_t rserved_32; - uint32_t ccr[4];// Capture / compare registers - uint16_t bdtr; // Break and dead-time register - uint16_t reserved_46; - uint16_t dcr; // DMA control register - uint16_t reserved_4a; - uint16_t dmar; // DMA address for full transfer - uint16_t reserved_4e; - uint16_t or; // Option register - uint16_t reserved_52; -} __attribute__ ((packed)); -typedef struct stm32f4_tim_s stm32f4_tim; - -#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/include/tm27.h b/c/src/lib/libbsp/arm/stm32f4/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include <rtems/tm27-default.h> diff --git a/c/src/lib/libbsp/arm/stm32f4/include/usart.h b/c/src/lib/libbsp/arm/stm32f4/include/usart.h deleted file mode 100644 index bac0f6845a..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/include/usart.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * @ingroup stm32f4_usart - * @brief USART (universal synchronous/asynchronous receiver/transmitter) support. - */ - -/* - * Copyright (c) 2012 Sebastian Huber. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_STM32F4_USART_H -#define LIBBSP_ARM_STM32F4_USART_H - -#include <libchip/serial.h> - -/** - * @defgroup stm32f4_usart USART Support - * @ingroup arm_stm32f4 - * @brief USART Support - * @{ - */ - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -extern const console_fns stm32f4_usart_fns; - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_STM32F4_USART_H */ diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am deleted file mode 100644 index 50489450a0..0000000000 --- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am +++ /dev/null @@ -1,167 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - -$(PROJECT_LIB)/start.$(OBJEXT): start.$(OBJEXT) $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/start.$(OBJEXT) -TMPINSTALL_FILES += $(PROJECT_LIB)/start.$(OBJEXT) - -$(PROJECT_LIB)/linkcmds: startup/linkcmds $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds -TMPINSTALL_FILES += $(PROJECT_LIB)/linkcmds - -$(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h - -$(PROJECT_INCLUDE)/bsp.h: include/bsp.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp.h - -$(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h - -$(PROJECT_INCLUDE)/bsp/bootcard.h: ../../shared/include/bootcard.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/bootcard.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/bootcard.h - -$(PROJECT_INCLUDE)/bsp/utility.h: ../../shared/include/utility.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/utility.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/utility.h - -$(PROJECT_INCLUDE)/bsp/irq-generic.h: ../../shared/include/irq-generic.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-generic.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-generic.h - -$(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h - -$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h - -$(PROJECT_INCLUDE)/bsp/start.h: ../shared/include/start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/start.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/start.h - -$(PROJECT_INCLUDE)/bsp/armv7m-irq.h: ../shared/armv7m/include/armv7m-irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/armv7m-irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/armv7m-irq.h - -$(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h - -$(PROJECT_INCLUDE)/bsp/usart.h: include/usart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/usart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/usart.h - -$(PROJECT_INCLUDE)/bsp/stm32f4.h: include/stm32f4.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4.h - -$(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h: include/stm32f10xxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_gpio.h - -$(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h: include/stm32f10xxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_rcc.h - -$(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h: include/stm32f10xxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h: include/stm32f4xxxx_adc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h: include/stm32f4xxxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h: include/stm32f4xxxx_pwr.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h: include/stm32f4xxxx_syscfg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h: include/stm32f4xxxx_tim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h - -$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h: include/stm32f4xxxx_otgfs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h - -$(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_i2c.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_i2c.h - -$(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h - -$(PROJECT_INCLUDE)/bsp/stm32_usart.h: include/stm32_usart.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_usart.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_usart.h - -$(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h - -$(PROJECT_INCLUDE)/bsp/rcc.h: include/rcc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/rcc.h -PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/rcc.h - diff --git a/c/src/lib/libbsp/arm/stm32f4/bsp_specs b/c/src/lib/libbsp/arm/stm32f4/startup/bsp_specs index 47dd31d46b..47dd31d46b 100644 --- a/c/src/lib/libbsp/arm/stm32f4/bsp_specs +++ b/c/src/lib/libbsp/arm/stm32f4/startup/bsp_specs |