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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-09-03 01:30:20 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-09-07 20:29:38 +0200 |
| commit | 7ec689adc75790f5c564f5ab2f87caeea4a7bed8 (patch) | |
| tree | d062d22bbe67a2c60d7659607c413ee8fc95e06d /c/src/lib/libbsp/arm/shared | |
| parent | bsp/atsam: Add SDRAM IS42S16320F-7BL. (diff) | |
| download | rtems-7ec689adc75790f5c564f5ab2f87caeea4a7bed8.tar.bz2 | |
bsps/arm: use defines for cache type register format field.
The change documents meaning of codes and opens
well defined way to use cache type format for cache
examination/debugging outside of arm-cp15.h file.
Diffstat (limited to 'c/src/lib/libbsp/arm/shared')
0 files changed, 0 insertions, 0 deletions