Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

5 files changed, 0 insertions, 895 deletions

diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h
deleted file mode 100644
index 45d567b36c..0000000000
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/**
- * @file
- *
- * @ingroup lpc_dma
- *
- * @brief DMA support API.
- */
-
-/*
- * Copyright (c) 2010-2012 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
-#define LIBBSP_ARM_SHARED_LPC_DMA_H
-
-#include <bspopts.h>
-#include <bsp/utility.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup lpc_dma DMA Support
- *
- * @ingroup arm_lpc24xx
- * @ingroup arm_lpc32xx
- *
- * @brief DMA support.
- *
- * @{
- */
-
-/**
- * @brief DMA descriptor item.
- */
-typedef struct {
-  uint32_t src;
-  uint32_t dest;
-  uint32_t lli;
-  uint32_t ctrl;
-} lpc_dma_descriptor;
-
-/**
- * @brief DMA channel block.
- */
-typedef struct {
-  lpc_dma_descriptor desc;
-  uint32_t cfg;
-  uint32_t reserved [3];
-} lpc_dma_channel;
-
-/**
- * @brief DMA control block.
- */
-typedef struct {
-  uint32_t int_stat;
-  uint32_t int_tc_stat;
-  uint32_t int_tc_clear;
-  uint32_t int_err_stat;
-  uint32_t int_err_clear;
-  uint32_t raw_tc_stat;
-  uint32_t raw_err_stat;
-  uint32_t enabled_channels;
-  uint32_t soft_burst_req;
-  uint32_t soft_single_req;
-  uint32_t soft_last_burst_req;
-  uint32_t soft_last_single_req;
-  uint32_t cfg;
-  uint32_t sync;
-  uint32_t reserved [50];
-  lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT];
-} lpc_dma;
-
-/**
- * @name DMA Configuration Register
- *
- * @{
- */
-
-#define DMA_CFG_E BSP_BIT32(0)
-#define DMA_CFG_M_0 BSP_BIT32(1)
-#define DMA_CFG_M_1 BSP_BIT32(2)
-
-/** @} */
-
-/**
- * @name DMA Channel Control Register
- *
- * @{
- */
-
-#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
-#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
-
-#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
-#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
-#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
-#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
-#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
-#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
-#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
-#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
-#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
-
-#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
-#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
-#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
-#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
-#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
-#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
-#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
-#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
-#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
-
-#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
-#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
-#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
-#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
-
-#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
-#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
-#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
-#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
-
-#define DMA_CH_CTRL_S BSP_BIT32(24)
-#define DMA_CH_CTRL_D BSP_BIT32(25)
-#define DMA_CH_CTRL_SI BSP_BIT32(26)
-#define DMA_CH_CTRL_DI BSP_BIT32(27)
-#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
-#define DMA_CH_CTRL_I BSP_BIT32(31)
-
-/** @} */
-
-/**
- * @name DMA Channel Configuration Register
- *
- * @{
- */
-
-#define DMA_CH_CFG_E BSP_BIT32(0)
-#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
-#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
-
-#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
-#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
-#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
-#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
-#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
-#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
-#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
-#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
-#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
-
-#define DMA_CH_CFG_IE BSP_BIT32(14)
-#define DMA_CH_CFG_ITC BSP_BIT32(15)
-#define DMA_CH_CFG_L BSP_BIT32(16)
-#define DMA_CH_CFG_A BSP_BIT32(17)
-#define DMA_CH_CFG_H BSP_BIT32(18)
-
-/** @} */
-
-/**
- * @name LPC24XX DMA Peripherals
- *
- * @{
- */
-
-#define LPC24XX_DMA_PER_SSP_0_TX 0
-#define LPC24XX_DMA_PER_SSP_0_RX 1
-#define LPC24XX_DMA_PER_SSP_1_TX 2
-#define LPC24XX_DMA_PER_SSP_1_RX 3
-#define LPC24XX_DMA_PER_SD_MMC 4
-#define LPC24XX_DMA_PER_I2S_CH_0 5
-#define LPC24XX_DMA_PER_I2S_CH_1 6
-
-/** @} */
-
-/**
- * @name LPC32XX DMA Peripherals
- *
- * @{
- */
-
-#define LPC32XX_DMA_PER_I2S_0_CH_0 0
-#define LPC32XX_DMA_PER_I2S_0_CH_1 13
-#define LPC32XX_DMA_PER_I2S_1_CH_0 2
-#define LPC32XX_DMA_PER_I2S_1_CH_1 10
-#define LPC32XX_DMA_PER_NAND_0 1
-#define LPC32XX_DMA_PER_NAND_1 12
-#define LPC32XX_DMA_PER_SD_MMC 4
-#define LPC32XX_DMA_PER_SSP_0_RX 14
-#define LPC32XX_DMA_PER_SSP_0_TX 15
-#define LPC32XX_DMA_PER_SSP_1_RX 3
-#define LPC32XX_DMA_PER_SSP_1_TX 11
-#define LPC32XX_DMA_PER_UART_1_RX 6
-#define LPC32XX_DMA_PER_UART_1_TX 5
-#define LPC32XX_DMA_PER_UART_2_RX 8
-#define LPC32XX_DMA_PER_UART_2_TX 7
-#define LPC32XX_DMA_PER_UART_7_RX 10
-#define LPC32XX_DMA_PER_UART_7_TX 9
-
-/** @} */
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-emc.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-emc.h
deleted file mode 100644
index 31cb4241c8..0000000000
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-emc.h
+++ /dev/null
@@ -1,170 +0,0 @@
-/**
- * @file
- *
- * @ingroup lpc_emc
- *
- * @brief EMC support API.
- */
-
-/*
- * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
-#define LIBBSP_ARM_SHARED_LPC_EMC_H
-
-#include <bsp/utility.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif /* __cplusplus */
-
-/**
- * @defgroup lpc_emc EMC Support
- *
- * @ingroup arm_lpc24xx
- * @ingroup arm_lpc32xx
- *
- * @brief EMC Support
- *
- * @{
- */
-
-/**
- * @name EMC Control Register (EMCControl)
- *
- * @{
- */
-
-#define EMC_CTRL_E BSP_BIT32(0)
-#define EMC_CTRL_M BSP_BIT32(0)
-#define EMC_CTRL_L BSP_BIT32(2)
-
-/** @} */
-
-/**
- * @name EMC Dynamic Memory Control Register (EMCDynamicControl)
- *
- * @{
- */
-
-#define EMC_DYN_CTRL_CE BSP_BIT32(0)
-#define EMC_DYN_CTRL_CS BSP_BIT32(1)
-#define EMC_DYN_CTRL_SR BSP_BIT32(2)
-#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
-#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
-#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
-#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
-#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
-#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
-#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
-#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
-#define EMC_DYN_CTRL_DP BSP_BIT32(13)
-
-/** @} */
-
-/**
- * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
- *
- * @{
- */
-
-#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
-#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
-#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
-#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
-
-/** @} */
-
-/**
- * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
- *
- * @{
- */
-
-#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
-#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
-#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
-#define EMC_DYN_CFG_B BSP_BIT32(19)
-#define EMC_DYN_CFG_P BSP_BIT32(20)
-
-/** @} */
-
-/**
- * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
- *
- * @{
- */
-
-#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
-#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
-
-/** @} */
-
-#define EMC_DYN_CHIP_COUNT 4
-
-#define EMC_STATIC_CHIP_COUNT 4
-
-typedef struct {
-  uint32_t config;
-  uint32_t rascas;
-  uint32_t reserved_0 [6];
-} lpc_emc_dynamic;
-
-typedef struct {
-  uint32_t config;
-  uint32_t waitwen;
-  uint32_t waitoen;
-  uint32_t waitrd;
-  uint32_t waitpage;
-  uint32_t waitwr;
-  uint32_t waitturn;
-  uint32_t reserved_0 [1];
-} lpc_emc_static;
-
-typedef struct {
-  uint32_t control;
-  uint32_t status;
-  uint32_t config;
-  uint32_t reserved_0 [5];
-  uint32_t dynamiccontrol;
-  uint32_t dynamicrefresh;
-  uint32_t dynamicreadconfig;
-  uint32_t reserved_1;
-  uint32_t dynamictrp;
-  uint32_t dynamictras;
-  uint32_t dynamictsrex;
-  uint32_t dynamictapr;
-  uint32_t dynamictdal;
-  uint32_t dynamictwr;
-  uint32_t dynamictrc;
-  uint32_t dynamictrfc;
-  uint32_t dynamictxsr;
-  uint32_t dynamictrrd;
-  uint32_t dynamictmrd;
-  uint32_t dynamictcdlr;
-  uint32_t reserved_3 [8];
-  uint32_t staticextendedwait;
-  uint32_t reserved_4 [31];
-  lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
-  uint32_t reserved_5 [32];
-  lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
-} lpc_emc;
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h
deleted file mode 100644
index 65e951b7d7..0000000000
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/**
- * @file
- *
- * @ingroup lpc_i2s
- *
- * @brief I2S API.
- */
-
-/*
- * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H
-#define LIBBSP_ARM_SHARED_LPC_I2S_H
-
-#include <bsp/utility.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup lpc_i2s I2S Support
- *
- * @ingroup arm_lpc24xx
- * @ingroup arm_lpc32xx
- *
- * @brief I2S support.
- *
- * @{
- */
-
-/**
- * @brief I2S control block.
- */
-typedef struct {
-  uint32_t dao;
-  uint32_t dai;
-  uint32_t txfifo;
-  uint32_t rxfifo;
-  uint32_t state;
-  uint32_t dma [2];
-  uint32_t irq;
-  uint32_t txrate;
-  uint32_t rxrate;
-} lpc_i2s;
-
-/**
- * @name I2S Digital Audio Input and Output
- *
- * @{
- */
-
-#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1)
-#define I2S_DAIO_MONO BSP_BIT32(2)
-#define I2S_DAIO_STOP BSP_BIT32(3)
-#define I2S_DAIO_RESET BSP_BIT32(4)
-#define I2S_DAIO_WS_SEL BSP_BIT32(5)
-#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14)
-#define I2S_DAIO_MUTE BSP_BIT32(15)
-
-/** @} */
-
-/**
- * @name I2S Status Feedback
- *
- * @{
- */
-
-#define I2S_STATE_IRQ BSP_BIT32(0)
-#define I2S_STATE_DMAREQ_0 BSP_BIT32(1)
-#define I2S_STATE_DMAREQ_1 BSP_BIT32(2)
-#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11)
-#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19)
-
-/** @} */
-
-/**
- * @name I2S DMA Configuration
- *
- * @{
- */
-
-#define I2S_DMA_RX_ENABLE BSP_BIT32(0)
-#define I2S_DMA_TX_ENABLE BSP_BIT32(1)
-#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
-#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
-
-/** @} */
-
-/**
- * @name I2S Interrupt Request Control
- *
- * @{
- */
-
-#define I2S_IRQ_RX BSP_BIT32(0)
-#define I2S_IRQ_TX BSP_BIT32(1)
-#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
-#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
-
-/** @} */
-
-/**
- * @name I2S Transmit and Receive Clock Rate
- *
- * @{
- */
-
-#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9)
-#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7)
-#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15)
-
-/** @} */
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-lcd.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-lcd.h
deleted file mode 100644
index a3ca4fe11a..0000000000
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-lcd.h
+++ /dev/null
@@ -1,213 +0,0 @@
-/**
- * @file
- *
- * @ingroup lpc_lcd
- *
- * @brief LCD support API.
- */
-
-/*
- * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
- *
- *  embedded brains GmbH
- *  Obere Lagerstr. 30
- *  82178 Puchheim
- *  Germany
- *  <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
-#define LIBBSP_ARM_SHARED_LPC_LCD_H
-
-#include <bsp/utility.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup lpc_lcd LCD Support
- *
- * @ingroup lpc
- * @ingroup arm_lpc32xx
- *
- * @brief LCD support.
- *
- * @{
- */
-
-typedef struct {
-  uint8_t img [1024];
-  uint32_t ctrl;
-  uint32_t cfg;
-  uint32_t pal0;
-  uint32_t pal1;
-  uint32_t xy;
-  uint32_t clip;
-  uint32_t intmsk;
-  uint32_t intclr;
-  uint32_t intraw;
-  uint32_t intstat;
-} lpc_cursor;
-
-typedef struct {
-  uint32_t timh;
-  uint32_t timv;
-  uint32_t pol;
-  uint32_t le;
-  uint32_t upbase;
-  uint32_t lpbase;
-  uint32_t ctrl;
-  uint32_t intmsk;
-  uint32_t intraw;
-  uint32_t intstat;
-  uint32_t intclr;
-  uint32_t upcurr;
-  uint32_t lpcurr;
-  uint8_t reserved_0 [0x200 - 0x034];
-  uint16_t pal [256];
-  uint8_t reserved_1 [0x800 - 0x400];
-  lpc_cursor crsr;
-} lpc_lcd;
-
-/**
- * @name LCD Configuration Register
- *
- * @{
- */
-
-#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
-#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
-#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
-#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
-
-/** @} */
-
-/**
- * @name LCD Horizontal Timing Register
- *
- * @{
- */
-
-#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
-#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
-#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
-#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
-#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
-#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
-#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
-#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
-
-/** @} */
-
-/**
- * @name LCD Vertical Timing Register
- *
- * @{
- */
-
-#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
-#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
-#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
-#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
-#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
-#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
-#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
-#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
-
-/** @} */
-
-/**
- * @name LCD Clock and Signal Polarity Register
- *
- * @{
- */
-
-#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
-#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
-#define LCD_POL_CLKSEL BSP_BIT32(5)
-#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
-#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
-#define LCD_POL_IVS BSP_BIT32(11)
-#define LCD_POL_IHS BSP_BIT32(12)
-#define LCD_POL_IPC BSP_BIT32(13)
-#define LCD_POL_IOE BSP_BIT32(14)
-#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
-#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
-#define LCD_POL_BCD BSP_BIT32(26)
-#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
-#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
-
-/** @} */
-
-/**
- * @name LCD Line End Control Register
- *
- * @{
- */
-
-#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
-#define LCD_LE_LEE BSP_BIT32(16)
-
-/** @} */
-
-/**
- * @name LCD Control Register
- *
- * @{
- */
-
-#define LCD_CTRL_LCDEN BSP_BIT32(0)
-#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
-#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
-#define LCD_CTRL_LCDBW BSP_BIT32(4)
-#define LCD_CTRL_LCDTFT BSP_BIT32(5)
-#define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
-#define LCD_CTRL_LCDDUAL BSP_BIT32(7)
-#define LCD_CTRL_BGR BSP_BIT32(8)
-#define LCD_CTRL_BEBO BSP_BIT32(9)
-#define LCD_CTRL_BEPO BSP_BIT32(10)
-#define LCD_CTRL_LCDPWR BSP_BIT32(11)
-#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
-#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
-#define LCD_CTRL_WATERMARK BSP_BIT32(16)
-
-/** @} */
-
-/**
- * @name LCD Interrupt Registers
- *
- * @{
- */
-
-#define LCD_INT_FUF BSP_BIT32(1)
-#define LCD_INT_LNBU BSP_BIT32(2)
-#define LCD_INT_VCOMP BSP_BIT32(3)
-#define LCD_INT_BER BSP_BIT32(4)
-
-/** @} */
-
-/**
- * @name LCD Color Palette Register
- *
- * @{
- */
-
-#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
-#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
-#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
-#define LCD_PAL_I BSP_BIT16(15)
-
-/** @} */
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */
diff --git a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h b/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
deleted file mode 100644
index 4c7ad4f1d1..0000000000
--- a/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- * @file
- *
- * @ingroup lpc_timer
- *
- * @brief Timer API.
- */
-
-/*
- * Copyright (c) 2009
- * embedded brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * <rtems@embedded-brains.de>
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
-#define LIBBSP_ARM_SHARED_LPC_TIMER_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @defgroup lpc_timer Timer Support
- *
- * @ingroup arm_lpc24xx
- * @ingroup arm_lpc32xx
- *
- * @brief Timer support.
- *
- * @{
- */
-
-/**
- * @name Interrupt Register Defines
- *
- * @{
- */
-
-#define LPC_TIMER_IR_MR0 0x1U
-#define LPC_TIMER_IR_MR1 0x2U
-#define LPC_TIMER_IR_MR2 0x4U
-#define LPC_TIMER_IR_MR3 0x8U
-#define LPC_TIMER_IR_CR0 0x10U
-#define LPC_TIMER_IR_CR1 0x20U
-#define LPC_TIMER_IR_CR2 0x40U
-#define LPC_TIMER_IR_CR3 0x80U
-#define LPC_TIMER_IR_ALL 0xffU
-
-/** @} */
-
-/**
- * @name Timer Control Register Defines
- *
- * @{
- */
-
-#define LPC_TIMER_TCR_EN 0x1U
-#define LPC_TIMER_TCR_RST 0x2U
-
-/** @} */
-
-/**
- * @name Match Control Register Defines
- *
- * @{
- */
-
-#define LPC_TIMER_MCR_MR0_INTR 0x1U
-#define LPC_TIMER_MCR_MR0_RST 0x2U
-#define LPC_TIMER_MCR_MR0_STOP 0x4U
-#define LPC_TIMER_MCR_MR1_INTR 0x8U
-#define LPC_TIMER_MCR_MR1_RST 0x10U
-#define LPC_TIMER_MCR_MR1_STOP 0x20U
-#define LPC_TIMER_MCR_MR2_INTR 0x40U
-#define LPC_TIMER_MCR_MR2_RST 0x80U
-#define LPC_TIMER_MCR_MR2_STOP 0x100U
-#define LPC_TIMER_MCR_MR3_INTR 0x200U
-#define LPC_TIMER_MCR_MR3_RST 0x400U
-#define LPC_TIMER_MCR_MR3_STOP 0x800U
-
-/** @} */
-
-/**
- * @name Capture Control Register Defines
- *
- * @{
- */
-
-#define LPC_TIMER_CCR_CAP0_RE 0x1U
-#define LPC_TIMER_CCR_CAP0_FE 0x2U
-#define LPC_TIMER_CCR_CAP0_INTR 0x4U
-#define LPC_TIMER_CCR_CAP1_RE 0x8U
-#define LPC_TIMER_CCR_CAP1_FE 0x10U
-#define LPC_TIMER_CCR_CAP1_INTR 0x20U
-#define LPC_TIMER_CCR_CAP2_RE 0x40U
-#define LPC_TIMER_CCR_CAP2_FE 0x80U
-#define LPC_TIMER_CCR_CAP2_INTR 0x100U
-#define LPC_TIMER_CCR_CAP3_RE 0x200U
-#define LPC_TIMER_CCR_CAP3_FE 0x400U
-#define LPC_TIMER_CCR_CAP3_INTR 0x800U
-
-/** @} */
-
-/**
- * @name External Match Register Defines
- *
- * @{
- */
-
-#define LPC_TIMER_EMR_EM0_RE 0x1U
-#define LPC_TIMER_EMR_EM1_FE 0x2U
-#define LPC_TIMER_EMR_EM2_INTR 0x4U
-#define LPC_TIMER_EMR_EM3_RE 0x8U
-#define LPC_TIMER_EMR_EMC0_FE 0x10U
-#define LPC_TIMER_EMR_EMC1_INTR 0x20U
-#define LPC_TIMER_EMR_EMC2_RE 0x40U
-#define LPC_TIMER_EMR_EMC3_FE 0x80U
-
-/** @} */
-
-/**
- * @brief Timer control block.
- */
-typedef struct {
-  uint32_t ir;
-  uint32_t tcr;
-  uint32_t tc;
-  uint32_t pr;
-  uint32_t pc;
-  uint32_t mcr;
-  uint32_t mr0;
-  uint32_t mr1;
-  uint32_t mr2;
-  uint32_t mr3;
-  uint32_t ccr;
-  uint32_t cr0;
-  uint32_t cr1;
-  uint32_t cr2;
-  uint32_t cr3;
-  uint32_t emr;
-  uint32_t ctcr;
-} lpc_timer;
-
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */