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author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2014-04-17 10:59:47 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-04-17 13:25:11 +0200 |
commit | db5a84d0ad4186e8875cdad9db15c7516364921f (patch) | |
tree | 933e4c7b74d1b501f8e396c2cdd9be871e807627 /c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | |
parent | bsp/arm: Correct L2 cache flushing (diff) | |
download | rtems-db5a84d0ad4186e8875cdad9db15c7516364921f.tar.bz2 |
bsp/arm: Correct cache misalignment handling
Correct misalignment handling and prepare for locking.
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h')
-rw-r--r-- | c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h index 77069bd1df..e4a19ad6ff 100644 --- a/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h +++ b/c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h @@ -247,8 +247,8 @@ static inline void arm_cache_l1_flush_data_range( uint32_t adx = (uint32_t) d_addr & ~ARM_CACHE_L1_DATA_LINE_MASK; const uint32_t ADDR_LAST = - ( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK; - + (uint32_t)( (size_t) d_addr + n_bytes - 1 ); + ARM_CACHE_L1_ERRATA_764369_HANDLER(); for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { @@ -300,13 +300,13 @@ static inline void arm_cache_l1_invalidate_data_range( uint32_t adx = (uint32_t) d_addr & ~ARM_CACHE_L1_DATA_LINE_MASK; const uint32_t end = - ( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK; + (uint32_t)( (size_t)d_addr + n_bytes -1); ARM_CACHE_L1_ERRATA_764369_HANDLER(); /* Back starting address up to start of a line and invalidate until end */ for (; - adx < end; + adx <= end; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { /* Invalidate the Instruction cache line */ arm_cp15_data_cache_invalidate_line( (void*)adx ); @@ -325,7 +325,7 @@ static inline void arm_cache_l1_invalidate_instruction_range( uint32_t adx = (uint32_t) i_addr & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK; const uint32_t end = - ( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK; + (uint32_t)( (size_t)i_addr + n_bytes -1); arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); @@ -333,7 +333,7 @@ static inline void arm_cache_l1_invalidate_instruction_range( /* Back starting address up to start of a line and invalidate until end */ for (; - adx < end; + adx <= end; adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) { /* Invalidate the Instruction cache line */ arm_cp15_instruction_cache_invalidate_line( (void*)adx ); |