bsp/realview-pbx-a9: New BSP

1 files changed, 86 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
new file mode 100644
index 0000000000..7d8f637bad
--- /dev/null
+++ b/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
+#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
+
+#include <bsp/utility.h>
+
+typedef struct {
+  uint32_t ctrl;
+  uint32_t cfg;
+  uint32_t pwrst;
+  uint32_t invss;
+  uint32_t reserved_10[12];
+  uint32_t fltstart;
+  uint32_t fltend;
+  uint32_t reserved_48[2];
+  uint32_t sac;
+  uint32_t snsac;
+} a9mpcore_scu;
+
+typedef struct {
+} a9mpcore_gic;
+
+typedef struct {
+  uint32_t cntr;
+  uint32_t reserved_04;
+  uint32_t ctrl;
+  uint32_t irqst;
+  uint32_t cmpval;
+  uint32_t reserved_14;
+  uint32_t autoinc;
+} a9mpcore_gt;
+
+typedef struct {
+  uint32_t load;
+  uint32_t cntr;
+  uint32_t ctrl;
+#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
+#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
+#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
+#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
+  uint32_t irqst;
+#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
+} a9mpcore_pt;
+
+typedef struct {
+  uint32_t load;
+  uint32_t cntr;
+  uint32_t ctrl;
+  uint32_t irqst;
+  uint32_t rstst;
+  uint32_t dis;
+} a9mpcore_pw;
+
+typedef struct {
+} a9mpcore_idist;
+
+typedef struct {
+  a9mpcore_scu scu;
+  uint32_t reserved_58[42];
+  a9mpcore_gic gic;
+  uint32_t reserved_100[64];
+  a9mpcore_gt gt;
+  uint32_t reserved_21c[249];
+  a9mpcore_pt pt;
+  uint32_t reserved_610[4];
+  a9mpcore_pw pw;
+  uint32_t reserved_638[626];
+  a9mpcore_idist idist;
+} a9mpcore;
+
+#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */