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| author | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-07-03 00:19:38 +0200 |
|---|---|---|
| committer | Pavel Pisa <pisa@cmp.felk.cvut.cz> | 2016-10-02 10:40:33 +0200 |
| commit | eb3af275ead2a9f5972fa1a7b69a4017a8cdf606 (patch) | |
| tree | cc61eea50a586b4c4666a21e80669ec94f249f4f /c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | |
| parent | score/arm: Ensure that copile time alignment is 64 bytes for Cortex-A multilib. (diff) | |
| download | rtems-eb3af275ead2a9f5972fa1a7b69a4017a8cdf606.tar.bz2 | |
rtems+bsps/cache: Define cache manager operations for code synchronization and maximal alignment.
There is need for unambiguous named and defined cache function
which should be called when code is updated, loaded
or is self-modifying.
There should be function to obtain maximal cache line length
as well. This function can and should be used for allocations
which can be used for data and or code and ensures that
there are no partial cache lines overlaps on start and
end of allocated region.
Updates #2782
Diffstat (limited to 'c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h')
0 files changed, 0 insertions, 0 deletions