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authorJoel Sherrill <joel.sherrill@OARcorp.com>2007-05-01 19:15:38 +0000
committerJoel Sherrill <joel.sherrill@OARcorp.com>2007-05-01 19:15:38 +0000
commite890774a799e1ea99221330f54d05cd7e8158629 (patch)
tree41737b358fe6702ef1d69b4027df10b6cd9ae196 /c/src/lib/libbsp/arm/rtl22xx/times
parentRebase against gcc-core-4.2.0-20070430 (gcc-4.2.0 rc2) (diff)
downloadrtems-e890774a799e1ea99221330f54d05cd7e8158629.tar.bz2
2007-05-01 Ray Xu <xr@trasin.net>
* README, times, console/lpc22xx_uart.h, console/uart.c, include/bsp.h, start/start.S, startup/bspstart.c, startup/exit.c, startup/linkcmds: Update BSP to address changes between 4.7 and CVS head as well as to address comments from Ralf and Joel.
Diffstat (limited to 'c/src/lib/libbsp/arm/rtl22xx/times')
-rw-r--r--c/src/lib/libbsp/arm/rtl22xx/times5
1 files changed, 2 insertions, 3 deletions
diff --git a/c/src/lib/libbsp/arm/rtl22xx/times b/c/src/lib/libbsp/arm/rtl22xx/times
index d8ded9d968..18a7ce338c 100644
--- a/c/src/lib/libbsp/arm/rtl22xx/times
+++ b/c/src/lib/libbsp/arm/rtl22xx/times
@@ -5,9 +5,9 @@
#
Board: rtl22xx
-CPU: Philips 2210
+CPU: Philips LPC2210
Clock Speed: 60MHz
-Memory Configuration: 512K SRAM, 16 bit bus, no SDRAM, nor cache
+Memory Configuration: 512K SRAM(256K used to store the .text), 16 bit bus, no SDRAM, nor cache
Cache: Data and Instruction cache enabled
Wait States:
@@ -21,4 +21,3 @@ rtems_semaphore_delete 380
rtems_semaphore_obtain: available 136
rtems_semaphore_obtain: not available -- NO_WAIT 136
rtems_semaphore_release: no waiting tasks 307
-