2010-10-14 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* include/emc.h, include/i2c.h, include/lpc32xx.h, include/nand-mlc.h:
	Update for <bsp/utility.h> changes.

5 files changed, 128 insertions, 123 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
index 1276c768e1..e07819e863 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
+++ b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog
@@ -1,3 +1,8 @@
+2010-10-14	Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+	* include/emc.h, include/i2c.h, include/lpc32xx.h, include/nand-mlc.h:
+	Update for <bsp/utility.h> changes.
+
 2010-09-28	Sebastian Huber <sebastian.huber@embedded-brains.de>
 
 	* misc/mmu.c: New file.
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/emc.h b/c/src/lib/libbsp/arm/lpc32xx/include/emc.h
index 2eb5a3bda3..e85702a776 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/emc.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/emc.h
@@ -47,19 +47,19 @@ extern "C" {
  * @{
  */
 
-#define SDRAMCLK_CLOCKS_DIS BIT32(0)
-#define SDRAMCLK_DDR_MODE BIT32(1)
-#define SDRAMCLK_DDR_DQSIN_DELAY(val) FIELD32(val, 2, 6)
-#define SDRAMCLK_RTC_TICK_EN BIT32(7)
-#define SDRAMCLK_SW_DDR_CAL BIT32(8)
-#define SDRAMCLK_CAL_DELAY BIT32(9)
-#define SDRAMCLK_SENSITIVITY_FACTOR(val) FIELD32(val, 10, 12)
-#define SDRAMCLK_DCA_STATUS BIT32(13)
-#define SDRAMCLK_COMMAND_DELAY(val) FIELD32(val, 14, 18)
-#define SDRAMCLK_SW_DDR_RESET BIT32(19)
-#define SDRAMCLK_PIN_1_FAST BIT32(20)
-#define SDRAMCLK_PIN_2_FAST BIT32(21)
-#define SDRAMCLK_PIN_3_FAST BIT32(22)
+#define SDRAMCLK_CLOCKS_DIS BSP_BIT32(0)
+#define SDRAMCLK_DDR_MODE BSP_BIT32(1)
+#define SDRAMCLK_DDR_DQSIN_DELAY(val) BSP_FLD32(val, 2, 6)
+#define SDRAMCLK_RTC_TICK_EN BSP_BIT32(7)
+#define SDRAMCLK_SW_DDR_CAL BSP_BIT32(8)
+#define SDRAMCLK_CAL_DELAY BSP_BIT32(9)
+#define SDRAMCLK_SENSITIVITY_FACTOR(val) BSP_FLD32(val, 10, 12)
+#define SDRAMCLK_DCA_STATUS BSP_BIT32(13)
+#define SDRAMCLK_COMMAND_DELAY(val) BSP_FLD32(val, 14, 18)
+#define SDRAMCLK_SW_DDR_RESET BSP_BIT32(19)
+#define SDRAMCLK_PIN_1_FAST BSP_BIT32(20)
+#define SDRAMCLK_PIN_2_FAST BSP_BIT32(21)
+#define SDRAMCLK_PIN_3_FAST BSP_BIT32(22)
 
 /** @} */
 
@@ -69,8 +69,8 @@ extern "C" {
  * @{
  */
 
-#define EMC_CTRL_EN BIT32(0)
-#define EMC_CTRL_LOW_POWER BIT32(2)
+#define EMC_CTRL_EN BSP_BIT32(0)
+#define EMC_CTRL_LOW_POWER BSP_BIT32(2)
 
 /** @} */
 
@@ -80,18 +80,18 @@ extern "C" {
  * @{
  */
 
-#define EMC_DYN_CTRL_CE BIT32(0)
-#define EMC_DYN_CTRL_CS BIT32(1)
-#define EMC_DYN_CTRL_SR BIT32(2)
-#define EMC_DYN_CTRL_SRMCC BIT32(3)
-#define EMC_DYN_CTRL_IMCC BIT32(4)
-#define EMC_DYN_CTRL_MCC BIT32(5)
-#define EMC_DYN_CTRL_I_MASK MASK32(7, 8)
-#define EMC_DYN_CTRL_I_NORMAL FIELD32(0x0, 7, 8)
-#define EMC_DYN_CTRL_I_MODE FIELD32(0x1, 7, 8)
-#define EMC_DYN_CTRL_I_PALL FIELD32(0x2, 7, 8)
-#define EMC_DYN_CTRL_I_NOP FIELD32(0x3, 7, 8)
-#define EMC_DYN_CTRL_DP BIT32(9)
+#define EMC_DYN_CTRL_CE BSP_BIT32(0)
+#define EMC_DYN_CTRL_CS BSP_BIT32(1)
+#define EMC_DYN_CTRL_SR BSP_BIT32(2)
+#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
+#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
+#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
+#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
+#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
+#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
+#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
+#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
+#define EMC_DYN_CTRL_DP BSP_BIT32(9)
 
 /** @} */
 
@@ -101,10 +101,10 @@ extern "C" {
  * @{
  */
 
-#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) FIELD32(val, 0, 1)
-#define EMC_DYN_READ_CONFIG_SDR_POL_POS BIT32(4)
-#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) FIELD32(val, 8, 9)
-#define EMC_DYN_READ_CONFIG_DDR_POL_POS BIT32(12)
+#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
+#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
+#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
+#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
 
 /** @} */
 
@@ -114,9 +114,9 @@ extern "C" {
  * @{
  */
 
-#define EMC_DYN_CFG_MD(val) FIELD32(val, 0, 2)
-#define EMC_DYN_CFG_AM(val) FIELD32(val, 7, 14)
-#define EMC_DYN_CFG_P(val) BIT32(20)
+#define EMC_DYN_CFG_MD(val) BSP_FLD32(val, 0, 2)
+#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
+#define EMC_DYN_CFG_P(val) BSP_BIT32(20)
 
 /** @} */
 
@@ -126,8 +126,8 @@ extern "C" {
  * @{
  */
 
-#define EMC_DYN_RAS(val) FIELD32(val, 0, 3)
-#define EMC_DYN_CAS(val) FIELD32(val, 7, 10)
+#define EMC_DYN_RAS(val) BSP_FLD32(val, 0, 3)
+#define EMC_DYN_CAS(val) BSP_FLD32(val, 7, 10)
 
 /** @} */
 
@@ -137,7 +137,7 @@ extern "C" {
  * @{
  */
 
-#define EMC_AHB_PORT_BUFF_EN BIT32(0)
+#define EMC_AHB_PORT_BUFF_EN BSP_BIT32(0)
 
 /** @} */
 
@@ -147,7 +147,7 @@ extern "C" {
  * @{
  */
 
-#define EMC_AHB_TIMEOUT(val) FIELD32(val, 0, 9)
+#define EMC_AHB_TIMEOUT(val) BSP_FLD32(val, 0, 9)
 
 /** @} */
 
@@ -182,14 +182,14 @@ extern "C" {
 #define SDRAM_EXTMODE_64MB(mode) \
   (SDRAM_ADDR_BANK_64MB(1, 0) | SDRAM_ADDR_ROW_64MB(mode))
 
-#define SDRAM_MODE_BURST_LENGTH(val) FIELD32(val, 0, 2)
-#define SDRAM_MODE_BURST_INTERLEAVE BIT32(3)
-#define SDRAM_MODE_CAS(val) FIELD32(val, 4, 6)
-#define SDRAM_MODE_TEST_MODE(val) FIELD32(val, 7, 8)
-#define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BIT32(9)
+#define SDRAM_MODE_BURST_LENGTH(val) BSP_FLD32(val, 0, 2)
+#define SDRAM_MODE_BURST_INTERLEAVE BSP_BIT32(3)
+#define SDRAM_MODE_CAS(val) BSP_FLD32(val, 4, 6)
+#define SDRAM_MODE_TEST_MODE(val) BSP_FLD32(val, 7, 8)
+#define SDRAM_MODE_WRITE_BURST_SINGLE_BIT BSP_BIT32(9)
 
-#define SDRAM_EXTMODE_PASR(val) FIELD32(val, 0, 2)
-#define SDRAM_EXTMODE_DRIVER_STRENGTH(val) FIELD32(val, 5, 6)
+#define SDRAM_EXTMODE_PASR(val) BSP_FLD32(val, 0, 2)
+#define SDRAM_EXTMODE_DRIVER_STRENGTH(val) BSP_FLD32(val, 5, 6)
 
 /** @} */
 
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h b/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h
index b25ea28c0a..232f834d34 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/i2c.h
@@ -49,11 +49,11 @@ extern "C" {
  * @{
  */
 
-#define I2CCLK_1_EN BIT32(0)
-#define I2CCLK_2_EN BIT32(1)
-#define I2CCLK_1_HIGH_DRIVE BIT32(2)
-#define I2CCLK_2_HIGH_DRIVE BIT32(3)
-#define I2CCLK_USB_HIGH_DRIVE BIT32(4)
+#define I2CCLK_1_EN BSP_BIT32(0)
+#define I2CCLK_2_EN BSP_BIT32(1)
+#define I2CCLK_1_HIGH_DRIVE BSP_BIT32(2)
+#define I2CCLK_2_HIGH_DRIVE BSP_BIT32(3)
+#define I2CCLK_USB_HIGH_DRIVE BSP_BIT32(4)
 
 /** @} */
 
@@ -63,10 +63,10 @@ extern "C" {
  * @{
  */
 
-#define I2C_TX_READ BIT32(0)
-#define I2C_TX_ADDR(val) FIELD32(val, 1, 7)
-#define I2C_TX_START BIT32(8)
-#define I2C_TX_STOP BIT32(9)
+#define I2C_TX_READ BSP_BIT32(0)
+#define I2C_TX_ADDR(val) BSP_FLD32(val, 1, 7)
+#define I2C_TX_START BSP_BIT32(8)
+#define I2C_TX_STOP BSP_BIT32(9)
 
 /** @} */
 
@@ -76,20 +76,20 @@ extern "C" {
  * @{
  */
 
-#define I2C_STAT_TDI BIT32(0)
-#define I2C_STAT_AFI BIT32(1)
-#define I2C_STAT_NAI BIT32(2)
-#define I2C_STAT_DRMI BIT32(3)
-#define I2C_STAT_DRSI BIT32(4)
-#define I2C_STAT_ACTIVE BIT32(5)
-#define I2C_STAT_SCL BIT32(6)
-#define I2C_STAT_SDA BIT32(7)
-#define I2C_STAT_RFF BIT32(8)
-#define I2C_STAT_RFE BIT32(9)
-#define I2C_STAT_TFF BIT32(10)
-#define I2C_STAT_TFE BIT32(11)
-#define I2C_STAT_TFFS BIT32(12)
-#define I2C_STAT_TFES BIT32(13)
+#define I2C_STAT_TDI BSP_BIT32(0)
+#define I2C_STAT_AFI BSP_BIT32(1)
+#define I2C_STAT_NAI BSP_BIT32(2)
+#define I2C_STAT_DRMI BSP_BIT32(3)
+#define I2C_STAT_DRSI BSP_BIT32(4)
+#define I2C_STAT_ACTIVE BSP_BIT32(5)
+#define I2C_STAT_SCL BSP_BIT32(6)
+#define I2C_STAT_SDA BSP_BIT32(7)
+#define I2C_STAT_RFF BSP_BIT32(8)
+#define I2C_STAT_RFE BSP_BIT32(9)
+#define I2C_STAT_TFF BSP_BIT32(10)
+#define I2C_STAT_TFE BSP_BIT32(11)
+#define I2C_STAT_TFFS BSP_BIT32(12)
+#define I2C_STAT_TFES BSP_BIT32(13)
 
 /** @} */
 
@@ -99,17 +99,17 @@ extern "C" {
  * @{
  */
 
-#define I2C_CTRL_TDIE BIT32(0)
-#define I2C_CTRL_AFIE BIT32(1)
-#define I2C_CTRL_NAIE BIT32(2)
-#define I2C_CTRL_DRMIE BIT32(3)
-#define I2C_CTRL_DRSIE BIT32(4)
-#define I2C_CTRL_RFFIE BIT32(5)
-#define I2C_CTRL_RFDAIE BIT32(6)
-#define I2C_CTRL_TFFIO BIT32(7)
-#define I2C_CTRL_RESET BIT32(8)
-#define I2C_CTRL_SEVEN BIT32(9)
-#define I2C_CTRL_TFFSIE BIT32(10)
+#define I2C_CTRL_TDIE BSP_BIT32(0)
+#define I2C_CTRL_AFIE BSP_BIT32(1)
+#define I2C_CTRL_NAIE BSP_BIT32(2)
+#define I2C_CTRL_DRMIE BSP_BIT32(3)
+#define I2C_CTRL_DRSIE BSP_BIT32(4)
+#define I2C_CTRL_RFFIE BSP_BIT32(5)
+#define I2C_CTRL_RFDAIE BSP_BIT32(6)
+#define I2C_CTRL_TFFIO BSP_BIT32(7)
+#define I2C_CTRL_RESET BSP_BIT32(8)
+#define I2C_CTRL_SEVEN BSP_BIT32(9)
+#define I2C_CTRL_TFFSIE BSP_BIT32(10)
 
 /** @} */
 
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
index be0a154d22..48bde5958c 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h
@@ -178,16 +178,16 @@
  * @{
  */
 
-#define PWR_STOP BIT32(0)
-#define PWR_HIGHCORE_ALWAYS BIT32(1)
-#define PWR_NORMAL_RUN_MODE BIT32(2)
-#define PWR_SYSCLKEN_ALWAYS BIT32(3)
-#define PWR_SYSCLKEN_HIGH BIT32(4)
-#define PWR_HIGHCORE_HIGH BIT32(5)
-#define PWR_SDRAM_AUTO_REFRESH BIT32(7)
-#define PWR_UPDATE_EMCSREFREQ BIT32(8)
-#define PWR_EMCSREFREQ BIT32(9)
-#define PWR_HCLK_USES_PERIPH_CLK BIT32(10)
+#define PWR_STOP BSP_BIT32(0)
+#define PWR_HIGHCORE_ALWAYS BSP_BIT32(1)
+#define PWR_NORMAL_RUN_MODE BSP_BIT32(2)
+#define PWR_SYSCLKEN_ALWAYS BSP_BIT32(3)
+#define PWR_SYSCLKEN_HIGH BSP_BIT32(4)
+#define PWR_HIGHCORE_HIGH BSP_BIT32(5)
+#define PWR_SDRAM_AUTO_REFRESH BSP_BIT32(7)
+#define PWR_UPDATE_EMCSREFREQ BSP_BIT32(8)
+#define PWR_EMCSREFREQ BSP_BIT32(9)
+#define PWR_HCLK_USES_PERIPH_CLK BSP_BIT32(10)
 
 /** @} */
 
@@ -197,14 +197,14 @@
  * @{
  */
 
-#define HCLK_PLL_LOCK BIT32(0)
-#define HCLK_PLL_M(val) FIELD32(val, 1, 8)
-#define HCLK_PLL_N(val) FIELD32(val, 9, 10)
-#define HCLK_PLL_P(val) FIELD32(val, 11, 12)
-#define HCLK_PLL_FBD_FCLKOUT BIT32(13)
-#define HCLK_PLL_DIRECT BIT32(14)
-#define HCLK_PLL_BYPASS BIT32(15)
-#define HCLK_PLL_POWER BIT32(16)
+#define HCLK_PLL_LOCK BSP_BIT32(0)
+#define HCLK_PLL_M(val) BSP_FLD32(val, 1, 8)
+#define HCLK_PLL_N(val) BSP_FLD32(val, 9, 10)
+#define HCLK_PLL_P(val) BSP_FLD32(val, 11, 12)
+#define HCLK_PLL_FBD_FCLKOUT BSP_BIT32(13)
+#define HCLK_PLL_DIRECT BSP_BIT32(14)
+#define HCLK_PLL_BYPASS BSP_BIT32(15)
+#define HCLK_PLL_POWER BSP_BIT32(16)
 
 /** @} */
 
@@ -214,9 +214,9 @@
  * @{
  */
 
-#define HCLK_DIV_HCLK(val) FIELD32(val, 0, 1)
-#define HCLK_DIV_PERIPH_CLK(val) FIELD32(val, 2, 6)
-#define HCLK_DIV_DDRAM_CLK(val) FIELD32(val, 7, 8)
+#define HCLK_DIV_HCLK(val) BSP_FLD32(val, 0, 1)
+#define HCLK_DIV_PERIPH_CLK(val) BSP_FLD32(val, 2, 6)
+#define HCLK_DIV_DDRAM_CLK(val) BSP_FLD32(val, 7, 8)
 
 /** @} */
 
diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h b/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
index c5849103d0..b783e08736 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
+++ b/c/src/lib/libbsp/arm/lpc32xx/include/nand-mlc.h
@@ -91,12 +91,12 @@ extern "C" {
  * @{
  */
 
-#define FLASHCLK_IRQ_MLC BIT32(5)
-#define FLASHCLK_MLC_DMA_RNB BIT32(4)
-#define FLASHCLK_MLC_DMA_INT BIT32(3)
-#define FLASHCLK_SELECT_SLC BIT32(2)
-#define FLASHCLK_MLC_CLK_ENABLE BIT32(1)
-#define FLASHCLK_SLC_CLK_ENABLE BIT32(0)
+#define FLASHCLK_IRQ_MLC BSP_BIT32(5)
+#define FLASHCLK_MLC_DMA_RNB BSP_BIT32(4)
+#define FLASHCLK_MLC_DMA_INT BSP_BIT32(3)
+#define FLASHCLK_SELECT_SLC BSP_BIT32(2)
+#define FLASHCLK_MLC_CLK_ENABLE BSP_BIT32(1)
+#define FLASHCLK_SLC_CLK_ENABLE BSP_BIT32(0)
 
 /** @} */
 
@@ -106,13 +106,13 @@ extern "C" {
  * @{
  */
 
-#define MLC_TIME_WR_LOW(val) FIELD32(val, 0, 3)
-#define MLC_TIME_WR_HIGH(val) FIELD32(val, 4, 7)
-#define MLC_TIME_RD_LOW(val) FIELD32(val, 8, 11)
-#define MLC_TIME_RD_HIGH(val) FIELD32(val, 12, 15)
-#define MLC_TIME_NAND_TA(val) FIELD32(val, 16, 18)
-#define MLC_TIME_BUSY_DELAY(val) FIELD32(val, 19, 23)
-#define MLC_TIME_TCEA_DELAY(val) FIELD32(val, 24, 25)
+#define MLC_TIME_WR_LOW(val) BSP_FLD32(val, 0, 3)
+#define MLC_TIME_WR_HIGH(val) BSP_FLD32(val, 4, 7)
+#define MLC_TIME_RD_LOW(val) BSP_FLD32(val, 8, 11)
+#define MLC_TIME_RD_HIGH(val) BSP_FLD32(val, 12, 15)
+#define MLC_TIME_NAND_TA(val) BSP_FLD32(val, 16, 18)
+#define MLC_TIME_BUSY_DELAY(val) BSP_FLD32(val, 19, 23)
+#define MLC_TIME_TCEA_DELAY(val) BSP_FLD32(val, 24, 25)
 
 /** @} */
 
@@ -132,11 +132,11 @@ extern "C" {
  * @{
  */
 
-#define MLC_ISR_DECODER_FAILURE BIT32(6)
-#define MLC_ISR_ERRORS_DETECTED BIT32(3)
-#define MLC_ISR_ECC_READY BIT32(2)
-#define MLC_ISR_CONTROLLER_READY BIT32(1)
-#define MLC_ISR_NAND_READY BIT32(0)
+#define MLC_ISR_DECODER_FAILURE BSP_BIT32(6)
+#define MLC_ISR_ERRORS_DETECTED BSP_BIT32(3)
+#define MLC_ISR_ECC_READY BSP_BIT32(2)
+#define MLC_ISR_CONTROLLER_READY BSP_BIT32(1)
+#define MLC_ISR_NAND_READY BSP_BIT32(0)
 
 /** @} */
 
@@ -146,10 +146,10 @@ extern "C" {
  * @{
  */
 
-#define MLC_ICR_SOFT_WRITE_PROT BIT32(3)
-#define MLC_ICR_LARGE_PAGES BIT32(2)
-#define MLC_ICR_ADDR_WORD_COUNT_4_5 BIT32(1)
-#define MLC_ICR_IO_BUS_16 BIT32(0)
+#define MLC_ICR_SOFT_WRITE_PROT BSP_BIT32(3)
+#define MLC_ICR_LARGE_PAGES BSP_BIT32(2)
+#define MLC_ICR_ADDR_WORD_COUNT_4_5 BSP_BIT32(1)
+#define MLC_ICR_IO_BUS_16 BSP_BIT32(0)
 
 /** @} */
 
@@ -159,7 +159,7 @@ extern "C" {
  * @{
  */
 
-#define MLC_ECC_AUTO_ENC_PROGRAM BIT32(8)
+#define MLC_ECC_AUTO_ENC_PROGRAM BSP_BIT32(8)
 
 /** @} */