2010-06-23 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* make/custom/lpc32xx_mzx_boot_int.cfg,
	startup/linkcmds.lpc32xx_mzx_boot_int: Removed files.
	* include/boot.h, include/emc.h, include/i2c.h, include/nand-mlc.h,
	make/custom/lpc32xx_mzx.cfg, make/custom/lpc32xx_mzx_stage_1.cfg,
	make/custom/lpc32xx_mzx_stage_2.cfg, misc/boot.c, misc/emc.c,
	misc/i2c.c, misc/nand-mlc.c, misc/nand-mlc-read-blocks.c,
	misc/nand-mlc-write-blocks.c, misc/restart.c,
	startup/linkcmds.lpc32xx, startup/linkcmds.lpc32xx_mzx,
	startup/linkcmds.lpc32xx_mzx_stage_1,
	startup/linkcmds.lpc32xx_mzx_stage_2: New files.
	* configure.ac, Makefile.am, preinstall.am: Reflect changes above.
	* include/bsp.h, include/lpc32xx.h, irq/irq.c, rtc/rtc-config.c,
	startup/bspstart.c, startup/bspstarthooks.c,
	startup/linkcmds.lpc32xx_phycore: Changes throughout.

1 files changed, 27 insertions, 46 deletions

diff --git a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
index 4ea1c1cc1c..c0f3bb8dba 100644
--- a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
+++ b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c
@@ -42,21 +42,6 @@ typedef union {
   uint32_t fields_table [LPC32XX_IRQ_MODULE_COUNT];
 } lpc32xx_irq_fields;
 
-typedef struct {
-  uint32_t er;
-  uint32_t rsr;
-  uint32_t sr;
-  uint32_t apr;
-  uint32_t atr;
-  uint32_t itr;
-} lpc32xx_irq_controller;
-
-static volatile lpc32xx_irq_controller *const lpc32xx_mic = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_MIC;
-
-static volatile lpc32xx_irq_controller *const lpc32xx_sic_1 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_1;
-
-static volatile lpc32xx_irq_controller *const lpc32xx_sic_2 = (volatile lpc32xx_irq_controller *) LPC32XX_BASE_SIC_2;
-
 static uint8_t lpc32xx_irq_priority_table [LPC32XX_IRQ_COUNT];
 
 static lpc32xx_irq_fields lpc32xx_irq_priority_masks [LPC32XX_IRQ_PRIORITY_COUNT];
@@ -80,8 +65,8 @@ static inline bool lpc32xx_irq_priority_is_valid(unsigned priority)
 #define LPC32XX_IRQ_BIT_OPS_FOR_REG_DEFINE \
   LPC32XX_IRQ_BIT_OPS_DEFINE; \
   unsigned module_offset = module << 14; \
-  volatile uint32_t *reg =  \
-    (volatile uint32_t *) (LPC32XX_BASE_MIC + module_offset + register_offset)
+  volatile uint32_t *reg = (volatile uint32_t *) \
+    ((volatile char *) &lpc32xx.mic + module_offset + register_offset)
 
 #define LPC32XX_IRQ_OFFSET_ER 0U
 #define LPC32XX_IRQ_OFFSET_RSR 4U
@@ -234,10 +219,10 @@ lpc32xx_irq_activation_type lpc32xx_irq_get_activation_type(rtems_vector_number
 
 void bsp_interrupt_dispatch(void)
 {
-  uint32_t status = lpc32xx_mic->sr & LPC32XX_MIC_STATUS_MASK;
-  uint32_t er_mic = lpc32xx_mic->er;
-  uint32_t er_sic_1 = lpc32xx_sic_1->er;
-  uint32_t er_sic_2 = lpc32xx_sic_2->er;
+  uint32_t status = lpc32xx.mic.sr & LPC32XX_MIC_STATUS_MASK;
+  uint32_t er_mic = lpc32xx.mic.er;
+  uint32_t er_sic_1 = lpc32xx.sic_1.er;
+  uint32_t er_sic_2 = lpc32xx.sic_2.er;
   uint32_t psr = 0;
   lpc32xx_irq_fields *masks = NULL;
   rtems_vector_number vector = 0;
@@ -246,11 +231,11 @@ void bsp_interrupt_dispatch(void)
   if (status != 0) {
     vector = lpc32xx_irq_get_index(status);
   } else {
-    status = lpc32xx_sic_1->sr;
+    status = lpc32xx.sic_1.sr;
     if (status != 0) {
       vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_1;
     } else {
-      status = lpc32xx_sic_2->sr;
+      status = lpc32xx.sic_2.sr;
       if (status != 0) {
         vector = lpc32xx_irq_get_index(status) + LPC32XX_IRQ_MODULE_SIC_2;
       } else {
@@ -263,9 +248,9 @@ void bsp_interrupt_dispatch(void)
 
   masks = &lpc32xx_irq_priority_masks [priority];
 
-  lpc32xx_mic->er = er_mic & masks->field.mic;
-  lpc32xx_sic_1->er = er_sic_1 & masks->field.sic_1;
-  lpc32xx_sic_2->er = er_sic_2 & masks->field.sic_2;
+  lpc32xx.mic.er = er_mic & masks->field.mic;
+  lpc32xx.sic_1.er = er_sic_1 & masks->field.sic_1;
+  lpc32xx.sic_2.er = er_sic_2 & masks->field.sic_2;
 
   psr = arm_status_irq_enable();
 
@@ -273,9 +258,9 @@ void bsp_interrupt_dispatch(void)
 
   arm_status_restore(psr);
 
-  lpc32xx_mic->er = er_mic & lpc32xx_irq_enable.field.mic;
-  lpc32xx_sic_1->er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
-  lpc32xx_sic_2->er = er_sic_2 & lpc32xx_irq_enable.field.sic_2;
+  lpc32xx.mic.er = er_mic & lpc32xx_irq_enable.field.mic;
+  lpc32xx.sic_1.er = er_sic_1 & lpc32xx_irq_enable.field.sic_1;
+  lpc32xx.sic_2.er = er_sic_2 & lpc32xx_irq_enable.field.sic_2;
 }
 
 rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector)
@@ -308,11 +293,7 @@ void lpc32xx_set_exception_handler(
 )
 {
   if ((unsigned) exception < MAX_EXCEPTIONS) {
-    #ifndef LPC32XX_DISABLE_MMU
-      uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS;
-    #else
-      uint32_t *table = (uint32_t *) bsp_section_start_begin + MAX_EXCEPTIONS;
-    #endif
+    uint32_t *table = (uint32_t *) bsp_vector_table_begin + MAX_EXCEPTIONS;
 
     table [exception] = (uint32_t) handler;
 
@@ -341,24 +322,24 @@ rtems_status_code bsp_interrupt_facility_initialize(void)
   lpc32xx_irq_enable.field.sic_2 = 0x0;
   lpc32xx_irq_enable.field.sic_1 = 0x0;
   lpc32xx_irq_enable.field.mic = 0xc0000003;
-  lpc32xx_sic_1->er = 0x0;
-  lpc32xx_sic_2->er = 0x0;
-  lpc32xx_mic->er = 0xc0000003;
+  lpc32xx.sic_1.er = 0x0;
+  lpc32xx.sic_2.er = 0x0;
+  lpc32xx.mic.er = 0xc0000003;
 
   /* Set interrupt types to IRQ */
-  lpc32xx_mic->itr = 0x0;
-  lpc32xx_sic_1->itr = 0x0;
-  lpc32xx_sic_2->itr = 0x0;
+  lpc32xx.mic.itr = 0x0;
+  lpc32xx.sic_1.itr = 0x0;
+  lpc32xx.sic_2.itr = 0x0;
 
   /* Set interrupt activation polarities */
-  lpc32xx_mic->apr = 0x3ff0efe0;
-  lpc32xx_sic_1->apr = 0xfbd27184;
-  lpc32xx_sic_2->apr = 0x801810c0;
+  lpc32xx.mic.apr = 0x3ff0efe0;
+  lpc32xx.sic_1.apr = 0xfbd27184;
+  lpc32xx.sic_2.apr = 0x801810c0;
 
   /* Set interrupt activation types */
-  lpc32xx_mic->atr = 0x0;
-  lpc32xx_sic_1->atr = 0x26000;
-  lpc32xx_sic_2->atr = 0x0;
+  lpc32xx.mic.atr = 0x0;
+  lpc32xx.sic_1.atr = 0x26000;
+  lpc32xx.sic_2.atr = 0x0;
 
   lpc32xx_set_exception_handler(ARM_EXCEPTION_IRQ, arm_exc_interrupt);