summaryrefslogtreecommitdiffstats
path: root/c/src/lib/libbsp/arm/lpc24xx/include
diff options
context:
space:
mode:
authorSebastian Huber <sebastian.huber@embedded-brains.de>2011-11-08 10:39:46 +0000
committerSebastian Huber <sebastian.huber@embedded-brains.de>2011-11-08 10:39:46 +0000
commit4a6cc2a4b35e2cb069cb273b7e098366c7bae059 (patch)
treeb08f1c8e32e76029b8442e1ab27e173a3565009b /c/src/lib/libbsp/arm/lpc24xx/include
parent2011-11-08 Sebastian Huber <sebastian.huber@embedded-brains.de> (diff)
downloadrtems-4a6cc2a4b35e2cb069cb273b7e098366c7bae059.tar.bz2
2011-11-08 Sebastian Huber <sebastian.huber@embedded-brains.de>
* include/lpc17xx.h: New file. * Makefile.am, preinstall.am: Reflect change above. Update due to API changes. * configure.ac, console/console-config.c, include/bsp.h, include/io.h, include/irq.h, include/lcd.h, include/lpc-clock-config.h, include/lpc24xx.h, include/start-config.h, irq/irq-dispatch.c, irq/irq.c, misc/bspidle.c, misc/io.c, misc/lcd.c, misc/restart.c, misc/system-clocks.c, ssp/ssp.c, startup/bspreset.c, startup/bspstart.c, startup/bspstarthooks.c, startup/start-config-emc-dynamic.c, startup/start-config-emc-static.c, startup/start-config-pinsel.c: Basic support for LPC17XX. New memory configurations for W9825G2JB75I, IS42S32800B, and SST39VF3201.
Diffstat (limited to 'c/src/lib/libbsp/arm/lpc24xx/include')
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/bsp.h30
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/io.h706
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/irq.h118
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/lcd.h22
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h4
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h187
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h324
-rw-r--r--c/src/lib/libbsp/arm/lpc24xx/include/start-config.h19
8 files changed, 1017 insertions, 393 deletions
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
index ca5e3b8411..c96406d6b0 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/bsp.h
@@ -7,15 +7,19 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems@embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
*/
#ifndef LIBBSP_ARM_LPC24XX_BSP_H
@@ -33,6 +37,10 @@ extern "C" {
#define BSP_FEATURE_IRQ_EXTENSION
+#define LPC24XX_PCLK (LPC24XX_CCLK / LPC24XX_PCLKDIV)
+
+#define LPC24XX_EMCCLK (LPC24XX_CCLK / LPC24XX_EMCCLKDIV)
+
#ifndef ASM
struct rtems_bsdnet_ifconfig;
@@ -87,7 +95,11 @@ int lpc_eth_attach_detach(
*/
void *bsp_idle_thread(uintptr_t ignored);
-#define BSP_CONSOLE_UART_BASE 0xe000c000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define BSP_CONSOLE_UART_BASE 0xe000c000
+#else
+ #define BSP_CONSOLE_UART_BASE 0x4000c000
+#endif
void bsp_restart(void *addr);
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/io.h b/c/src/lib/libbsp/arm/lpc24xx/include/io.h
index c424c54c7c..b40bfdde6b 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/io.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/io.h
@@ -47,14 +47,18 @@ extern "C" {
#define LPC24XX_IO_INDEX_BY_PORT(port, bit) (((port) << 5U) + (bit))
-#define LPC24XX_IO_PORT(index) (index >> 5U)
+#define LPC24XX_IO_PORT(index) ((index) >> 5U)
-#define LPC24XX_IO_PORT_BIT(index) (index & 0x1fU)
+#define LPC24XX_IO_PORT_BIT(index) ((index) & 0x1fU)
typedef enum {
- LPC24XX_MODULE_ACF = 0,
- LPC24XX_MODULE_ADC,
- LPC24XX_MODULE_BAT_RAM,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_ACF,
+ #endif
+ LPC24XX_MODULE_ADC,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_BAT_RAM,
+ #endif
LPC24XX_MODULE_CAN_0,
LPC24XX_MODULE_CAN_1,
LPC24XX_MODULE_DAC,
@@ -72,7 +76,9 @@ typedef enum {
LPC24XX_MODULE_PWM_0,
LPC24XX_MODULE_PWM_1,
LPC24XX_MODULE_RTC,
- LPC24XX_MODULE_SPI,
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_SPI,
+ #endif
LPC24XX_MODULE_SSP_0,
LPC24XX_MODULE_SSP_1,
LPC24XX_MODULE_SYSCON,
@@ -84,16 +90,16 @@ typedef enum {
LPC24XX_MODULE_UART_1,
LPC24XX_MODULE_UART_2,
LPC24XX_MODULE_UART_3,
- LPC24XX_MODULE_USB,
- LPC24XX_MODULE_WDT
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LPC24XX_MODULE_WDT,
+ #endif
+ LPC24XX_MODULE_USB
} lpc24xx_module;
-#define LPC24XX_MODULE_FIRST LPC24XX_MODULE_ACF
-
-#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_WDT + 1)
+#define LPC24XX_MODULE_COUNT (LPC24XX_MODULE_USB + 1)
typedef enum {
- LPC24XX_MODULE_PCLK_DEFAULT = 0x0U,
+ LPC24XX_MODULE_PCLK_DEFAULT = 0x4U,
LPC24XX_MODULE_CCLK = 0x1U,
LPC24XX_MODULE_CCLK_2 = 0x2U,
LPC24XX_MODULE_CCLK_4 = 0x0U,
@@ -105,16 +111,13 @@ typedef enum {
typedef enum {
LPC24XX_GPIO_DEFAULT = 0x0U,
- LPC24XX_GPIO_RESISTOR_DEFAULT = 0x0U,
+ LPC24XX_GPIO_RESISTOR_PULL_UP = 0x0U,
LPC24XX_GPIO_RESISTOR_NONE = 0x1U,
- LPC24XX_GPIO_RESISTOR_PULL_UP = 0x2U,
- LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x3U,
+ LPC24XX_GPIO_RESISTOR_PULL_DOWN = 0x2U,
LPC24XX_GPIO_INPUT = 0x0U,
- LPC24XX_GPIO_OUTPUT = 0x8U
+ LPC24XX_GPIO_OUTPUT = 0x8000U
} lpc24xx_gpio_settings;
-#define LPC24XX_GPIO_RESISTOR_MASK 0x3U
-
rtems_status_code lpc24xx_module_enable(
lpc24xx_module module,
lpc24xx_module_clock clock
@@ -174,7 +177,7 @@ typedef enum {
/**
* @brief Sets the pin function.
*/
- LPC24XX_PIN_SET_FUNCTION = 0,
+ LPC24XX_PIN_SET_FUNCTION,
/**
* @brief Checks if all pins are configured with the specified function.
@@ -195,23 +198,37 @@ typedef enum {
typedef union {
struct {
uint16_t port : 3;
- uint16_t index_begin : 5;
- uint16_t index_last : 5;
+ uint16_t port_bit : 5;
uint16_t function : 3;
+ uint16_t type : 4;
+ uint16_t range : 1;
} fields;
uint16_t value;
} lpc24xx_pin_range;
-#define LPC24XX_PIN_FUNCTION_00 0x0
-#define LPC24XX_PIN_FUNCTION_01 0x1
-#define LPC24XX_PIN_FUNCTION_10 0x2
-#define LPC24XX_PIN_FUNCTION_11 0x3
-
-#define LPC24XX_PIN(p, i, f) { { p, i, i, f } }
-
-#define LPC24XX_PIN_RANGE(p, i, j, f) { { p, i, j, f } }
+typedef enum {
+ LPC24XX_PIN_FUNCTION_00,
+ LPC24XX_PIN_FUNCTION_01,
+ LPC24XX_PIN_FUNCTION_10,
+ LPC24XX_PIN_FUNCTION_11
+} lpc24xx_pin_function;
-#define LPC24XX_PIN_TERMINAL { { 0x3, 0x1f, 0x1f, 0x3 } }
+typedef enum {
+ LPC17XX_PIN_TYPE_DEFAULT,
+ LPC17XX_PIN_TYPE_ADC,
+ LPC17XX_PIN_TYPE_DAC,
+ LPC17XX_PIN_TYPE_I2C,
+ LPC17XX_PIN_TYPE_I2C_FAST_PLUS
+} lpc17xx_pin_type;
+
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_PIN(p, i, f0, f1) { { p, i, f0, 0, 0 } }
+ #define LPC24XX_PIN_WITH_TYPE(p, i, f0, f1, t) { { p, i, f0, t, 0 } }
+ #define LPC24XX_PIN_RANGE(p, i, j, f0, f1) \
+ { { p, i, f0, 0, 0 } }, { { p, j, f0, 0, 1 } }
+#endif
+
+#define LPC24XX_PIN_TERMINAL { { 0x7, 0x1f, 0x7, 0xf, 0x1 } }
/**
* @brief Performs the @a action with the @a pins
@@ -256,21 +273,49 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_ADC_CHANNEL_0 \
- LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 23, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_1 \
- LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 24, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_2 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 25, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_3 \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_4 \
- LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(1, 30, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_5 \
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(1, 31, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_6 \
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 12, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
#define LPC24XX_PIN_ADC_CHANNEL_7 \
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 13, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_ADC)
+
+/** @} */
+
+/**
+ * @name CAN 0 Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_CAN_0_RD \
+ LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_CAN_0_TD \
+ LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name CAN 1 Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_CAN_1_RD \
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_10, 2)
+
+#define LPC24XX_PIN_CAN_1_TD \
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -281,7 +326,7 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_DAC \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 26, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_DAC)
/** @} */
@@ -292,16 +337,146 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_ETHERNET_MII \
- LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 0, 17, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_0 \
- LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 0, 1, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_1 \
- LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_2 \
- LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 8, 10, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_ETHERNET_RMII_3 \
- LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_RANGE(1, 14, 17, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name External Interrupt Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_EINT_0 \
+ LPC24XX_PIN(2, 10, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_1 \
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_2 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EINT_3 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 1)
+
+/** @} */
+
+/**
+ * @name External Memory Controller (EMC) Pins
+ *
+ * @{
+ */
+
+#define LPC24XX_PIN_EMC_CS_0 \
+ LPC24XX_PIN(4, 30, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_1 \
+ LPC24XX_PIN(4, 31, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_2 \
+ LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CS_3 \
+ LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_DYCS_0 \
+ LPC24XX_PIN(2, 20, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_1 \
+ LPC24XX_PIN(2, 21, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_2 \
+ LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DYCS_3 \
+ LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_OE \
+ LPC24XX_PIN(4, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_WE \
+ LPC24XX_PIN(4, 25, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CAS \
+ LPC24XX_PIN(2, 16, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_RAS \
+ LPC24XX_PIN(2, 17, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_CLK_0 \
+ LPC24XX_PIN(2, 18, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CLK_1 \
+ LPC24XX_PIN(2, 19, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_CKE_0 \
+ LPC24XX_PIN(2, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_1 \
+ LPC24XX_PIN(2, 25, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_2 \
+ LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_CKE_3 \
+ LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_DQM_0 \
+ LPC24XX_PIN(2, 28, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_1 \
+ LPC24XX_PIN(2, 29, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_2 \
+ LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_DQM_3 \
+ LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_BLS0 \
+ LPC24XX_PIN(4, 26, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS1 \
+ LPC24XX_PIN(4, 27, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS2 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_BLS3 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_D_0_15 \
+ LPC24XX_PIN_RANGE(3, 0, 15, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_D_15_31 \
+ LPC24XX_PIN_RANGE(3, 15, 31, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_D_0_31 \
+ LPC24XX_PIN_RANGE(3, 0, 31, LPC24XX_PIN_FUNCTION_01, 1)
+
+#define LPC24XX_PIN_EMC_A_0_12 \
+ LPC24XX_PIN_RANGE(4, 0, 12, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_13 \
+ LPC24XX_PIN_RANGE(4, 0, 13, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_14 \
+ LPC24XX_PIN_RANGE(4, 0, 14, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_15 \
+ LPC24XX_PIN_RANGE(4, 0, 15, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_16 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN(4, 16, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_17 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 17, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_18 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 18, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_19 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 19, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_20 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 20, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_21 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 21, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_22 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 22, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_23 \
+ LPC24XX_PIN_EMC_A_0_15, \
+ LPC24XX_PIN_RANGE(4, 16, 23, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_24 \
+ LPC24XX_PIN_EMC_A_0_23, \
+ LPC24XX_PIN(5, 24, LPC24XX_PIN_FUNCTION_01, 1)
+#define LPC24XX_PIN_EMC_A_0_25 \
+ LPC24XX_PIN_EMC_A_0_23, \
+ LPC24XX_PIN_RANGE(5, 24, 25, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -312,9 +487,9 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_I2C_0_SDA \
- LPC24XX_PIN(0, 27, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 27, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_0_SCL \
- LPC24XX_PIN(0, 28, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN_WITH_TYPE(0, 28, LPC24XX_PIN_FUNCTION_01, 1, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -325,18 +500,18 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_I2C_1_SDA_P0_0 \
- LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 0, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SDA_P0_19 \
- LPC24XX_PIN(0, 19, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 19, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SDA_P2_14 \
- LPC24XX_PIN(2, 14, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 14, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
-#define LPC24XX_PIN_I2C_1_SCL_P0_20 \
- LPC24XX_PIN(0, 20, LPC24XX_PIN_FUNCTION_11)
#define LPC24XX_PIN_I2C_1_SCL_P0_1 \
- LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(0, 1, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
+#define LPC24XX_PIN_I2C_1_SCL_P0_20 \
+ LPC24XX_PIN_WITH_TYPE(0, 20, LPC24XX_PIN_FUNCTION_11, 3, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_1_SCL_P2_15 \
- LPC24XX_PIN(2, 15, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 15, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -347,18 +522,18 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_I2C_2_SDA_P0_10 \
- LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 10, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SDA_P2_30 \
- LPC24XX_PIN(2, 30, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN_WITH_TYPE(2, 30, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SDA_P4_20 \
- LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(4, 20, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
-#define LPC24XX_PIN_I2C_2_SCL_P2_31 \
- LPC24XX_PIN(2, 31, LPC24XX_PIN_FUNCTION_11)
#define LPC24XX_PIN_I2C_2_SCL_P0_11 \
- LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(0, 11, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
+#define LPC24XX_PIN_I2C_2_SCL_P2_31 \
+ LPC24XX_PIN_WITH_TYPE(2, 31, LPC24XX_PIN_FUNCTION_11, 2, LPC17XX_PIN_TYPE_I2C)
#define LPC24XX_PIN_I2C_2_SCL_P4_21 \
- LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN_WITH_TYPE(4, 21, LPC24XX_PIN_FUNCTION_10, 2, LPC17XX_PIN_TYPE_I2C)
/** @} */
@@ -369,34 +544,34 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_I2S_RX_CLK_P0_4 \
- LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_CLK_P0_23 \
- LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 23, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_RX_WS_P0_5 \
- LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_WS_P0_24 \
- LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 24, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_RX_SDA_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_RX_SDA_P0_25 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_I2S_TX_CLK_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_CLK_P2_11 \
- LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_I2S_TX_WS_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_WS_P2_12 \
- LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_I2S_TX_SDA_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_I2S_TX_SDA_P2_13 \
- LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -407,68 +582,114 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_LCD_PWR \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_LE \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_DCLK \
- LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_FP \
- LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_ENAB_M \
- LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_LP \
- LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_11, 7)
#define LPC24XX_PIN_LCD_CLKIN \
- LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01)
-
-#define LPC24XX_PIN_LCD_VD_P0_4 \
- LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_5 \
- LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_22 \
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_25 \
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_26 \
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_27 \
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_28 \
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P1_29 \
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P2_6 \
- LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_7 \
- LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_8 \
- LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_9 \
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_LCD_VD_P2_12 \
- LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P2_13 \
- LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01)
-#define LPC24XX_PIN_LCD_VD_P4_28 \
- LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10)
-#define LPC24XX_PIN_LCD_VD_P4_29 \
- LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 11, LPC24XX_PIN_FUNCTION_01, 7)
+
+#define LPC24XX_PIN_LCD_VD_0_P0_4 \
+ LPC24XX_PIN(0, 4, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_0_P2_6 \
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_1_P0_5 \
+ LPC24XX_PIN(0, 5, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_1_P2_7 \
+ LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_2_P2_8 \
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_2_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 7)
+#define LPC24XX_PIN_LCD_VD_3_P2_9 \
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 6)
+#define LPC24XX_PIN_LCD_VD_3_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 5)
+#define LPC24XX_PIN_LCD_VD_3_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 7)
+#define LPC24XX_PIN_LCD_VD_4_P2_6 \
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_4_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 4)
+#define LPC24XX_PIN_LCD_VD_5_P2_7 \
+ LPC24XX_PIN(2, 7, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_5_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 5)
+#define LPC24XX_PIN_LCD_VD_6_P1_20 \
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_6_P2_8 \
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_6_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 5)
+#define LPC24XX_PIN_LCD_VD_7_P1_21 \
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_7_P2_9 \
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_11, 7)
+#define LPC24XX_PIN_LCD_VD_7_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 5)
+#define LPC24XX_PIN_LCD_VD_8_P0_6 \
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_8_P1_22 \
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_8_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_9_P0_7 \
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_9_P1_23 \
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_9_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_10_P1_20 \
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_10_P1_24 \
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_10_P4_28 \
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_10, 6)
+#define LPC24XX_PIN_LCD_VD_11_P1_21 \
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_11_P1_25 \
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_11_P4_29 \
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_10, 6)
+#define LPC24XX_PIN_LCD_VD_12_P1_22 \
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_12_P1_26 \
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_13_P1_23 \
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_13_P1_27 \
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_14_P1_24 \
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_14_P1_28 \
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_15_P1_25 \
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_15_P1_29 \
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 6)
+#define LPC24XX_PIN_LCD_VD_16_P0_8 \
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_17_P0_9 \
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_18_P2_12 \
+ LPC24XX_PIN(2, 12, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_19_P2_13 \
+ LPC24XX_PIN(2, 13, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_20_P1_26 \
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_21_P1_27 \
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_22_P1_28 \
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 7)
+#define LPC24XX_PIN_LCD_VD_23_P1_29 \
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 7)
/** @} */
@@ -479,39 +700,39 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_PWM_0_CHANNEL_1_P1_2 \
- LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 2, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_1_P3_16 \
- LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_2_P1_3 \
- LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 3, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_2_P3_17 \
- LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_3_P1_5 \
- LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 5, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_3_P3_18 \
- LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_4_P1_6 \
- LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 6, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_4_P3_19 \
- LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 19, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_5_P1_7 \
- LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 7, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_5_P3_20 \
- LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 20, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CHANNEL_6_P1_11 \
- LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 11, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CHANNEL_6_P3_21 \
- LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 21, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_0_CAPTURE_0_P1_12 \
- LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 12, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_PWM_0_CAPTURE_0_P3_22 \
- LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(3, 22, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -522,73 +743,56 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P1_18 \
- LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P2_0 \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_1_P3_24 \
- LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 24, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P2_1 \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_2_P3_25 \
- LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 25, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P2_2 \
- LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 2, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_3_P3_26 \
- LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 26, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P2_3 \
- LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 3, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_4_P3_27 \
- LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 27, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P2_4 \
- LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 4, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_5_P3_28 \
- LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 28, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P1_26 \
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P2_5 \
- LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 5, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CHANNEL_6_P3_29 \
- LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11)
+ LPC24XX_PIN(3, 29, LPC24XX_PIN_FUNCTIO9_11, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P1_28 \
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P2_7 \
- LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 6, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_PWM_1_CAPTURE_0_P3_23 \
- LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 23, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_PWM_1_CAPTURE_1_P1_29 \
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10)
-
-/** @} */
-
-/**
- * @name SPI Pins
- *
- * @{
- */
-
-#define LPC24XX_PIN_SPI_SCK \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_SSEL \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_MISO \
- LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_11)
-#define LPC24XX_PIN_SPI_MOSI \
- LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -599,32 +803,32 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_SSP_0_SCK_P0_15 \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_SCK_P1_20 \
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_SCK_P2_22 \
- LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 22, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_SSEL_P0_16 \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_SSEL_P1_21 \
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_0_SSEL_P2_23 \
- LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 23, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_MISO_P0_17 \
- LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 17, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_MISO_P1_23 \
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_MISO_P2_26 \
- LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 26, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_0_MOSI_P0_18 \
- LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 18, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_0_MOSI_P1_24 \
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_11, 5)
#define LPC24XX_PIN_SSP_0_MOSI_P2_27 \
- LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(2, 27, LPC24XX_PIN_FUNCTION_11, 2)
/** @} */
@@ -635,32 +839,32 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_SSP_1_SCK_P0_6 \
- LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SCK_P0_12 \
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SCK_P4_20 \
- LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 20, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_SSEL_P0_7 \
- LPC24XX_PIN(0, 7, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 6, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_SSEL_P0_13 \
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_SSP_1_SSEL_P4_21 \
- LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 21, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_MISO_P0_8 \
- LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 8, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MISO_P0_14 \
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MISO_P4_22 \
- LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_SSP_1_MOSI_P0_9 \
- LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 9, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MOSI_P1_31 \
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_SSP_1_MOSI_P4_23 \
- LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -671,10 +875,10 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_UART_0_TXD \
- LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 2, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_0_RXD \
- LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 3, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -685,18 +889,18 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_UART_1_TXD_P0_15 \
- LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 15, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_1_TXD_P2_0 \
- LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 0, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_1_TXD_P3_16 \
- LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 16, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_1_RXD_P0_16 \
- LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 16, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_1_RXD_P2_1 \
- LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 1, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_1_RXD_P3_17 \
- LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(3, 17, LPC24XX_PIN_FUNCTION_11, 3)
/** @} */
@@ -707,18 +911,18 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_UART_2_TXD_P0_10 \
- LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 10, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_2_TXD_P2_8 \
- LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 8, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_TXD_P4_22 \
- LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(4, 22, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_RXD_P0_11 \
- LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 11, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_UART_2_RXD_P2_9 \
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_2_RXD_P4_23 \
- LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(4, 23, LPC24XX_PIN_FUNCTION_10, 2)
/** @} */
@@ -729,18 +933,18 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_UART_3_TXD_P0_0 \
- LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 0, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_3_TXD_P0_25 \
- LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 25, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_3_TXD_P4_28 \
- LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 28, LPC24XX_PIN_FUNCTION_11, 2)
#define LPC24XX_PIN_UART_3_RXD_P0_1 \
- LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 1, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_UART_3_RXD_P0_25 \
- LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(0, 26, LPC24XX_PIN_FUNCTION_11, 3)
#define LPC24XX_PIN_UART_3_RXD_P4_29 \
- LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11)
+ LPC24XX_PIN(4, 29, LPC24XX_PIN_FUNCTION_11, 2)
/** @} */
@@ -751,43 +955,43 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_USB_D_PLUS_1\
- LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 29, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_D_MINUS_1\
- LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 30, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_UP_LED_1\
- LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 18, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_TX_E_1\
- LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PPWR_1\
- LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 19, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_TX_DP_1\
- LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 20, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_TX_DM_1\
- LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 21, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_RCV_1\
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PWRD_1\
- LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 22, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_RX_DP_1\
- LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 23, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_RX_DM_1\
- LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 24, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_LS_1\
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_HSTEN_1\
- LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 25, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_SSPND_1\
- LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 26, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_INT_1\
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_OVRCR_1\
- LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(1, 27, LPC24XX_PIN_FUNCTION_10, 2)
#define LPC24XX_PIN_USB_SCL_1\
- LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 28, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_SDA_1\
- LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 29, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_CONNECT_1\
- LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(2, 9, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
@@ -798,19 +1002,19 @@ rtems_status_code lpc24xx_pin_config(
*/
#define LPC24XX_PIN_USB_PPWR_2\
- LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 12, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_UP_LED_2\
- LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 13, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_HSTEN_2\
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_CONNECT_2\
- LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(0, 14, LPC24XX_PIN_FUNCTION_01, 3)
#define LPC24XX_PIN_USB_D_PLUS_2\
- LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_10)
+ LPC24XX_PIN(0, 31, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_PWRD_2\
- LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 30, LPC24XX_PIN_FUNCTION_01, 1)
#define LPC24XX_PIN_USB_OVRCR_2\
- LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01)
+ LPC24XX_PIN(1, 31, LPC24XX_PIN_FUNCTION_01, 1)
/** @} */
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h b/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
index 6b9ddf8a37..d82946d35d 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/irq.h
@@ -7,25 +7,27 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems@embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
*/
#ifndef LIBBSP_ARM_LPC24XX_IRQ_H
#define LIBBSP_ARM_LPC24XX_IRQ_H
#ifndef ASM
-
-#include <rtems.h>
-#include <rtems/irq.h>
-#include <rtems/irq-extension.h>
+ #include <rtems.h>
+ #include <rtems/irq.h>
+ #include <rtems/irq-extension.h>
+#endif
/**
* @addtogroup bsp_interrupt
@@ -33,61 +35,63 @@
* @{
*/
-#define LPC24XX_IRQ_WDT 0
-#define LPC24XX_IRQ_SOFTWARE 1
-#define LPC24XX_IRQ_ARM_CORE_0 2
-#define LPC24XX_IRQ_ARM_CORE_1 3
-#define LPC24XX_IRQ_TIMER_0 4
-#define LPC24XX_IRQ_TIMER_1 5
-#define LPC24XX_IRQ_UART_0 6
-#define LPC24XX_IRQ_UART_1 7
-#define LPC24XX_IRQ_PWM 8
-#define LPC24XX_IRQ_I2C_0 9
-#define LPC24XX_IRQ_SPI_SSP_0 10
-#define LPC24XX_IRQ_SSP_1 11
-#define LPC24XX_IRQ_PLL 12
-#define LPC24XX_IRQ_RTC 13
-#define LPC24XX_IRQ_EINT_0 14
-#define LPC24XX_IRQ_EINT_1 15
-#define LPC24XX_IRQ_EINT_2 16
-#define LPC24XX_IRQ_EINT_3 17
-#define LPC24XX_IRQ_ADC_0 18
-#define LPC24XX_IRQ_I2C_1 19
-#define LPC24XX_IRQ_BOD 20
-#define LPC24XX_IRQ_ETHERNET 21
-#define LPC24XX_IRQ_USB 22
-#define LPC24XX_IRQ_CAN 23
-#define LPC24XX_IRQ_SD_MMC 24
-#define LPC24XX_IRQ_DMA 25
-#define LPC24XX_IRQ_TIMER_2 26
-#define LPC24XX_IRQ_TIMER_3 27
-#define LPC24XX_IRQ_UART_2 28
-#define LPC24XX_IRQ_UART_3 29
-#define LPC24XX_IRQ_I2C_2 30
-#define LPC24XX_IRQ_I2S 31
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_IRQ_WDT 0
+ #define LPC24XX_IRQ_SOFTWARE 1
+ #define LPC24XX_IRQ_ARM_CORE_0 2
+ #define LPC24XX_IRQ_ARM_CORE_1 3
+ #define LPC24XX_IRQ_TIMER_0 4
+ #define LPC24XX_IRQ_TIMER_1 5
+ #define LPC24XX_IRQ_UART_0 6
+ #define LPC24XX_IRQ_UART_1 7
+ #define LPC24XX_IRQ_PWM 8
+ #define LPC24XX_IRQ_I2C_0 9
+ #define LPC24XX_IRQ_SPI_SSP_0 10
+ #define LPC24XX_IRQ_SSP_1 11
+ #define LPC24XX_IRQ_PLL 12
+ #define LPC24XX_IRQ_RTC 13
+ #define LPC24XX_IRQ_EINT_0 14
+ #define LPC24XX_IRQ_EINT_1 15
+ #define LPC24XX_IRQ_EINT_2 16
+ #define LPC24XX_IRQ_EINT_3 17
+ #define LPC24XX_IRQ_ADC_0 18
+ #define LPC24XX_IRQ_I2C_1 19
+ #define LPC24XX_IRQ_BOD 20
+ #define LPC24XX_IRQ_ETHERNET 21
+ #define LPC24XX_IRQ_USB 22
+ #define LPC24XX_IRQ_CAN 23
+ #define LPC24XX_IRQ_SD_MMC 24
+ #define LPC24XX_IRQ_DMA 25
+ #define LPC24XX_IRQ_TIMER_2 26
+ #define LPC24XX_IRQ_TIMER_3 27
+ #define LPC24XX_IRQ_UART_2 28
+ #define LPC24XX_IRQ_UART_3 29
+ #define LPC24XX_IRQ_I2C_2 30
+ #define LPC24XX_IRQ_I2S 31
+
+ #define BSP_INTERRUPT_VECTOR_MAX 31
+#endif
-#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0U
-#define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15U
-#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1U)
+#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15
+#endif
+#define LPC24XX_IRQ_PRIORITY_COUNT (LPC24XX_IRQ_PRIORITY_VALUE_MAX + 1)
#define LPC24XX_IRQ_PRIORITY_HIGHEST LPC24XX_IRQ_PRIORITY_VALUE_MIN
#define LPC24XX_IRQ_PRIORITY_LOWEST LPC24XX_IRQ_PRIORITY_VALUE_MAX
-/**
- * @brief Minimum vector number.
- */
-#define BSP_INTERRUPT_VECTOR_MIN LPC24XX_IRQ_WDT
-
-/**
- * @brief Maximum vector number.
- */
-#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
+#ifndef ASM
void lpc24xx_irq_set_priority(rtems_vector_number vector, unsigned priority);
unsigned lpc24xx_irq_get_priority(rtems_vector_number vector);
-/** @} */
+void bsp_interrupt_dispatch(void);
#endif /* ASM */
+/** @} */
+
#endif /* LIBBSP_ARM_LPC24XX_IRQ_H */
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h b/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h
index bbe5e847b3..08f5a4476a 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lcd.h
@@ -7,7 +7,7 @@
*/
/*
- * Copyright (c) 2010 embedded brains GmbH. All rights reserved.
+ * Copyright (c) 2010-2011 embedded brains GmbH. All rights reserved.
*
* embedded brains GmbH
* Obere Lagerstr. 30
@@ -42,15 +42,17 @@ extern "C" {
*/
typedef enum {
- LCD_MODE_STN_4_BIT = 0,
- LCD_MODE_STN_8_BIT,
- LCD_MODE_STN_DUAL_PANEL_4_BIT,
- LCD_MODE_STN_DUAL_PANEL_8_BIT,
- LCD_MODE_TFT_12_BIT_4_4_4,
- LCD_MODE_TFT_16_BIT_5_6_5,
- LCD_MODE_TFT_16_BIT_1_5_5_5,
- LCD_MODE_TFT_24_BIT,
- LCD_MODE_DISABLED
+ #ifdef ARM_MULTILIB_ARCH_V4
+ LCD_MODE_STN_4_BIT = 0,
+ LCD_MODE_STN_8_BIT,
+ LCD_MODE_STN_DUAL_PANEL_4_BIT,
+ LCD_MODE_STN_DUAL_PANEL_8_BIT,
+ LCD_MODE_TFT_12_BIT_4_4_4,
+ LCD_MODE_TFT_16_BIT_5_6_5,
+ LCD_MODE_TFT_16_BIT_1_5_5_5,
+ LCD_MODE_TFT_24_BIT,
+ LCD_MODE_DISABLED
+ #endif
} lpc24xx_lcd_mode;
/**
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h
index d8aff6c4c8..d6f67f091e 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc-clock-config.h
@@ -35,10 +35,10 @@ extern "C" {
#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR
-#define LPC_CLOCK_REFERENCE LPC24XX_CCLK
+#define LPC_CLOCK_REFERENCE LPC24XX_PCLK
#define LPC_CLOCK_MODULE_ENABLE() \
- lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_CCLK)
+ lpc24xx_module_enable(LPC24XX_MODULE_TIMER_0, LPC24XX_MODULE_PCLK_DEFAULT)
#ifdef __cplusplus
}
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h
new file mode 100644
index 0000000000..4f57813280
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc17xx.h
@@ -0,0 +1,187 @@
+/**
+ * @file
+ *
+ * @ingroup lpc24xx_regs
+ *
+ * @brief Register definitions.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
+ */
+
+#ifndef LPC17XX_REGS_H
+#define LPC17XX_REGS_H
+
+#include <bsp/utility.h>
+
+#define LPC17XX_BASE 0x00
+
+typedef struct {
+#define LPC17XX_PLL_CON_PLLE BSP_BIT32(0)
+#define LPC17XX_PLL_SEL_MSEL(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_PLL_SEL_MSEL_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_PLL_SEL_MSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_PLL_SEL_PSEL(val) BSP_FLD32(val, 5, 6)
+#define LPC17XX_PLL_SEL_PSEL_GET(reg) BSP_FLD32GET(reg, 5, 6)
+#define LPC17XX_PLL_SEL_PSEL_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
+#define LPC17XX_PLL_STAT_PLLE BSP_BIT32(8)
+#define LPC17XX_PLL_STAT_PLOCK BSP_BIT32(10)
+ uint32_t con;
+ uint32_t cfg;
+ uint32_t stat;
+ uint32_t feed;
+} lpc17xx_pll;
+
+typedef struct {
+ uint32_t flashcfg;
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM(val) BSP_FLD32(val, 12, 15)
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define LPC17XX_SCB_FLASHCFG_FLASHTIM_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+ uint32_t reserved_04 [15];
+ uint32_t memmap;
+#define LPC17XX_SCB_MEMMAP_MAP BSP_BIT32(0)
+ uint32_t reserved_44 [15];
+ lpc17xx_pll pll_0;
+ uint32_t reserved_90 [4];
+ lpc17xx_pll pll_1;
+ uint32_t reserved_b0 [4];
+ uint32_t pcon;
+#define LPC17XX_SCB_PCON_PM0 BSP_BIT32(0)
+#define LPC17XX_SCB_PCON_PM1 BSP_BIT32(1)
+#define LPC17XX_SCB_PCON_BODRPM BSP_BIT32(2)
+#define LPC17XX_SCB_PCON_BOGD BSP_BIT32(3)
+#define LPC17XX_SCB_PCON_BORD BSP_BIT32(4)
+#define LPC17XX_SCB_PCON_SMFLAG BSP_BIT32(8)
+#define LPC17XX_SCB_PCON_DSFLAG BSP_BIT32(9)
+#define LPC17XX_SCB_PCON_PDFLAG BSP_BIT32(10)
+#define LPC17XX_SCB_PCON_DPDFLAG BSP_BIT32(11)
+ uint32_t pconp;
+#define LPC17XX_SCB_PCONP_LCD BSP_BIT32(0)
+#define LPC17XX_SCB_PCONP_TIMER_0 BSP_BIT32(1)
+#define LPC17XX_SCB_PCONP_TIMER_1 BSP_BIT32(2)
+#define LPC17XX_SCB_PCONP_UART_0 BSP_BIT32(3)
+#define LPC17XX_SCB_PCONP_UART_1 BSP_BIT32(4)
+#define LPC17XX_SCB_PCONP_PWM_0 BSP_BIT32(5)
+#define LPC17XX_SCB_PCONP_PWM_1 BSP_BIT32(6)
+#define LPC17XX_SCB_PCONP_I2C_0 BSP_BIT32(7)
+#define LPC17XX_SCB_PCONP_UART_4 BSP_BIT32(8)
+#define LPC17XX_SCB_PCONP_RTC BSP_BIT32(9)
+#define LPC17XX_SCB_PCONP_SSP_1 BSP_BIT32(10)
+#define LPC17XX_SCB_PCONP_EMC BSP_BIT32(11)
+#define LPC17XX_SCB_PCONP_ADC BSP_BIT32(12)
+#define LPC17XX_SCB_PCONP_CAN_0 BSP_BIT32(13)
+#define LPC17XX_SCB_PCONP_CAN_1 BSP_BIT32(14)
+#define LPC17XX_SCB_PCONP_GPIO BSP_BIT32(15)
+#define LPC17XX_SCB_PCONP_QEI BSP_BIT32(17)
+#define LPC17XX_SCB_PCONP_I2C_1 BSP_BIT32(18)
+#define LPC17XX_SCB_PCONP_SSP_2 BSP_BIT32(19)
+#define LPC17XX_SCB_PCONP_SSP_0 BSP_BIT32(20)
+#define LPC17XX_SCB_PCONP_TIMER_2 BSP_BIT32(21)
+#define LPC17XX_SCB_PCONP_TIMER_3 BSP_BIT32(22)
+#define LPC17XX_SCB_PCONP_UART_2 BSP_BIT32(23)
+#define LPC17XX_SCB_PCONP_UART_3 BSP_BIT32(24)
+#define LPC17XX_SCB_PCONP_I2C_2 BSP_BIT32(25)
+#define LPC17XX_SCB_PCONP_I2S BSP_BIT32(26)
+#define LPC17XX_SCB_PCONP_SDC BSP_BIT32(27)
+#define LPC17XX_SCB_PCONP_GPDMA BSP_BIT32(28)
+#define LPC17XX_SCB_PCONP_ENET BSP_BIT32(29)
+#define LPC17XX_SCB_PCONP_USB BSP_BIT32(30)
+#define LPC17XX_SCB_PCONP_MCPWM BSP_BIT32(31)
+ uint32_t reserved_c8 [14];
+ uint32_t emcclksel;
+#define LPC17XX_SCB_EMCCLKSEL_EMCDIV BSP_BIT32(0)
+ uint32_t cclksel;
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_CCLKSEL_CCLKSEL BSP_BIT32(8)
+ uint32_t usbclksel;
+#define LPC17XX_SCB_USBCLKSEL_USBDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL(val) BSP_FLD32(val, 8, 9)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL_GET(reg) BSP_FLD32GET(reg, 8, 9)
+#define LPC17XX_SCB_USBCLKSEL_USBSEL_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
+ uint32_t clksrcsel;
+#define LPC17XX_SCB_CLKSRCSEL_CLKSRC BSP_BIT32(0)
+ uint32_t reserved_110 [12];
+ uint32_t extint;
+ uint32_t reserved_144;
+ uint32_t extmode;
+ uint32_t extpolar;
+ uint32_t reserved_150 [12];
+ uint32_t rsid;
+ uint32_t reserved_184 [7];
+ uint32_t scs;
+#define LPC17XX_SCB_SCS_EMC_SHIFT_CTL BSP_BIT32(0)
+#define LPC17XX_SCB_SCS_EMC_RESET_DIS BSP_BIT32(1)
+#define LPC17XX_SCB_SCS_EMC_BURST_CTL BSP_BIT32(2)
+#define LPC17XX_SCB_SCS_MCIPWR BSP_BIT32(3)
+#define LPC17XX_SCB_SCS_OSC_RANGE_SEL BSP_BIT32(4)
+#define LPC17XX_SCB_SCS_OSC_ENABLE BSP_BIT32(5)
+#define LPC17XX_SCB_SCS_OSC_STATUS BSP_BIT32(6)
+ uint32_t reserved_1a4;
+ uint32_t pclksel;
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_PCLKSEL_PCLKDIV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+ uint32_t reserved_1ac;
+ uint32_t pboost;
+#define LPC17XX_SCB_PBOOST_BOOST BSP_BIT32(0)
+ uint32_t reserved_1b4 [5];
+ uint32_t clkoutcfg;
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL(val) BSP_FLD32(val, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_GET(reg) BSP_FLD32GET(reg, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 0)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV(val) BSP_FLD32(val, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_GET(reg) BSP_FLD32GET(reg, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUTDIV_SET(reg, val) BSP_FLD32SET(reg, val, 7, 4)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32(8)
+#define LPC17XX_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32(9)
+ uint32_t rstcon0;
+ uint32_t rstcon1;
+ uint32_t reserved_1d4 [2];
+ uint32_t emcdlyctl;
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY(val) BSP_FLD32(val, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_CMDDLY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY(val) BSP_FLD32(val, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_GET(reg) BSP_FLD32GET(reg, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_FBCLKDLY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 12)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY(val) BSP_FLD32(val, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_GET(reg) BSP_FLD32GET(reg, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT0DLY_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY(val) BSP_FLD32(val, 24, 28)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_GET(reg) BSP_FLD32GET(reg, 24, 28)
+#define LPC17XX_SCB_EMCDLYCTL_CLKOUT1DLY_SET(reg, val) BSP_FLD32SET(reg, val, 24, 28)
+ uint32_t emccal;
+#define LPC17XX_SCB_EMCCAL_CALVALUE(val) BSP_FLD32(val, 0, 7)
+#define LPC17XX_SCB_EMCCAL_CALVALUE_GET(reg) BSP_FLD32GET(reg, 0, 7)
+#define LPC17XX_SCB_EMCCAL_CALVALUE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
+#define LPC17XX_SCB_EMCCAL_START BSP_BIT32(14)
+#define LPC17XX_SCB_EMCCAL_DONE BSP_BIT32(15)
+} lpc17xx_scb;
+
+#define LPC17XX_SCB (*(volatile lpc17xx_scb *) (LPC17XX_BASE + 0x400fc000))
+
+typedef struct {
+ uint32_t reserved_00 [268693504];
+ lpc17xx_scb scb;
+} lpc17xx;
+
+#define LPC17XX (*(volatile lpc17xx *) (LPC17XX_BASE))
+
+#endif /* LPC17XX_REGS_H */
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
index bf2d3accce..2839790fb8 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h
@@ -7,24 +7,32 @@
*/
/*
- * Copyright (c) 2008
- * Embedded Brains GmbH
- * Obere Lagerstr. 30
- * D-82178 Puchheim
- * Germany
- * rtems@embedded-brains.de
+ * Copyright (c) 2008-2011 embedded brains GmbH. All rights reserved.
*
- * The license and distribution terms for this file may be found in the file
- * LICENSE in this distribution or at http://www.rtems.com/license/LICENSE.
+ * embedded brains GmbH
+ * Obere Lagerstr. 30
+ * 82178 Puchheim
+ * Germany
+ * <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * $Id$
*/
#ifndef LIBBSP_ARM_LPC24XX_LPC24XX_H
#define LIBBSP_ARM_LPC24XX_LPC24XX_H
-#include <stdint.h>
+#include <rtems/score/cpu.h>
#include <bsp/utility.h>
#include <bsp/lpc-i2s.h>
+#ifdef ARM_MULTILIB_ARCH_V7M
+ #include <bsp/lpc17xx.h>
+#endif
+
/**
* @defgroup lpc24xx_regs Register Definitions
*
@@ -35,6 +43,8 @@
* @{
*/
+#ifdef ARM_MULTILIB_ARCH_V4
+
/* Vectored Interrupt Controller (VIC) */
#define VIC_BASE_ADDR 0xFFFFF000
#define VICIRQStatus (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x000))
@@ -118,9 +128,17 @@
#define VICVectAddr (*(volatile uint32_t *) (VIC_BASE_ADDR + 0xF00))
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* Pin Connect Block */
-#define PINSEL_BASE_ADDR 0xE002C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PINSEL_BASE_ADDR 0xE002C000
+#else
+ #define PINSEL_BASE_ADDR 0x4002C000
+#endif
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
#define PINSEL0 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x00))
#define PINSEL1 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x04))
#define PINSEL2 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x08))
@@ -145,8 +163,14 @@
#define PINMODE8 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x60))
#define PINMODE9 (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x64))
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* General Purpose Input/Output (GPIO) */
-#define GPIO_BASE_ADDR 0xE0028000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define GPIO_BASE_ADDR 0xE0028000
+#else
+ #define GPIO_BASE_ADDR 0x40028000
+#endif
#define IOPIN0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x00))
#define IOSET0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x04))
#define IODIR0 (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x08))
@@ -171,11 +195,19 @@
#define IO_INT_STAT (*(volatile uint32_t *) (GPIO_BASE_ADDR + 0x80))
+#ifdef ARM_MULTILIB_ARCH_V4
+
#define PARTCFG_BASE_ADDR 0x3FFF8000
#define PARTCFG (*(volatile uint32_t *) (PARTCFG_BASE_ADDR + 0x00))
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* Fast I/O setup */
-#define FIO_BASE_ADDR 0x3FFFC000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define FIO_BASE_ADDR 0x3FFFC000
+#else
+ #define FIO_BASE_ADDR 0x20098000
+#endif
#define FIO0DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x00))
#define FIO0MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x10))
#define FIO0PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x14))
@@ -206,6 +238,16 @@
#define FIO4SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x98))
#define FIO4CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0x9C))
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+#define FIO5DIR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xa0))
+#define FIO5MASK (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb0))
+#define FIO5PIN (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb4))
+#define FIO5SET (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xb8))
+#define FIO5CLR (*(volatile uint32_t *) (FIO_BASE_ADDR + 0xbC))
+
+#endif /* ARM_MULTILIB_ARCH_V7M */
+
/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
#define FIO0DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x00))
#define FIO1DIR0 (*(volatile uint8_t *) (FIO_BASE_ADDR + 0x20))
@@ -387,6 +429,7 @@
#define FIO3CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x7E))
#define FIO4CLRU (*(volatile uint16_t *) (FIO_BASE_ADDR + 0x9E))
+#ifdef ARM_MULTILIB_ARCH_V4
/* System Control Block(SCB) modules include Memory Accelerator Module,
Phase Locked Loop, VPB divider, Power Control, External Interrupt,
@@ -435,9 +478,14 @@ Reset, and Code Security/Debugging */
/* System Controls and Status */
#define SCS (*(volatile uint32_t *) (SCB_BASE_ADDR + 0x1A0))
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* External Memory Controller (EMC) */
-#define EMC_BASE_ADDR 0xFFE08000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define EMC_BASE_ADDR 0xFFE08000
+#else
+ #define EMC_BASE_ADDR 0x2009c000
+#endif
#define EMC_CTRL (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x000))
#define EMC_STAT (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x004))
#define EMC_CONFIG (*(volatile uint32_t *) (EMC_BASE_ADDR + 0x008))
@@ -508,7 +556,11 @@ Reset, and Code Security/Debugging */
/* Timer 0 */
-#define TMR0_BASE_ADDR 0xE0004000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR0_BASE_ADDR 0xE0004000
+#else
+ #define TMR0_BASE_ADDR 0x40004000
+#endif
#define T0IR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x00))
#define T0TCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x04))
#define T0TC (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x08))
@@ -528,7 +580,11 @@ Reset, and Code Security/Debugging */
#define T0CTCR (*(volatile uint32_t *) (TMR0_BASE_ADDR + 0x70))
/* Timer 1 */
-#define TMR1_BASE_ADDR 0xE0008000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR1_BASE_ADDR 0xE0008000
+#else
+ #define TMR1_BASE_ADDR 0x40008000
+#endif
#define T1IR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x00))
#define T1TCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x04))
#define T1TC (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x08))
@@ -548,7 +604,11 @@ Reset, and Code Security/Debugging */
#define T1CTCR (*(volatile uint32_t *) (TMR1_BASE_ADDR + 0x70))
/* Timer 2 */
-#define TMR2_BASE_ADDR 0xE0070000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR2_BASE_ADDR 0xE0070000
+#else
+ #define TMR2_BASE_ADDR 0x40090000
+#endif
#define T2IR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x00))
#define T2TCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x04))
#define T2TC (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x08))
@@ -568,7 +628,11 @@ Reset, and Code Security/Debugging */
#define T2CTCR (*(volatile uint32_t *) (TMR2_BASE_ADDR + 0x70))
/* Timer 3 */
-#define TMR3_BASE_ADDR 0xE0074000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define TMR3_BASE_ADDR 0xE0074000
+#else
+ #define TMR3_BASE_ADDR 0x40094000
+#endif
#define T3IR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x00))
#define T3TCR (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x04))
#define T3TC (*(volatile uint32_t *) (TMR3_BASE_ADDR + 0x08))
@@ -589,7 +653,11 @@ Reset, and Code Security/Debugging */
/* Pulse Width Modulator (PWM) */
-#define PWM0_BASE_ADDR 0xE0014000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PWM0_BASE_ADDR 0xE0014000
+#else
+ #define PWM0_BASE_ADDR 0x40014000
+#endif
#define PWM0IR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x00))
#define PWM0TCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x04))
#define PWM0TC (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x08))
@@ -613,7 +681,11 @@ Reset, and Code Security/Debugging */
#define PWM0LER (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x50))
#define PWM0CTCR (*(volatile uint32_t *) (PWM0_BASE_ADDR + 0x70))
-#define PWM1_BASE_ADDR 0xE0018000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define PWM1_BASE_ADDR 0xE0018000
+#else
+ #define PWM1_BASE_ADDR 0x40018000
+#endif
#define PWM1IR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x00))
#define PWM1TCR (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x04))
#define PWM1TC (*(volatile uint32_t *) (PWM1_BASE_ADDR + 0x08))
@@ -639,7 +711,11 @@ Reset, and Code Security/Debugging */
/* Universal Asynchronous Receiver Transmitter 0 (UART0) */
-#define UART0_BASE_ADDR 0xE000C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART0_BASE_ADDR 0xE000C000
+#else
+ #define UART0_BASE_ADDR 0x4000C000
+#endif
#define U0RBR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
#define U0THR (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
#define U0DLL (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x00))
@@ -656,7 +732,11 @@ Reset, and Code Security/Debugging */
#define U0TER (*(volatile uint32_t *) (UART0_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 1 (UART1) */
-#define UART1_BASE_ADDR 0xE0010000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART1_BASE_ADDR 0xE0010000
+#else
+ #define UART1_BASE_ADDR 0x40010000
+#endif
#define U1RBR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
#define U1THR (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
#define U1DLL (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x00))
@@ -674,7 +754,11 @@ Reset, and Code Security/Debugging */
#define U1TER (*(volatile uint32_t *) (UART1_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 2 (UART2) */
-#define UART2_BASE_ADDR 0xE0078000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART2_BASE_ADDR 0xE0078000
+#else
+ #define UART2_BASE_ADDR 0x40098000
+#endif
#define U2RBR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
#define U2THR (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
#define U2DLL (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x00))
@@ -691,7 +775,11 @@ Reset, and Code Security/Debugging */
#define U2TER (*(volatile uint32_t *) (UART2_BASE_ADDR + 0x30))
/* Universal Asynchronous Receiver Transmitter 3 (UART3) */
-#define UART3_BASE_ADDR 0xE007C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define UART3_BASE_ADDR 0xE007C000
+#else
+ #define UART3_BASE_ADDR 0x4009C000
+#endif
#define U3RBR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
#define U3THR (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
#define U3DLL (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x00))
@@ -708,7 +796,11 @@ Reset, and Code Security/Debugging */
#define U3TER (*(volatile uint32_t *) (UART3_BASE_ADDR + 0x30))
/* I2C Interface 0 */
-#define I2C0_BASE_ADDR 0xE001C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C0_BASE_ADDR 0xE001C000
+#else
+ #define I2C0_BASE_ADDR 0x4001C000
+#endif
#define I20CONSET (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x00))
#define I20STAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x04))
#define I20DAT (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x08))
@@ -718,7 +810,11 @@ Reset, and Code Security/Debugging */
#define I20CONCLR (*(volatile uint32_t *) (I2C0_BASE_ADDR + 0x18))
/* I2C Interface 1 */
-#define I2C1_BASE_ADDR 0xE005C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C1_BASE_ADDR 0xE005C000
+#else
+ #define I2C1_BASE_ADDR 0x4005C000
+#endif
#define I21CONSET (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x00))
#define I21STAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x04))
#define I21DAT (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x08))
@@ -728,7 +824,11 @@ Reset, and Code Security/Debugging */
#define I21CONCLR (*(volatile uint32_t *) (I2C1_BASE_ADDR + 0x18))
/* I2C Interface 2 */
-#define I2C2_BASE_ADDR 0xE0080000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2C2_BASE_ADDR 0xE0080000
+#else
+ #define I2C2_BASE_ADDR 0x400a0000
+#endif
#define I22CONSET (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x00))
#define I22STAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x04))
#define I22DAT (*(volatile uint32_t *) (I2C2_BASE_ADDR + 0x08))
@@ -746,7 +846,11 @@ Reset, and Code Security/Debugging */
#define S0SPINT (*(volatile uint32_t *) (SPI0_BASE_ADDR + 0x1C))
/* SSP0 Controller */
-#define SSP0_BASE_ADDR 0xE0068000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define SSP0_BASE_ADDR 0xE0068000
+#else
+ #define SSP0_BASE_ADDR 0x40088000
+#endif
#define SSP0CR0 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x00))
#define SSP0CR1 (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x04))
#define SSP0DR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x08))
@@ -759,7 +863,11 @@ Reset, and Code Security/Debugging */
#define SSP0DMACR (*(volatile uint32_t *) (SSP0_BASE_ADDR + 0x24))
/* SSP1 Controller */
-#define SSP1_BASE_ADDR 0xE0030000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define SSP1_BASE_ADDR 0xE0030000
+#else
+ #define SSP1_BASE_ADDR 0x40030000
+#endif
#define SSP1CR0 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x00))
#define SSP1CR1 (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x04))
#define SSP1DR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x08))
@@ -771,9 +879,29 @@ Reset, and Code Security/Debugging */
#define SSP1ICR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x20))
#define SSP1DMACR (*(volatile uint32_t *) (SSP1_BASE_ADDR + 0x24))
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+/* SSP2 Controller */
+#define SSP2_BASE_ADDR 0x400ac000
+#define SSP2CR0 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x00))
+#define SSP2CR1 (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x04))
+#define SSP2DR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x08))
+#define SSP2SR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x0C))
+#define SSP2CPSR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x10))
+#define SSP2IMSC (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x14))
+#define SSP2RIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x18))
+#define SSP2MIS (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x1C))
+#define SSP2ICR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x20))
+#define SSP2DMACR (*(volatile uint32_t *) (SSP2_BASE_ADDR + 0x24))
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
/* Real Time Clock */
-#define RTC_BASE_ADDR 0xE0024000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define RTC_BASE_ADDR 0xE0024000
+#else
+ #define RTC_BASE_ADDR 0x40024000
+#endif
#define RTC_ILR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x00))
#define RTC_CTC (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x04))
#define RTC_CCR (*(volatile uint32_t *) (RTC_BASE_ADDR + 0x08))
@@ -804,7 +932,11 @@ Reset, and Code Security/Debugging */
/* A/D Converter 0 (AD0) */
-#define AD0_BASE_ADDR 0xE0034000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define AD0_BASE_ADDR 0xE0034000
+#else
+ #define AD0_BASE_ADDR 0x40034000
+#endif
#define AD0CR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x00))
#define AD0GDR (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
#define AD0INTEN (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
@@ -821,12 +953,20 @@ Reset, and Code Security/Debugging */
/* D/A Converter */
-#define DAC_BASE_ADDR 0xE006C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define DAC_BASE_ADDR 0xE006C000
+#else
+ #define DAC_BASE_ADDR 0x4008C000
+#endif
#define DACR (*(volatile uint32_t *) (DAC_BASE_ADDR + 0x00))
/* Watchdog */
-#define WDG_BASE_ADDR 0xE0000000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define WDG_BASE_ADDR 0xE0000000
+#else
+ #define WDG_BASE_ADDR 0x40000000
+#endif
#define WDMOD (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x00))
#define WDTC (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x04))
#define WDFEED (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x08))
@@ -834,7 +974,11 @@ Reset, and Code Security/Debugging */
#define WDCLKSEL (*(volatile uint32_t *) (WDG_BASE_ADDR + 0x10))
/* CAN CONTROLLERS AND ACCEPTANCE FILTER */
-#define CAN_ACCEPT_BASE_ADDR 0xE003C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN_ACCEPT_BASE_ADDR 0xE003C000
+#else
+ #define CAN_ACCEPT_BASE_ADDR 0x4003C000
+#endif
#define CAN_AFMR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x00))
#define CAN_SFF_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x04))
#define CAN_SFF_GRP_SA (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x08))
@@ -844,12 +988,20 @@ Reset, and Code Security/Debugging */
#define CAN_LUT_ERR_ADR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x18))
#define CAN_LUT_ERR (*(volatile uint32_t *) (CAN_ACCEPT_BASE_ADDR + 0x1C))
-#define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN_CENTRAL_BASE_ADDR 0xE0040000
+#else
+ #define CAN_CENTRAL_BASE_ADDR 0x40040000
+#endif
#define CAN_TX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x00))
#define CAN_RX_SR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x04))
#define CAN_MSR (*(volatile uint32_t *) (CAN_CENTRAL_BASE_ADDR + 0x08))
-#define CAN1_BASE_ADDR 0xE0044000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN1_BASE_ADDR 0xE0044000
+#else
+ #define CAN1_BASE_ADDR 0x40044000
+#endif
#define CAN1MOD (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x00))
#define CAN1CMR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x04))
#define CAN1GSR (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x08))
@@ -876,7 +1028,11 @@ Reset, and Code Security/Debugging */
#define CAN1TDA3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x58))
#define CAN1TDB3 (*(volatile uint32_t *) (CAN1_BASE_ADDR + 0x5C))
-#define CAN2_BASE_ADDR 0xE0048000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define CAN2_BASE_ADDR 0xE0048000
+#else
+ #define CAN2_BASE_ADDR 0x40048000
+#endif
#define CAN2MOD (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x00))
#define CAN2CMR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x04))
#define CAN2GSR (*(volatile uint32_t *) (CAN2_BASE_ADDR + 0x08))
@@ -905,7 +1061,11 @@ Reset, and Code Security/Debugging */
/* MultiMedia Card Interface(MCI) Controller */
-#define MCI_BASE_ADDR 0xE008C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define MCI_BASE_ADDR 0xE008C000
+#else
+ #define MCI_BASE_ADDR 0x400c0000
+#endif
#define MCI_POWER (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x00))
#define MCI_CLOCK (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x04))
#define MCI_ARGUMENT (*(volatile uint32_t *) (MCI_BASE_ADDR + 0x08))
@@ -928,7 +1088,11 @@ Reset, and Code Security/Debugging */
/* I2S Interface Controller (I2S) */
-#define I2S_BASE_ADDR 0xE0088000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define I2S_BASE_ADDR 0xE0088000
+#else
+ #define I2S_BASE_ADDR 0x400a8000
+#endif
#define I2S_DAO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x00))
#define I2S_DAI (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x04))
#define I2S_TX_FIFO (*(volatile uint32_t *) (I2S_BASE_ADDR + 0x08))
@@ -942,7 +1106,11 @@ Reset, and Code Security/Debugging */
/* General-purpose DMA Controller */
-#define DMA_BASE_ADDR 0xFFE04000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define DMA_BASE_ADDR 0xFFE04000
+#else
+ #define DMA_BASE_ADDR 0x20080000
+#endif
#define GPDMA_INT_STAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x000))
#define GPDMA_INT_TCSTAT (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x004))
#define GPDMA_INT_TCCLR (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x008))
@@ -974,10 +1142,14 @@ Reset, and Code Security/Debugging */
#define GPDMA_CH1_CTRL (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x12C))
#define GPDMA_CH1_CFG (*(volatile uint32_t *) (DMA_BASE_ADDR + 0x130))
-
/* USB Controller */
-#define USB_INT_BASE_ADDR 0xE01FC1C0
-#define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USB_INT_BASE_ADDR 0xE01FC1C0
+ #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
+#else
+ #define USB_INT_BASE_ADDR 0x400fc1c0
+ #define USB_BASE_ADDR 0x2008c200
+#endif
#define USB_INT_STAT (*(volatile uint32_t *) (USB_INT_BASE_ADDR + 0x00))
@@ -1031,9 +1203,12 @@ Reset, and Code Security/Debugging */
#define SYS_ERR_INT_CLR (*(volatile uint32_t *) (USB_BASE_ADDR + 0xBC))
#define SYS_ERR_INT_SET (*(volatile uint32_t *) (USB_BASE_ADDR + 0xC0))
-
/* USB Host Controller */
-#define USBHC_BASE_ADDR 0xFFE0C000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBHC_BASE_ADDR 0xFFE0C000
+#else
+ #define USBHC_BASE_ADDR 0x2008c000
+#endif
#define HC_REVISION (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x00))
#define HC_CONTROL (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x04))
#define HC_CMD_STAT (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x08))
@@ -1059,7 +1234,11 @@ Reset, and Code Security/Debugging */
#define HC_RH_PORT_STAT2 (*(volatile uint32_t *) (USBHC_BASE_ADDR + 0x58))
/* USB OTG Controller */
-#define USBOTG_BASE_ADDR 0xFFE0C100
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_BASE_ADDR 0xFFE0C100
+#else
+ #define USBOTG_BASE_ADDR 0x2008c100
+#endif
#define OTG_INT_STAT (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x00))
#define OTG_INT_EN (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x04))
#define OTG_INT_SET (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x08))
@@ -1067,7 +1246,11 @@ Reset, and Code Security/Debugging */
#define OTG_STAT_CTRL (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x10))
#define OTG_TIMER (*(volatile uint32_t *) (USBOTG_BASE_ADDR + 0x14))
-#define USBOTG_I2C_BASE_ADDR 0xFFE0C300
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
+#else
+ #define USBOTG_I2C_BASE_ADDR 0x2008c300
+#endif
#define OTG_I2C_RX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
#define OTG_I2C_TX (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x00))
#define OTG_I2C_STS (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x04))
@@ -1075,13 +1258,20 @@ Reset, and Code Security/Debugging */
#define OTG_I2C_CLKHI (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x0C))
#define OTG_I2C_CLKLO (*(volatile uint32_t *) (USBOTG_I2C_BASE_ADDR + 0x10))
-#define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
+#else
+ #define USBOTG_CLK_BASE_ADDR 0x2008cff0
+#endif
#define OTG_CLK_CTRL (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x04))
#define OTG_CLK_STAT (*(volatile uint32_t *) (USBOTG_CLK_BASE_ADDR + 0x08))
-
/* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
-#define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
+#else
+ #define MAC_BASE_ADDR 0x20084000
+#endif
#define MAC_MAC1 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
#define MAC_MAC2 (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
#define MAC_IPGT (*(volatile uint32_t *) (MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
@@ -1138,7 +1328,11 @@ Reset, and Code Security/Debugging */
/* LCD Controller */
-#define LCD_BASE_ADDR 0xFFE10000
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LCD_BASE_ADDR 0xFFE10000
+#else
+ #define LCD_BASE_ADDR 0x20088000
+#endif
#define LCD_CFG (*(volatile uint32_t *) 0xE01FC1B8)
#define LCD_TIMH (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
#define LCD_TIMV (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
@@ -1937,6 +2131,28 @@ typedef struct {
/* IO */
+#ifdef ARM_MULTILIB_ARCH_V4
+ #define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
+ #define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
+#else
+ #define IOCON_FUNC(val) BSP_FLD32(val, 0, 2)
+ #define IOCON_FUNC_GET(reg) BSP_FLD32GET(reg, 0, 2)
+ #define IOCON_FUNC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+ #define IOCON_MODE(val) BSP_FLD32(val, 3, 4)
+ #define IOCON_MODE_GET(reg) BSP_FLD32GET(reg, 3, 4)
+ #define IOCON_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 3, 4)
+ #define IOCON_HYS BSP_BIT32(5)
+ #define IOCON_INV BSP_BIT32(6)
+ #define IOCON_ADMODE BSP_BIT32(7)
+ #define IOCON_FILTER BSP_BIT32(8)
+ #define IOCON_HS BSP_BIT32(8)
+ #define IOCON_SLEW BSP_BIT32(9)
+ #define IOCON_HIDRIVE BSP_BIT32(9)
+ #define IOCON_OD BSP_BIT32(10)
+ #define IOCON_DACEN BSP_BIT32(16)
+ #define LPC17XX_IOCON ((volatile uint32_t *) PINSEL_BASE_ADDR)
+#endif
+
typedef struct {
uint32_t dir;
uint32_t reserved [3];
@@ -1946,18 +2162,18 @@ typedef struct {
uint32_t clr;
} lpc24xx_fio;
-#define LPC24XX_PINSEL ((volatile uint32_t *) &PINSEL0)
-
-#define LPC24XX_PINMODE ((volatile uint32_t *) &PINMODE0)
-
#define LPC24XX_FIO ((volatile lpc24xx_fio *) FIO_BASE_ADDR)
+#ifdef ARM_MULTILIB_ARCH_V4
+
/* PCONP */
#define PCONP_GPDMA (1U << 29)
#define PCONP_ETHERNET (1U << 30)
#define PCONP_USB (1U << 31)
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
/* I2S */
static volatile lpc_i2s *const lpc24xx_i2s = (lpc_i2s *) I2S_BASE_ADDR;
diff --git a/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h b/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
index a7ba00f292..3002b59a89 100644
--- a/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
+++ b/c/src/lib/libbsp/arm/lpc24xx/include/start-config.h
@@ -26,6 +26,7 @@
#define LIBBSP_ARM_LPC24XX_START_CONFIG_H
#include <bsp.h>
+#include <bsp/io.h>
#include <bsp/start.h>
#include <bsp/lpc-emc.h>
@@ -47,6 +48,7 @@ typedef struct {
uint32_t txsr;
uint32_t trrd;
uint32_t tmrd;
+ uint32_t emcdlyctl;
} lpc24xx_emc_dynamic_config;
typedef struct {
@@ -70,25 +72,22 @@ typedef struct {
} config;
} lpc24xx_emc_static_chip_config;
-extern const BSP_START_DATA_SECTION uint32_t
- lpc24xx_start_config_pinsel_5_9 [];
+extern BSP_START_DATA_SECTION const lpc24xx_pin_range
+ lpc24xx_start_config_pinsel [];
-extern const BSP_START_DATA_SECTION size_t
- lpc24xx_start_config_pinsel_5_9_size;
-
-extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_config
lpc24xx_start_config_emc_dynamic [];
-extern const BSP_START_DATA_SECTION lpc24xx_emc_dynamic_chip_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_dynamic_chip_config
lpc24xx_start_config_emc_dynamic_chip [];
-extern const BSP_START_DATA_SECTION size_t
+extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_dynamic_chip_count;
-extern const BSP_START_DATA_SECTION lpc24xx_emc_static_chip_config
+extern BSP_START_DATA_SECTION const lpc24xx_emc_static_chip_config
lpc24xx_start_config_emc_static_chip [];
-extern const BSP_START_DATA_SECTION size_t
+extern BSP_START_DATA_SECTION const size_t
lpc24xx_start_config_emc_static_chip_count;
#ifdef __cplusplus
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-03 01:06:21 +0000