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| author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
| commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
| tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /c/src/lib/libbsp/arm/lpc176x | |
| parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
| download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 | |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'c/src/lib/libbsp/arm/lpc176x')
27 files changed, 10 insertions, 4456 deletions
diff --git a/c/src/lib/libbsp/arm/lpc176x/Makefile.am b/c/src/lib/libbsp/arm/lpc176x/Makefile.am index 4e2d98bfbf..634df1a609 100644 --- a/c/src/lib/libbsp/arm/lpc176x/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc176x/Makefile.am @@ -11,56 +11,13 @@ EXTRA_DIST = include $(top_srcdir)/../../../../automake/compile.am include $(top_srcdir)/../../bsp.am -include_bspdir = $(includedir)/bsp - -dist_project_lib_DATA = bsp_specs +dist_project_lib_DATA = startup/bsp_specs # ---------------------------- # ------ Headers # ---------------------------- -include_HEADERS = include/bsp.h - -nodist_include_HEADERS = include/bspopts.h - -nodist_include_bsp_HEADERS = ../../shared/include/bootcard.h - -include_bsp_HEADERS = -include_bsp_HEADERS += ../../shared/include/utility.h -include_bsp_HEADERS += ../../shared/include/irq-generic.h -include_bsp_HEADERS += ../../shared/include/irq-info.h -include_bsp_HEADERS += ../../shared/include/stackalloc.h -include_bsp_HEADERS += ../../shared/include/uart-output-char.h -include_bsp_HEADERS += ../shared/include/start.h -include_bsp_HEADERS += ../shared/lpc/include/lpc-timer.h -include_bsp_HEADERS += ../shared/lpc/include/lpc-i2s.h -include_bsp_HEADERS += ../shared/lpc/include/lpc-dma.h -include_bsp_HEADERS += ../shared/armv7m/include/armv7m-irq.h -include_bsp_HEADERS += include/dma.h -include_bsp_HEADERS += include/io-defs.h -include_bsp_HEADERS += include/io.h -include_bsp_HEADERS += include/common-types.h -include_bsp_HEADERS += include/gpio-defs.h -include_bsp_HEADERS += include/lpc-gpio.h -include_bsp_HEADERS += include/can.h -include_bsp_HEADERS += include/can-defs.h -include_bsp_HEADERS += include/pwmout.h -include_bsp_HEADERS += include/pwmout-defs.h -include_bsp_HEADERS += include/adc.h -include_bsp_HEADERS += include/adc-defs.h -include_bsp_HEADERS += include/timer-defs.h -include_bsp_HEADERS += include/timer.h -include_bsp_HEADERS += include/watchdog.h -include_bsp_HEADERS += include/watchdog-defs.h -include_bsp_HEADERS += include/irq.h -include_bsp_HEADERS += include/lpc176x.h -include_bsp_HEADERS += include/lpc-clock-config.h -include_bsp_HEADERS += include/system-clocks.h -include_bsp_HEADERS += include/mbed-pinmap.h - -include_HEADERS += include/tm27.h - # ---------------------------- # ------ Data @@ -70,12 +27,11 @@ EXTRA_DIST += ../shared/start/start.S start.$(OBJEXT): ../shared/start/start.S $(CPPASCOMPILE) -o $@ -c $< project_lib_DATA = start.$(OBJEXT) -project_lib_DATA += startup/linkcmds - -EXTRA_DIST += startup/linkcmds.lpc1768_mbed -EXTRA_DIST += startup/linkcmds.lpc1768_mbed_ahb_ram -EXTRA_DIST += startup/linkcmds.lpc1768_mbed_ahb_ram_eth +project_lib_DATA += linkcmds +dist_project_lib_DATA += startup/linkcmds.lpc1768_mbed +dist_project_lib_DATA += startup/linkcmds.lpc1768_mbed_ahb_ram +dist_project_lib_DATA += startup/linkcmds.lpc1768_mbed_ahb_ram_eth # ---------------------------- # ------ LibBSP @@ -84,7 +40,7 @@ EXTRA_DIST += startup/linkcmds.lpc1768_mbed_ahb_ram_eth noinst_LIBRARIES = libbsp.a libbsp_a_SOURCES = -libbsp_a_CPPFLAGS = +libbsp_a_CPPFLAGS = $(AM_CPPFLAGS) libbsp_a_LIBADD = # Shared @@ -172,5 +128,5 @@ libbsp_a_SOURCES += startup/bspstarthooks.c DISTCLEANFILES = include/bspopts.h -include $(srcdir)/preinstall.am include $(top_srcdir)/../../../../automake/local.am +include $(srcdir)/../../../../../../bsps/arm/lpc176x/headers.am diff --git a/c/src/lib/libbsp/arm/lpc176x/configure.ac b/c/src/lib/libbsp/arm/lpc176x/configure.ac index dae4322987..b64bef7463 100644 --- a/c/src/lib/libbsp/arm/lpc176x/configure.ac +++ b/c/src/lib/libbsp/arm/lpc176x/configure.ac @@ -10,6 +10,9 @@ AC_INIT([rtems-c-src-lib-libbsp-arm-lpc176x],[_RTEMS_VERSION], [https://devel.rtems.org/newticket]) AC_CONFIG_SRCDIR([make/custom/lpc1768_mbed_ahb_ram.cfg]) RTEMS_TOP(../../../../../..) +RTEMS_SOURCE_TOP +RTEMS_BUILD_TOP +RTEMS_BSP_LINKCMDS RTEMS_CANONICAL_TARGET_CPU AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) @@ -68,7 +71,6 @@ RTEMS_BSPOPTS_SET([LPC_DMA_CHANNEL_COUNT],[*],[2]) RTEMS_BSPOPTS_HELP([LPC_DMA_CHANNEL_COUNT],[DMA channel count]) RTEMS_BSP_CLEANUP_OPTIONS -RTEMS_BSP_LINKCMDS AC_CONFIG_FILES([Makefile]) AC_OUTPUT diff --git a/c/src/lib/libbsp/arm/lpc176x/include/adc-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/adc-defs.h deleted file mode 100755 index 3daca807b7..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/adc-defs.h +++ /dev/null @@ -1,96 +0,0 @@ -/** - * @file adc-defs.h - * - * @ingroup lpc176x - * - * @brief ADC library for the lpc176x bsp. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ -#ifndef LPC176X_ADC_DEFS_H -#define LPC176X_ADC_DEFS_H - -#include <bsp.h> -#include <bsp/io.h> -#include <bsp/lpc176x.h> -#include <bsp/adc.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief The ADC inputs of the board. - */ -typedef enum { - ADC_0, - ADC_1, - ADC_2, - ADC_3, - ADC_4, - ADC_5, - ADC_6, - ADC_7, - ADC_DEVICES_COUNT -} lpc176x_adc_number; - -#define MAX_ADC_CLK 13000000u - -#define ADC_RANGE 0xFFFu - -#define ADC_NUMBER_VALID( number ) ( ( (uint32_t) number ) < \ - ADC_DEVICES_COUNT ) - -#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) -#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) -#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) -#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) -#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) -#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) -#define ADC_CR_BURST BSP_BIT32( 16 ) -#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) -#define ADC_CR_PDN BSP_BIT32( 21 ) -#define ADC_CR_START_NOW BSP_BIT32( 24 ) -#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) -#define ADC_CR_EDGE BSP_BIT32( 27 ) - -#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 4, 15 ) -#define ADC_DR_OVERRUN BSP_BIT32( 30 ) -#define ADC_DR_DONE BSP_BIT32( 31 ) - -#define ADC_DATA_CONVERSION_DONE( val ) ( ( val & ADC_DR_DONE ) != 0u ) - -/** - * @brief The ADC low-level device. - */ -typedef struct { - volatile uint32_t ADCR; - volatile uint32_t ADGDR; - volatile uint32_t RESERVED0; - volatile uint32_t ADINTEN; - volatile uint32_t ADDR[ ADC_DEVICES_COUNT ]; - volatile uint32_t ADSTAT; - volatile uint32_t ADTRM; -} lpc176x_adc_device; - -/** - * @brief Represents the pin and function for each ADC input. - */ -typedef struct { - uint32_t pin_number; - lpc176x_pin_function pin_function; -} lpc176x_adc_pin_map; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/c/src/lib/libbsp/arm/lpc176x/include/adc.h b/c/src/lib/libbsp/arm/lpc176x/include/adc.h deleted file mode 100755 index 34df8b7efd..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/adc.h +++ /dev/null @@ -1,60 +0,0 @@ -/** - * @file adc.h - * - * @ingroup lpc176x - * - * @brief ADC library for the lpc176x bsp. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LPC176X_ADC_H -#define LPC176X_ADC_H - -#include <bsp.h> -#include <bsp/common-types.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Opens and initializes the ADC device. - * - * @param adc_number The ADC pin number to be initialized. - * @return RTEMS_SUCCESSFUL if the initialization was succesful, - * RTEMS_INVALID_NUMBER if wrong parameter. - */ -rtems_status_code adc_open( const lpc176x_pin_number pin_number ); - -/** - * @brief Closes the ADC device. - * - * @return RTEMS_SUCCESSFUL if closed succesfully. - */ -rtems_status_code adc_close( void ); - -/** - * @brief Starts a conversion, waits for it to finish and reads the value. - * - * @param pin_number The port to read the value. - * @param result The read result. (In a percentage between 0.0f and 1.0f). - */ -rtems_status_code adc_read( - const lpc176x_pin_number pin_number , - float *const result -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/c/src/lib/libbsp/arm/lpc176x/include/bsp.h b/c/src/lib/libbsp/arm/lpc176x/include/bsp.h deleted file mode 100644 index e81e1cd53c..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/bsp.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x - * - * @brief Global BSP definitions. - */ - -/* - * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_BSP_H -#define LIBBSP_ARM_LPC176X_BSP_H - -#include <bspopts.h> - -#define LPC176X_PCLK ( LPC176X_CCLK / LPC176X_PCLKDIV ) -#define LPC176X_MPU_REGION_COUNT 8u - -#define BSP_FEATURE_IRQ_EXTENSION -#define BSP_ARMV7M_IRQ_PRIORITY_DEFAULT ( 29u << 3u ) -#define BSP_ARMV7M_SYSTICK_PRIORITY ( 30u << 3u ) -#define BSP_ARMV7M_SYSTICK_FREQUENCY LPC176X_CCLK - -#ifndef ASM - -#include <rtems.h> -#include <bsp/default-initial-extension.h> - -/** Define operation count for Tests */ -#define OPERATION_COUNT 4 - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -struct rtems_bsdnet_ifconfig; - -/** - * @defgroup lpc176x LPC176X Support - * - * @ingroup bsp_arm - * - * @brief LPC176X support package. - * - * @{ - */ - -/** - * @brief Optimized idle task. - * - * This idle task sets the power mode to idle. This causes the processor - * clock to be stopped, while on-chip peripherals remain active. - * Any enabled interrupt from a peripheral or an external interrupt source - * will cause the processor to resume execution. - * - * To enable the idle task use the following in the system configuration: - * - * @code - * #include <bsp.h> - * - * #define CONFIGURE_INIT - * - * #define CONFIGURE_IDLE_TASK_BODY bsp_idle_thread - * - * #include <confdefs.h> - * @endcode - */ -void*bsp_idle_thread( uintptr_t ignored ); - -#define BSP_CONSOLE_UART_BASE 0x4000C000U - -/** - * @brief Restarts the bsp with "addr" address - * @param addr Address used to restart the bsp - */ -void bsp_restart( const void *addr ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ASM */ - -#endif /* LIBBSP_ARM_LPC176X_BSP_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/can-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/can-defs.h deleted file mode 100755 index 4db229eb1c..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/can-defs.h +++ /dev/null @@ -1,183 +0,0 @@ -/** - * @file can-defs.h - * - * @ingroup lpc176x - * - * @brief CAN controller for the lpc176x controller. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LPC176X_TIMER_DEFS_H -#define LPC176X_TIMER_DEFS_H - -#include <bsp/common-types.h> -#include <bsp/can.h> - -/* CAN ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0x4003C000 - -#define CAN_DRIVER_IS_MINOR_VALID( minor ) ( minor < CAN_DEVICES_NUMBER ) -#define CAN_DEFAULT_BAUD_RATE 1000000u -#define CAN_DEFAULT_INTERRUPT_CONFIGURATION 0 - -#define MAX_NUMBER_OF_CAN_BITS 25u -#define MIN_NUMBER_OF_CAN_BITS 4u -#define CAN_BRP_EXTRA_BIT 1u -#define CAN_TSEG_EXTRA_BITS 3u -#define MAX_TSEG1_TSEG2_BITS 22u - -#define CAN_GSR_RBS_MASK 1u -#define CAN_CMR_RRB_MASK 4u - -#define CAN_MAXIMUM_DATA_SIZE 8u -#define CAN10_MAXIMUM_ID 0x7FFu - -/** - * @brief The Time segments of a CAN bit. - */ -typedef enum { - CAN_TSEG1, - CAN_TSEG2, - CAN_NUMBER_OF_TSEG, -} can_tseg_number; - -#define CAN_BTR_TSEG1_SHIFT 16u -#define CAN_BTR_TSEG2_SHIFT 20u -#define CAN_BTR_SJW_SHIFT 14u -#define CAN_BTR_BRP_SHIFT 0u - -#define CAN_BTR_TSEG1_MASK 0x000F0000U -#define CAN_BTR_TSEG2_MASK 0x00700000U -#define CAN_BTR_SJW_MASK 0x0000C000U -#define CAN_BTR_BRP_MASK 0x000003FFU - -#define WRONG_BTR_VALUE 0xFFFFFFFF - -/** - * @brief The transmit buffers of the CAN device. - */ -typedef enum { - CAN_TRANSMIT1, - CAN_TRANSMIT2, - CAN_TRANSMIT3, - CAN_NUMBER_OF_TRANSMIT_BUFFERS -} can_transmit_number; - -/** - * @brief The CAN status and control masks to send a message - * for each transmit buffer. - */ -typedef struct { - uint32_t can_status_mask; - uint32_t not_cc_cmr_value; -} can_transmit_info; - -/** @brief Represents the CAN controller registers.*/ -typedef struct { - volatile uint32_t MOD; - volatile uint32_t CMR; - volatile uint32_t GSR; - volatile uint32_t ICR; - volatile uint32_t IER; - volatile uint32_t BTR; - volatile uint32_t EWL; - volatile uint32_t SR; - volatile registers_can_message receive; - volatile registers_can_message transmit[ CAN_NUMBER_OF_TRANSMIT_BUFFERS ]; -} can_device; - -/** - * @brief A TX or RX pin for each CAN device . - */ -typedef enum { - CAN_TX_PIN, - CAN_RX_PIN, - NUMBER_OF_CAN_PINS -} can_pin_number; - -/** - * @brief A driver entry for each low level device. - */ -typedef struct { - can_device *const device; - const lpc176x_module module; - const uint32_t pconp_pin; - const uint32_t pins[ NUMBER_OF_CAN_PINS ]; - const lpc176x_pin_function pinfunction; -} can_driver_entry; - -/** @brief Represents the CAN centralized registers. */ -typedef struct { - volatile uint32_t TX_SR; - volatile uint32_t RX_SR; - volatile uint32_t MSR; -} can_central; - -/** @brief Represents the acceptance filter registers. */ -typedef struct { - volatile uint32_t AFMR; - volatile uint32_t SFF_SA; - volatile uint32_t SFF_GRP_SA; - volatile uint32_t EFF_SA; - volatile uint32_t EFF_GRP_SA; - volatile uint32_t EOT; - volatile uint32_t LUT_ERR_ADR; - volatile uint32_t LUT_ERR; - volatile uint32_t FCANIE; - volatile uint32_t FCANIC0; - volatile uint32_t FCANIC1; -} can_acceptance_filter; - -/** - * @brief The possible CAN formats for a message. - */ -typedef enum { - CANStandard = 0, - CANExtended = 1, - CANAny = 2 -} can_format; - -/** - * @brief The types of message. - */ -typedef enum { - CANData = 0, - CANRemote = 1 -} can_type; - -#define CAN_INTERRUPT_TYPE_MASK 0x1ffu - -/** - * @brief The vector with all the callbacks for the CAN isr. - */ -typedef lpc176x_can_isr lpc176x_can_isr_vector[ CAN_IRQ_NUMBER ]; - -#define CAN_MOD_RM 0x00000001U - -#define CAN_ACCF_AFMR_ACCOF 0x00000001U -#define CAN_ACCF_AFMR_ACCBP 0x00000002U -#define CAN_ACCF_AFMR_EFCAN 0x00000004U - -#define CAN_IER_RIE 0x000000001U -#define CAN_IER_TIE1 0x000000002U -#define CAN_IER_EIE 0x000000004U -#define CAN_IER_DOIE 0x000000008U -#define CAN_IER_WUIE 0x000000010U -#define CAN_IER_EPIEX 0x000000020U -#define CAN_IER_ALIEX 0x000000040U -#define CAN_IER_BEIEX 0x000000080U -#define CAN_IER_IDIEX 0x000000100U -#define CAN_IER_TIE2 0x000000200U -#define CAN_IER_TIE3 0x000000400U - -#endif /*LPC176X_TIMER_DEFS_H*/ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/can.h b/c/src/lib/libbsp/arm/lpc176x/include/can.h deleted file mode 100755 index 7515ec2f53..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/can.h +++ /dev/null @@ -1,179 +0,0 @@ -/** - * @file can.h - * - * @ingroup lpc176x - * - * @brief CAN controller for the mbed lpc1768 board. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LPC176X_CAN_H -#define LPC176X_CAN_H - -#include <bsp.h> -#include <bsp/io.h> -#include <bsp/lpc176x.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief The CAN devices of the board. - */ -typedef enum { - CAN_0, - CAN_1, - CAN_DEVICES_NUMBER -} lpc176x_can_number; - -/** - * @brief A CAN message represented for the registers of the device. - */ -typedef struct { - uint32_t info; - uint32_t id; - uint32_t data_a; - uint32_t data_b; -} registers_can_message; - -/** - * @brief A CAN message represented with each logical parts - */ -typedef struct { - unsigned int reserved1 : 16; - unsigned int dlc : 4; /* Bits 16..19: DLC - Data Length Counter*/ - unsigned int reserved0 : 10; - unsigned int rtr : 1; /* Bit 30: Set if this is a RTR message*/ - unsigned int type : 1; /* Bit 31: Set if this is a 29-bit ID message*/ - unsigned int id; /* CAN Message ID (11-bit or 29-bit)*/ - unsigned char data[ 8 ]; /* CAN Message Data Bytes 0-7*/ -} low_level_can_message; - -/** - * @brief A CAN message represented of both forms. - */ -typedef union { - low_level_can_message low_level; - registers_can_message registers; -} can_message; - -/** - * @brief The possible interrupt sources for CAN. - */ -typedef enum { - IRQ_RX = 0, - IRQ_TX, - IRQ_ERROR, - IRQ_OVERRUN, - IRQ_WAKEUP, - IRQ_PASSIVE, - IRQ_ARB, - IRQ_BUS, - IRQ_READY, - CAN_IRQ_NUMBER -} can_irq_type; - -/** - * @brief An isr for a CAN interrupt - * - * @param number The CAN which rised the interrupt. - */ -typedef void (*lpc176x_can_isr) ( lpc176x_can_number number ); - -/** - * @brief A CAN frequency value - */ -typedef unsigned int can_freq; - -/** - * @brief Opens CAN device. - * @details It enables the module and gives it a clock, sets the pins, - * disables the interrupts, sets the frequency and bypasses - * the acceptance filter. - * - * @param minor The device to open. - * @param freq The desired frequency. - * @return RTEMS_SUCCESFUL on success. - */ -rtems_status_code can_open( lpc176x_can_number minor, can_freq freq ); - -/** - * @brief Closes the passed CAN device and shut it down. - * - * @param minor The device to close. - * @return RTEMS_SUCCESSFUL if ok, RTEMS_INVALID_NUMBER for a bad parameter. - */ -rtems_status_code can_close( lpc176x_can_number minor ); - -/** - * @brief Reads the CAN device. - * - * @param minor The CAN device to read. - * @param message The read message. - * @return RTEMS_SUCCESSFUL if read ok, RTEMS_IO_ERROR otherwise. - */ -rtems_status_code can_read( - const lpc176x_can_number minor, - can_message *message -); - -/** - * @brief Writes the passed CAN message into the selected CAN device. - * - * @param minor The device to write. - * @param message The message to write. - * @return RTEMS_SUCCESFUL if write ok. RTEMS_IO_ERROR otherwise. - */ -rtems_status_code can_write( - const lpc176x_can_number minor, - const can_message *const message -); - -/** - * @brief Registers an isr in the driver vector, and enables the interrupt -* in the device. - * - * @param number The CAN device to set - * @param type The interrupt type. - * @param isr The isr to register. - * @return RTEMS_SUCCESSFUL if ok RTEMS_INVALID_NUMBER otherwise. - */ -rtems_status_code can_register_isr( - const lpc176x_can_number number, - const can_irq_type type, - const lpc176x_can_isr isr -); - -/** - * @brief Creates a CAN message. - * @details [long description] - * - * @param msg The created message. - * @param _id The can id for the message. - * @param _data The data of the message. - * @param _len The length of the message. - * @return RTEMS_SUCCESFUL if created, RTEMS_INVALID_NUMBER otherwise. - */ -rtems_status_code create_can_message( - can_message *const msg, - const int _id, - const char *const _data, - const char _len -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* ifndef LPC176X_CAN_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/common-types.h b/c/src/lib/libbsp/arm/lpc176x/include/common-types.h deleted file mode 100644 index 943ff288a9..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/common-types.h +++ /dev/null @@ -1,118 +0,0 @@ -/** - * @file common-types.h - * - * @ingroup lpc176x - * - * @brief Definitions types used by some devices in common. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_COMMON_TYPES_H -#define LIBBSP_ARM_LPC176X_COMMON_TYPES_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief A pin of the board. - */ -typedef uint32_t lpc176x_pin_number; - -/** - * @brief Microseconds representation. - */ -typedef uint32_t lpc176x_microseconds; - -/** - * @brief lpc176x module representation. - * - * Enumerated type to define the set of modules for a lpc176x board. - */ -typedef enum { - LPC176X_MODULE_WD, - LPC176X_MODULE_ADC, - LPC176X_MODULE_CAN_0, - LPC176X_MODULE_CAN_1, - LPC176X_MODULE_ACCF, - LPC176X_MODULE_DAC, - LPC176X_MODULE_GPDMA, - LPC176X_MODULE_GPIO, - LPC176X_MODULE_I2S, - LPC176X_MODULE_MCI, - LPC176X_MODULE_MCPWM, - LPC176X_MODULE_PCB, - LPC176X_MODULE_PWM_0, - LPC176X_MODULE_PWM_1, - LPC176X_MODULE_QEI, - LPC176X_MODULE_RTC, - LPC176X_MODULE_SYSCON, - LPC176X_MODULE_TIMER_0, - LPC176X_MODULE_TIMER_1, - LPC176X_MODULE_TIMER_2, - LPC176X_MODULE_TIMER_3, - LPC176X_MODULE_UART_0, - LPC176X_MODULE_UART_1, - LPC176X_MODULE_UART_2, - LPC176X_MODULE_UART_3, - LPC176X_MODULE_USB -} lpc176x_module; - -/** - * @brief Defines all the clock modules. - * - * Enumerated type to define the set of clock modules for a lpc176x board. - */ -typedef enum { - LPC176X_MODULE_PCLK_DEFAULT = 0x4U, - LPC176X_MODULE_CCLK = 0x1U, - LPC176X_MODULE_CCLK_2 = 0x2U, - LPC176X_MODULE_CCLK_4 = 0x0U, - LPC176X_MODULE_CCLK_6 = 0x3U, - LPC176X_MODULE_CCLK_8 = 0x3U -} lpc176x_module_clock; - -/** - * @brief Fast Input/Output registers representation. - */ -typedef struct { - /** - * @brief Direction control register. - */ - uint32_t dir; - uint32_t reserved[ 3U ]; - /** - * @brief Mask register for port. - */ - uint32_t mask; - /** - * @brief Pinvalue register using 'mask'. - */ - uint32_t pin; - /** - * @brief Output Set register using 'mask'. - */ - uint32_t set; - /** - * @brief Output Clear register using 'maks'. - */ - uint32_t clr; -} lpc176x_fio; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_COMMON_TYPES_H */
\ No newline at end of file diff --git a/c/src/lib/libbsp/arm/lpc176x/include/dma.h b/c/src/lib/libbsp/arm/lpc176x/include/dma.h deleted file mode 100644 index 65edfc4e30..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/dma.h +++ /dev/null @@ -1,98 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x_dma - * - * @brief Direct memory access (DMA) support. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_DMA_H -#define LIBBSP_ARM_LPC176X_DMA_H - -#include <rtems.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc176x_dma DMA Support - * - * @ingroup lpc176x - * - * @brief Direct memory access (DMA) support. - * - * @{ - */ - -/** - * @brief Initializes the general purpose DMA. - */ -void lpc176x_dma_initialize( void ); - -/** - * @brief Tries to obtain the DMA channel @a channel. - * - * @retval RTEMS_SUCCESSFUL Successful operation. - * @retval RTEMS_INVALID_ID Invalid channel number. - * @retval RTEMS_RESOURCE_IN_USE Channel already occupied. - */ -rtems_status_code lpc176x_dma_channel_obtain( unsigned channel ); - -/** - * @brief Releases the DMA channel @a channel. - * - * You must have obtained this channel with lpc176x_dma_channel_obtain() - * previously. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc176x_dma_channel_release( unsigned channel ); - -/** - * @brief Disables the DMA channel @a channel. - * - * If @a force is @c false the channel will be halted and disabled when the - * channel is inactive otherwise it will be disabled immediately. - * - * If the channel number @a channel is out of range nothing will happen. - */ -void lpc176x_dma_channel_disable( - unsigned channel, - bool force -); - -rtems_status_code lpc176x_dma_copy_initialize( void ); - -rtems_status_code lpc176x_dma_copy_release( void ); - -rtems_status_code lpc176x_dma_copy( - unsigned channel, - const void *dest, - const void *src, - size_t n, - size_t width -); - -rtems_status_code lpc176x_dma_copy_wait( unsigned channel ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_DMA_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/gpio-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/gpio-defs.h deleted file mode 100644 index c6ed499d35..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/gpio-defs.h +++ /dev/null @@ -1,218 +0,0 @@ -/** - * @file gpio-defs.h - * - * @ingroup lpc176x - * - * @brief API definitions of the GPIO driver for the lpc176x bsp in RTEMS. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_GPIO_DEFS_H -#define LIBBSP_ARM_LPC176X_GPIO_DEFS_H - -#include <bsp/common-types.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* General Purpose Input/Output (GPIO) */ -#define LPC176X_GPIO_BASE_ADDR 0x40028000U -#define LPC176X_GPIO_INTERRUPT_STATUS 0x40028080U - -#define LPC176X_IOPIN0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x00U ) ) -#define LPC176X_IOSET0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x04U ) ) -#define LPC176X_IODIR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x08U ) ) -#define LPC176X_IOCLR0 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x0CU ) ) -#define LPC176X_IOPIN1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x10U ) ) -#define LPC176X_IOSET1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x14U ) ) -#define LPC176X_IODIR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x18U ) ) -#define LPC176X_IOCLR1 ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR + \ - 0x1CU ) ) - -/* GPIO Interrupt Registers */ -#define LPC176X_IO0_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0x90U ) ) -#define LPC176X_IO0_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0x94U ) ) -#define LPC176X_IO0_INT_STAT_R ( *(volatile uint32_t *) ( \ - LPC176X_GPIO_BASE_ADDR \ - + 0x84U ) ) -#define LPC176X_IO0_INT_STAT_F ( *(volatile uint32_t *) ( \ - LPC176X_GPIO_BASE_ADDR \ - + 0x88U ) ) -#define LPC176X_IO0_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0x8CU ) ) -#define LPC176X_IO2_INT_EN_R ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0xB0U ) ) -#define LPC176X_IO2_INT_EN_F ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0xB4U ) ) -#define LPC176X_IO2_INT_STAT_R ( *(volatile uint32_t *) ( \ - LPC176X_GPIO_BASE_ADDR \ - + 0xA4U ) ) -#define LPC176X_IO2_INT_STAT_F ( *(volatile uint32_t *) ( \ - LPC176X_GPIO_BASE_ADDR \ - + 0xA8U ) ) -#define LPC176X_IO2_INT_CLR ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0xACU ) ) -#define LPC176X_IO_INT_STAT ( *(volatile uint32_t *) ( LPC176X_GPIO_BASE_ADDR \ - + 0x80U ) ) - -#define LPC176X_RESERVED_ISR_FUNCT_SIZE 2U -#define LPC176X_RESERVED_ISR_FUNCT_MAX_SIZE 5U - -#define LPC176X_MAX_PORT_NUMBER 160U -#define LPC176X_SET_BIT( reg, pin, value ) \ - reg = ( reg & ~( 1U << pin ) ) | ( ( value & 1U ) << pin ) - -#define LPC176X_INT_STATUS ( *(volatile uint32_t *) \ - ( LPC176X_GPIO_INTERRUPT_STATUS ) ) -#define LPC176X_INT_STATUS_P0 1U -#define LPC176X_INT_STATUS_P2 ( 1U << 2U ) -#define LPC176X_INT_ENABLE 1U -#define LPC176X_INT_DISABLE 0U - -#define LPC176X_IRQ_EINT_3 21U - -#define LPC176X_PIN_BIT( pin ) ( 1U << pin ) - -/** - * @brief The direction of the GPIO port (input or output). - * - * Enumerated type to define the set of function types for a gpio device. - */ -typedef enum { - LPC176X_GPIO_FUNCTION_INPUT, - LPC176X_GPIO_FUNCTION_OUTPUT, - LPC176X_GPIO_FUNCTION_COUNT -} -lpc176x_gpio_direction; - -/** - * @brief The interrupt sources edge for a GPIO. - * - * Enumerated type to define the set of interrupt types for a gpio device. - */ -typedef enum { - LPC176X_GPIO_INTERRUPT_DISABLE, - LPC176X_GPIO_INTERRUPT_RISING, - LPC176X_GPIO_INTERRUPT_FALLING, - LPC176X_GPIO_INTERRUPT_BOTH, - LPC176X_GPIO_INTERRUPT_COUNT -} lpc176x_gpio_interrupt; - -/** - * @brief The ports for a GPIO. - * - * Enumerated type to define the set of ports for a gpio device. - */ -typedef enum { - LPC176X_GPIO_PORT_0, - LPC176X_GPIO_PORT_1, - LPC176X_GPIO_PORT_2, - LPC176X_GPIO_PORT_3, - LPC176X_GPIO_PORT_4, - LPC176X_GPIO_PORTS_COUNT -} lpc176x_gpio_ports; - -/** - * @brief Addresses for a GPIO. - * - * Enumerated type to define the set of fio bases addresses - * for a gpio device. - */ -typedef enum { - LPC176X_FIO0_BASE_ADDRESS = 0x2009C000U, - LPC176X_FIO1_BASE_ADDRESS = 0x2009C020U, - LPC176X_FIO2_BASE_ADDRESS = 0x2009C040U, - LPC176X_FIO3_BASE_ADDRESS = 0x2009C060U, - LPC176X_FIO4_BASE_ADDRESS = 0x2009C080U, -} lpc176x_gpio_address; - -/** - * @brief Addresses for the two interrupts. - * - * Enumerated type to define the set of interrupt addresses - * for a gpio device. - */ -typedef enum { - LPC176X_IO0_INT_BASE_ADDRESS = 0x40028084U, - LPC176X_IO2_INT_BASE_ADDRESS = 0x400280A4U, -} lpc176x_interrupt_address; - -/** - * @brief GPIO Interrupt register map. - */ -typedef struct { - /** - * @brief Interrupt Enable for Rising edge. - */ - volatile uint32_t StatR; - /** - * @brief Interrupt Enable for Falling edge. - */ - volatile uint32_t StatF; - /** - * @brief Interrupt Clear. - */ - volatile uint32_t Clr; - /** - * @brief Interrupt Enable for Rising edge. - */ - volatile uint32_t EnR; - /** - * @brief Interrupt Enable for Falling edge. - */ - volatile uint32_t EnF; -} lpc176x_interrupt_control; - -/** - * @brief A function that attends an interrupt for GPIO. - * - * @param pin Pin number. - * @param edge Interrupt. - * @return Pointer to the interrupt function. - */ -typedef void (*lpc176x_gpio_interrupt_function) ( - const lpc176x_pin_number pin, - const lpc176x_gpio_interrupt edge -); - -/** - * @brief A registered interrupt function for the pin 'pin'. - */ -typedef struct { - /** - * @brief Pin board. - */ - lpc176x_pin_number pin; - /** - * @brief A function that attends an interrupt for 'pin'. - */ - lpc176x_gpio_interrupt_function function; -} lpc176x_registered_interrupt_function; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_GPIO_DEFS_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/io-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/io-defs.h deleted file mode 100644 index f9cf3dbbbd..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/io-defs.h +++ /dev/null @@ -1,142 +0,0 @@ -/** - * @file io-defs.h - * - * @ingroup lpc176x - * - * @brief Input/output module definitions. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_IO_DEFS_H -#define LIBBSP_ARM_LPC176X_IO_DEFS_H - -#include <bsp/lpc176x.h> -#include <bsp/common-types.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC176X_PLL0CON 0XAAU -#define LPC176X_PLL0CFG 0X55U - -#define LPC176X_CCLK_PRESCALER_DIVISOR 1000000U - -#define LPC176X_PINSEL ( &PINSEL0 ) -#define LPC176X_PINMODE ( &PINMODE0 ) - -#define LPC176X_PIN_SELECT( index ) ( ( index ) >> 4U ) -#define LPC176X_PIN_SELECT_SHIFT( index ) ( ( ( index ) & 0xFU ) << 1U ) -#define LPC176X_PIN_SELECT_MASK 0x3U -#define LPC176X_PIN_SELECT_MASK_SIZE 2U -#define LPC176X_PIN_UART_0_TXD 2U -#define LPC176X_PIN_UART_0_RXD 3U -#define LPC176X_PIN_UART_1_TXD 15U -#define LPC176X_PIN_UART_1_RXD 16U -#define LPC176X_PIN_UART_2_TXD 10U -#define LPC176X_PIN_UART_2_RXD 11U -#define LPC176X_PIN_UART_3_TXD 0U -#define LPC176X_PIN_UART_3_RXD 1U - -#define LPC176X_MODULE_BITS_COUNT 32U -#define LPC176X_MODULE_COUNT ( LPC176X_MODULE_USB + 1U ) - -#define LPC176X_IO_PORT_COUNT 5U -#define LPC176X_IO_INDEX_MAX ( LPC176X_IO_PORT_COUNT * \ - LPC176X_MODULE_BITS_COUNT ) -#define LPC176X_IO_INDEX_BY_PORT( port, bit ) ( ( ( port ) << 5U ) + ( bit ) ) -#define LPC176X_IO_PORT( index ) ( ( index ) >> 5U ) -#define LPC176X_IO_PORT_BIT( index ) ( ( index ) & 0x1FU ) - -/** - * @brief Defines the functions according to the pin. - * - * Enumerated type to define the set of pin function for a io device. - */ -typedef enum { - LPC176X_PIN_FUNCTION_00, - LPC176X_PIN_FUNCTION_01, - LPC176X_PIN_FUNCTION_10, - LPC176X_PIN_FUNCTION_11, - LPC176X_PIN_FUNCTION_COUNT -} -lpc176x_pin_function; - -/** - * @brief Defines the pin modes. - * - */ -typedef enum { - LPC176X_PIN_MODE_PULLUP, - LPC176X_PIN_MODE_REPEATER, - LPC176X_PIN_MODE_NONE, - LPC176X_PIN_MODE_PULLDOWN, - LPC176X_PIN_MODE_COUNT -} -lpc176x_pin_mode; - -/** - * @brief Defines all type of pins. - * - * Enumerated type to define the set of pin type for a io device. - */ -typedef enum { - LPC176X_PIN_TYPE_DEFAULT, - LPC176X_PIN_TYPE_ADC, - LPC176X_PIN_TYPE_DAC, - LPC176X_PIN_TYPE_OPEN_DRAIN -} lpc176x_pin_type; - -/** - * @brief Represents each pclksel number. - * - * Enumerated type to define the set of values for a pcklsel. - */ -typedef enum { - LPC176X_SCB_PCLKSEL0, - LPC176X_SCB_PCLKSEL1, - LPC176X_SCB_PCLKSEL_COUNT -} lpc176x_scb_value_pclksel; - -/** - * @brief Defines the module entry. - */ -typedef struct { - /** - * @brief Power entry bit. - */ - unsigned char power : 1; - /** - * @brief Clock entry bit. - */ - unsigned char clock : 1; - /** - * @brief Index entry bits. - */ - unsigned char index : 6; -} lpc176x_module_entry; - -#define LPC176X_MODULE_ENTRY( mod, pwr, clk, idx ) \ - [ mod ] = { \ - .power = pwr, \ - .clock = clk, \ - .index = idx \ - } - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_IO_DEFS_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/io.h b/c/src/lib/libbsp/arm/lpc176x/include/io.h deleted file mode 100644 index 4a8510479c..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/io.h +++ /dev/null @@ -1,88 +0,0 @@ -/** - * @file io.h - * - * @ingroup lpc176x - * - * @brief Input/output module methods definitions. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_IO_H -#define LIBBSP_ARM_LPC176X_IO_H - -#include <assert.h> -#include <rtems.h> -#include <bsp/io-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Sets pin to the selected function. - * - * @param pin The pin to set. - * @param function Defines the function to set. - */ -void lpc176x_pin_select( - uint32_t pin, - lpc176x_pin_function function -); - -/** - * @brief Sets pin to the selected mode. - * - * @param pin The pin to set. - * @param mode Defines the mode to set. - */ -void lpc176x_pin_set_mode( - const uint32_t pin, - const lpc176x_pin_mode mode -); - -/** - * @brief Enables the module power and clock. - * - * @param module Represents the module to be enabled. - * @param clock Represents the clock to set for this module. - * @return RTEMS_SUCCESFULL if the module was enabled succesfully. - */ -rtems_status_code lpc176x_module_enable( - lpc176x_module module, - lpc176x_module_clock clock -); - -/** - * @brief Checks if the current module is turned off and disables a module. - * - * @param module Represents the module to be disabled. - * @return RTEMS_SUCCESFULL if the module was disabled succesfully. - */ -rtems_status_code lpc176x_module_disable( lpc176x_module module ); - -/** - * @brief Checks if the current module is enabled or not. - * - * @param module Represents the module to be checked. - * @return TRUE if the module is enabled. - * FALSE otherwise. - */ -bool lpc176x_module_is_enabled( lpc176x_module module ); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_IO_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/irq.h b/c/src/lib/libbsp/arm/lpc176x/include/irq.h deleted file mode 100644 index 719608c8f7..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/irq.h +++ /dev/null @@ -1,108 +0,0 @@ -/** - * @file - * - * @ingroup bsp_interrupt - * - * @brief LPC176X interrupt definitions. - */ - -/* - * Copyright (c) 2008-2012 embedded brains GmbH. All rights reserved. - * - * embedded brains GmbH - * Obere Lagerstr. 30 - * 82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_IRQ_H -#define LIBBSP_ARM_LPC176X_IRQ_H - -#ifndef ASM -#include <rtems.h> -#include <rtems/irq.h> -#include <rtems/irq-extension.h> -#endif - -/** - * @addtogroup bsp_interrupt - * - * @{ - */ - -#define BSP_INTERRUPT_VECTOR_MIN 0U - -#define LPC176X_IRQ_WDT 0U -#define LPC176X_IRQ_TIMER_0 1U -#define LPC176X_IRQ_TIMER_1 2U -#define LPC176X_IRQ_TIMER_2 3U -#define LPC176X_IRQ_TIMER_3 4U -#define LPC176X_IRQ_UART_0 5U -#define LPC176X_IRQ_UART_1 6U -#define LPC176X_IRQ_UART_2 7U -#define LPC176X_IRQ_UART_3 8U -#define LPC176X_IRQ_PWM_1 9U -#define LPC176X_IRQ_PLL 16U -#define LPC176X_IRQ_RTC 17U -#define LPC176X_IRQ_EINT_0 18U -#define LPC176X_IRQ_EINT_1 19U -#define LPC176X_IRQ_EINT_2 20U -#define LPC176X_IRQ_EINT_3 21U -#define LPC176X_IRQ_ADC_0 22U -#define LPC176X_IRQ_BOD 23U -#define LPC176X_IRQ_USB 24U -#define LPC176X_IRQ_CAN 25U -#define LPC176X_IRQ_DMA 26U -#define LPC176X_IRQ_I2S 27U -#define LPC176X_IRQ_SD_MMC 29U -#define LPC176X_IRQ_MCPWM 30U -#define LPC176X_IRQ_QEI 31U -#define LPC176X_IRQ_PLL_ALT 32U -#define LPC176X_IRQ_USB_ACTIVITY 33U -#define LPC176X_IRQ_CAN_ACTIVITY 34U -#define LPC176X_IRQ_UART_4 35U -#define LPC176X_IRQ_GPIO 38U -#define LPC176X_IRQ_PWM 39U -#define LPC176X_IRQ_EEPROM 40U - -#define BSP_INTERRUPT_VECTOR_MAX 40 - -#define LPC176X_IRQ_PRIORITY_VALUE_MIN 0U - -#define LPC176X_IRQ_PRIORITY_VALUE_MAX 31U - -#define LPC176X_IRQ_PRIORITY_COUNT ( LPC176X_IRQ_PRIORITY_VALUE_MAX + 1U ) -#define LPC176X_IRQ_PRIORITY_HIGHEST LPC176X_IRQ_PRIORITY_VALUE_MIN -#define LPC176X_IRQ_PRIORITY_LOWEST LPC176X_IRQ_PRIORITY_VALUE_MAX - -#ifndef ASM - -/** - * @brief Sets the priority according to the current interruption. - * - * @param vector Interrupt to be attended. - * @param priority Interrupts priority. - */ -void lpc176x_irq_set_priority( - rtems_vector_number vector, - unsigned priority -); - -/** - * @brief Gets the priority number according to the current interruption. - * - * @param vector Interrupts to be attended. - * @return The priority number according to the current interruption. - */ -unsigned lpc176x_irq_get_priority( rtems_vector_number vector ); - -#endif /* ASM */ - -/** @} */ - -#endif /* LIBBSP_ARM_LPC176X_IRQ_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h b/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h deleted file mode 100644 index 3eef02152e..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/lpc-clock-config.h +++ /dev/null @@ -1,45 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x - * - * @brief Clock driver configuration. - */ - -/* - * Copyright (c) 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H -#define LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H - -#include <bsp.h> -#include <bsp/irq.h> -#include <bsp/lpc176x.h> -#include <bsp/io.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC_CLOCK_INTERRUPT LPC176X_IRQ_TIMER_0 -#define LPC_CLOCK_TIMER_BASE TMR0_BASE_ADDR -#define LPC_CLOCK_TIMECOUNTER_BASE TMR1_BASE_ADDR -#define LPC_CLOCK_REFERENCE LPC176X_PCLK -#define LPC_CLOCK_MODULE_ENABLE() \ - lpc176x_module_enable( LPC176X_MODULE_TIMER_0, LPC176X_MODULE_PCLK_DEFAULT ) - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_LPC_CLOCK_CONFIG_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/lpc-gpio.h b/c/src/lib/libbsp/arm/lpc176x/include/lpc-gpio.h deleted file mode 100644 index 9cb23df142..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/lpc-gpio.h +++ /dev/null @@ -1,100 +0,0 @@ -/** - * @file lpc-gpio.h - * - * @ingroup lpc176x - * - * @brief API of the GPIO driver for the lpc176x bsp in RTEMS. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_GPIO_H -#define LIBBSP_ARM_LPC176X_GPIO_H - -#include <bsp/lpc176x.h> -#include <bsp/gpio-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Configures the pin as input or output GPIO. - * - * @param pin The pin to configure - * @param dir Input or output. - */ -rtems_status_code lpc176x_gpio_config( - lpc176x_pin_number pin, - lpc176x_gpio_direction dir -); - -/** - * @brief Configures the pin as input, enables interrupt for an - * edge/s and sets isrfunct as the function to call when that - * interrupt occurs. - * - * @param pin The pin to configure. - * @param edge Which edge or edges will activate the interrupt. - * @param isrfunct The function that is called when the interrupt occurs. - * @return RTEMS_SUCCESSFULL if the configurations was success. - */ -rtems_status_code lpc176x_gpio_config_input_with_interrupt( - lpc176x_pin_number pin, - lpc176x_gpio_interrupt edge, - lpc176x_gpio_interrupt_function isrfunct -); - -/** - * @brief Sets the output pin to 1. - * - * @param pin The pin to set - */ -rtems_status_code lpc176x_gpio_set_pin( lpc176x_pin_number pin ); - -/** - * @brief Sets the output pin to 0. - * - * @param pin The pin to set - */ -rtems_status_code lpc176x_gpio_clear_pin( lpc176x_pin_number pin ); - -/** - * @brief Sets the output pin to 0 or 1 according to value. - * - * @param pin The pin to set - * @param value the value to set. - */ -rtems_status_code lpc176x_gpio_write_pin( - lpc176x_pin_number pin, - bool value -); - -/** - * @brief Returns the value at the given input pin. - * - * @param pin The pin where to read the value. - * @param pin_value TRUE if the pin value was getted successfuly. - * @return RTEMS_SUCCESSFUL if the pin value was getted successfuly. - */ -rtems_status_code lpc176x_gpio_get_pin_value( - lpc176x_pin_number pin, - bool *pin_value -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_GPIO_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/lpc176x.h b/c/src/lib/libbsp/arm/lpc176x/include/lpc176x.h deleted file mode 100644 index f10991f346..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/lpc176x.h +++ /dev/null @@ -1,1585 +0,0 @@ -/** - * @file lpc176x.h - * - * @ingroup lpc176x - * - * @brief Specific register definitions according to lpc176x family boards. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_H -#define LIBBSP_ARM_LPC176X_H - -#include <bsp/lpc-i2s.h> - -#define LPC176X_PLL_CON_PLLE BSP_BIT32( 0 ) -#define LPC176X_PLL_CON_PLLC BSP_BIT32( 1 ) -#define LPC176X_PLL_SEL_MSEL( val ) BSP_FLD32( val, 0, 14 ) -#define LPC176X_PLL_SEL_MSEL_GET( reg ) BSP_FLD32GET( reg, 0, 14 ) -#define LPC176X_PLL_SEL_MSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 14 ) -#define LPC176X_PLL_SEL_PSEL( val ) BSP_FLD32( val, 16, 23 ) -#define LPC176X_PLL_SEL_PSEL_GET( reg ) BSP_FLD32GET( reg, 16, 23 ) -#define LPC176X_PLL_SEL_PSEL_SET( reg, val ) BSP_FLD32SET( reg, val, 16, 23 ) -#define LPC176X_PLL_STAT_PLLE BSP_BIT32( 24 ) -#define LPC176X_PLL_STAT_PLLC BSP_BIT32( 25 ) -#define LPC176X_PLL_STAT_PLOCK BSP_BIT32( 26 ) - -/** - * @brief Phase-Locked Loop representation. - */ -typedef struct { - /** - * @brief PLL Control Register. - */ - uint32_t con; - /** - * @brief PLL Configuration Register. - */ - uint32_t cfg; - /** - * @brief PLL Status Register. - */ - uint32_t stat; - /** - * @brief PLL Feed Register. - */ - uint32_t feed; -} lpc176x_pll; - -#define LPC176X_SCB_BASE_ADDR 0x400FC000U -#define LPC176X_SCB_FLASHCFG_FLASHTIM( val ) BSP_FLD32( val, 12, 15 ) -#define LPC176X_SCB_FLASHCFG_FLASHTIM_GET( reg ) BSP_FLD32GET( reg, 12, 15 ) -#define LPC176X_SCB_FLASHCFG_FLASHTIM_SET( reg, val ) BSP_FLD32SET( reg, val, \ - 12, 15 ) -#define LPC176X_SCB_MEMMAP_MAP BSP_BIT32( 0 ) -/* POWER MODE CONTROL REGISTER (PCON) */ -/* Power mode control bit 0 */ -#define LPC176X_SCB_PCON_PM0 BSP_BIT32( 0 ) -/* Power mode control bit 1 */ -#define LPC176X_SCB_PCON_PM1 BSP_BIT32( 1 ) -/* Brown-Out Reduced ower Down */ -#define LPC176X_SCB_PCON_BODRPM BSP_BIT32( 2 ) -/* Brown-Out Global Disable */ -#define LPC176X_SCB_PCON_BOGD BSP_BIT32( 3 ) -/* Brown-Out Reset Disable */ -#define LPC176X_SCB_PCON_BORD BSP_BIT32( 4 ) -/* Sleep Mode entry flag */ -#define LPC176X_SCB_PCON_SMFLAG BSP_BIT32( 8 ) -/* Deep Sleep entry flag */ -#define LPC176X_SCB_PCON_DSFLAG BSP_BIT32( 9 ) -/* Power-Down entry flag */ -#define LPC176X_SCB_PCON_PDFLAG BSP_BIT32( 10 ) -/* Deep Power-Down entry flag */ -#define LPC176X_SCB_PCON_DPDFLAG BSP_BIT32( 11 ) -/* POWER CONTROL for PERIPHERALS REGISTER (PCONP) */ -/* 0 - Reserved */ -/* Timer/Counter 0 power/clock control bit */ -#define LPC176X_SCB_PCONP_TIMER_0 BSP_BIT32( 1 ) -/* Timer/Counter 1 power/clock control bit */ -#define LPC176X_SCB_PCONP_TIMER_1 BSP_BIT32( 2 ) -/* UART 0 power/clock control bit */ -#define LPC176X_SCB_PCONP_UART_0 BSP_BIT32( 3 ) -/* UART 1 power/clock control bit */ -#define LPC176X_SCB_PCONP_UART_1 BSP_BIT32( 4 ) -/* 5 - Reserved */ -/* PWM 1 power/clock control bit */ -#define LPC176X_SCB_PCONP_PWM_0 BSP_BIT32( 6 ) -/* The I2C0 interface power/clock control bit */ -#define LPC176X_SCB_PCONP_I2C_0 BSP_BIT32( 7 ) -/* The SPI interface power/clock control bit */ -#define LPC176X_SCB_PCONP_SPI BSP_BIT32( 8 ) -/* The RTC power/clock control bit */ -#define LPC176X_SCB_PCONP_RTC BSP_BIT32( 9 ) -/* The SSP1 interface power/clock control bit */ -#define LPC176X_SCB_PCONP_SSP_1 BSP_BIT32( 10 ) -/* 11 - Reserved */ -/* A/D converter (ADC) power/clock control bit */ -#define LPC176X_SCB_PCONP_ADC BSP_BIT32( 12 ) -/* CAN Controller 1 power/clock control bit */ -#define LPC176X_SCB_PCONP_CAN_1 BSP_BIT32( 13 ) -/* CAN Controller 2 power/clock control bit */ -#define LPC176X_SCB_PCONP_CAN_2 BSP_BIT32( 14 ) -/* Power/clock control bit for IOCON, GPIO, and GPIO interrupts*/ -#define LPC176X_SCB_PCONP_GPIO BSP_BIT32( 15 ) -/* Repetitive Interrupt Timer power/clock control bit */ -#define LPC176X_SCB_PCONP_RIT BSP_BIT32( 16 ) -/* Motor Control PWM */ -#define LPC176X_SCB_PCONP_MCPWM BSP_BIT32( 17 ) -/* Quadrate Encoder Interface power/clock control bit */ -#define LPC176X_SCB_PCONP_QEI BSP_BIT32( 18 ) -/* The IC21 interface power/clock control bit */ -#define LPC176X_SCB_PCONP_I2C_1 BSP_BIT32( 19 ) -/* 20 - Reserved */ -/* The SSP0 interface power/clock control bit */ -#define LPC176X_SCB_PCONP_SSP_0 BSP_BIT32( 21 ) -/* Timer 2 power/clock control bit */ -#define LPC176X_SCB_PCONP_TIMER_2 BSP_BIT32( 22 ) -/* Timer 3 power/clock control bit */ -#define LPC176X_SCB_PCONP_TIMER_3 BSP_BIT32( 23 ) -/* UART 2 power/clock control bit */ -#define LPC176X_SCB_PCONP_UART_2 BSP_BIT32( 24 ) -/* UART 3 power/clock control bit */ -#define LPC176X_SCB_PCONP_UART_3 BSP_BIT32( 25 ) -/* I2C interface 2 power/clock control bit */ -#define LPC176X_SCB_PCONP_I2C_2 BSP_BIT32( 26 ) -/* I2S interface power/clock control bit */ -#define LPC176X_SCB_PCONP_I2S BSP_BIT32( 27 ) -/* 28 - Reserved */ -/* GPDMA function power/clock control bit */ -#define LPC176X_SCB_PCONP_GPDMA BSP_BIT32( 29 ) -/* Ethernet block power/clock control bit */ -#define LPC176X_SCB_PCONP_ENET BSP_BIT32( 30 ) -/* USB interface power/clock control bit */ -#define LPC176X_SCB_PCONP_USB BSP_BIT32( 31 ) -#define LPC176X_SCB_CCLKSEL_CCLKDIV( val ) BSP_FLD32( val, 0, 7 ) -#define LPC176X_SCB_CCLKSEL_CCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 7 ) -#define LPC176X_SCB_CCLKSEL_CCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ - val, \ - 0, \ - 7 ) -#define LPC176X_SCB_CCLKSEL_CCLKSEL BSP_BIT32( 8 ) -#define LPC176X_SCB_USBCLKSEL_USBDIV( val ) BSP_FLD32( val, 0, 4 ) -#define LPC176X_SCB_USBCLKSEL_USBDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) -#define LPC176X_SCB_USBCLKSEL_USBDIV_SET( reg, val ) BSP_FLD32SET( reg, \ - val, \ - 0, \ - 4 ) -#define LPC176X_SCB_USBCLKSEL_USBSEL( val ) BSP_FLD32( val, 8, 9 ) -#define LPC176X_SCB_USBCLKSEL_USBSEL_GET( reg ) BSP_FLD32GET( reg, 8, 9 ) -#define LPC176X_SCB_USBCLKSEL_USBSEL_SET( reg, val ) BSP_FLD32SET( reg, \ - val, \ - 8, \ - 9 ) -#define LPC176X_SCB_CLKSRCSEL_CLKSRC BSP_BIT32( 0 ) -#define LPC176X_SCB_SCS_MCIPWR BSP_BIT32( 3 ) -#define LPC176X_SCB_SCS_OSC_RANGE_SEL BSP_BIT32( 4 ) -#define LPC176X_SCB_SCS_OSC_ENABLE BSP_BIT32( 5 ) -#define LPC176X_SCB_SCS_OSC_STATUS BSP_BIT32( 6 ) -#define LPC176X_SCB_PCLKSEL_PCLKDIV( val ) BSP_FLD32( val, 0, 4 ) -#define LPC176X_SCB_PCLKSEL_PCLKDIV_GET( reg ) BSP_FLD32GET( reg, 0, 4 ) -#define LPC176X_SCB_PCLKSEL_PCLKDIV_SET( reg, val ) BSP_FLD32SET( reg, \ - val, \ - 0, \ - 4 ) -#define LPC176X_SCB_PBOOST_BOOST BSP_BIT32( 0 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL( val ) BSP_FLD32( val, 3, 0 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_GET( reg ) BSP_FLD32GET( reg, 3, 0 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTSEL_SET( reg, val ) BSP_FLD32SET( reg, \ - val, 3, 0 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV( val ) BSP_FLD32( val, 7, 4 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_GET( reg ) BSP_FLD32GET( reg, 7, 4 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUTDIV_SET( reg, val ) BSP_FLD32SET( reg, \ - val, 7, 4 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUT_EN BSP_BIT32( 8 ) -#define LPC176X_SCB_CLKOUTCFG_CLKOUT_ACT BSP_BIT32( 9 ) - -/** - * @brief System Control Block representation. - */ -typedef struct { - /** - * @brief Flash Accelerator Configuration Register. - */ - uint32_t flashcfg; - uint32_t reserved_04[ 15 ]; - /** - * @brief Memopry Map Control. - */ - uint32_t memmap; - uint32_t reserved_44[ 15 ]; - /** - * @brief Phase-Locked Loop 0. - */ - lpc176x_pll pll_0; - uint32_t reserved_90[ 4 ]; - /** - * @brief Phase-Locked Loop 1. - */ - lpc176x_pll pll_1; - uint32_t reserved_b0[ 4 ]; - /** - * @brief Power Mode Control register. - */ - uint32_t pcon; - /** - * @brief Power Control for Peripherals register. - */ - uint32_t pconp; - uint32_t reserved_c8[ 15 ]; - /** - *@brief Selects the divide valuefor creating the CPU clock from the - * PPL0 output. - */ - uint32_t cclksel; - /** - * @brief Selects the divide value for creating the USB clock from the - * PPL0 output. - */ - uint32_t usbclksel; - /** - * @brief Clock Source Select register. - */ - uint32_t clksrcsel; - uint32_t reserved_110[ 12 ]; - /** - * @brief External Interrupt flag register. - */ - uint32_t extint; - uint32_t reserved_144; - /** - * @brief External Interrupt Mode register. - */ - uint32_t extmode; - /** - * @brief External Interrupt Polarity register. - */ - uint32_t extpolar; - uint32_t reserved_150[ 12 ]; - /** - * @brief Reset Source Identification Register. - */ - uint32_t rsid; - uint32_t reserved_184[ 7 ]; - /** - * @brief System Controls and Status Register. - */ - uint32_t scs; - uint32_t reserved_1a4; - /** - * @brief Peripheral Clock Selection registers 0 and 1. - */ - uint32_t pclksel[ 2 ]; - /** - * @brief Peripheral boost. - */ - uint32_t pboost; - uint32_t reserved_1b4[ 5 ]; - /** - * @brief Clock Output Configuration Register. - */ - uint32_t clkoutcfg; - /** - * @brief Reset Control bit 0 and 1. - */ - uint32_t rstcon[ 2 ]; - uint32_t reserved_1d4[ 4 ]; -} lpc176x_scb; - -#define LPC176X_BASE 0x00u -#define LPC176X_SCB ( *(volatile lpc176x_scb *) ( LPC176X_SCB_BASE_ADDR ) ) - -/* Fast I/O setup */ -#define LPC176X_FIO_BASE_ADDR 0x2009C000U -#define LPC176X_FIO ( (volatile lpc176x_fio *) LPC176X_FIO_BASE_ADDR ) - -#define FIO0DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) -#define FIO0MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) -#define FIO0PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) -#define FIO0SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) -#define FIO0CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) - -#define FIO1DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) -#define FIO1MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) -#define FIO1PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) -#define FIO1SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) -#define FIO1CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) - -#define FIO2DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) -#define FIO2MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) -#define FIO2PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) -#define FIO2SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) -#define FIO2CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) - -#define FIO3DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) -#define FIO3MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) -#define FIO3PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) -#define FIO3SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) -#define FIO3CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) - -#define FIO4DIR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) -#define FIO4MASK ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) -#define FIO4PIN ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) -#define FIO4SET ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) -#define FIO4CLR ( *(volatile uint32_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) - -/* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ -#define FIO0DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) -#define FIO1DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) -#define FIO2DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) -#define FIO3DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) -#define FIO4DIR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) - -#define FIO0DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x01U ) ) -#define FIO1DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) -#define FIO2DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x41U ) ) -#define FIO3DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x61U ) ) -#define FIO4DIR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x81U ) ) - -#define FIO0DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) -#define FIO1DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) -#define FIO2DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) -#define FIO3DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) -#define FIO4DIR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) - -#define FIO0DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x03U ) ) -#define FIO1DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x23U ) ) -#define FIO2DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x43U ) ) -#define FIO3DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x63U ) ) -#define FIO4DIR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x83U ) ) - -#define FIO0DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x00U ) ) -#define FIO1DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x20U ) ) -#define FIO2DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x40U ) ) -#define FIO3DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x60U ) ) -#define FIO4DIRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x80U ) ) - -#define FIO0DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x02U ) ) -#define FIO1DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x22U ) ) -#define FIO2DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x42U ) ) -#define FIO3DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x62U ) ) -#define FIO4DIRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x82U ) ) - -#define FIO0MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) -#define FIO1MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) -#define FIO2MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) -#define FIO3MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) -#define FIO4MASK0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) - -#define FIO0MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x11U ) ) -#define FIO1MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x21U ) ) -#define FIO2MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x51U ) ) -#define FIO3MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x71U ) ) -#define FIO4MASK1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x91U ) ) - -#define FIO0MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) -#define FIO1MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) -#define FIO2MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) -#define FIO3MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) -#define FIO4MASK2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) - -#define FIO0MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x13U ) ) -#define FIO1MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x33U ) ) -#define FIO2MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x53U ) ) -#define FIO3MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x73U ) ) -#define FIO4MASK3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x93U ) ) - -#define FIO0MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x10U ) ) -#define FIO1MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x30U ) ) -#define FIO2MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x50U ) ) -#define FIO3MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x70U ) ) -#define FIO4MASKL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x90U ) ) - -#define FIO0MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x12U ) ) -#define FIO1MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x32U ) ) -#define FIO2MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x52U ) ) -#define FIO3MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x72U ) ) -#define FIO4MASKU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x92U ) ) - -#define FIO0PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) -#define FIO1PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) -#define FIO2PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) -#define FIO3PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) -#define FIO4PIN0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) - -#define FIO0PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x15U ) ) -#define FIO1PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x25U ) ) -#define FIO2PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x55U ) ) -#define FIO3PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x75U ) ) -#define FIO4PIN1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x95U ) ) - -#define FIO0PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) -#define FIO1PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) -#define FIO2PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) -#define FIO3PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) -#define FIO4PIN2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) - -#define FIO0PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x17U ) ) -#define FIO1PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x37U ) ) -#define FIO2PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x57U ) ) -#define FIO3PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x77U ) ) -#define FIO4PIN3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x97U ) ) - -#define FIO0PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x14U ) ) -#define FIO1PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x34U ) ) -#define FIO2PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x54U ) ) -#define FIO3PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x74U ) ) -#define FIO4PINL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x94U ) ) - -#define FIO0PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x16U ) ) -#define FIO1PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x36U ) ) -#define FIO2PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x56U ) ) -#define FIO3PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x76U ) ) -#define FIO4PINU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x96U ) ) - -#define FIO0SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) -#define FIO1SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) -#define FIO2SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) -#define FIO3SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) -#define FIO4SET0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) - -#define FIO0SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x19U ) ) -#define FIO1SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x29U ) ) -#define FIO2SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x59U ) ) -#define FIO3SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x79U ) ) -#define FIO4SET1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x99U ) ) - -#define FIO0SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) -#define FIO1SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) -#define FIO2SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) -#define FIO3SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) -#define FIO4SET2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) - -#define FIO0SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1BU ) ) -#define FIO1SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3BU ) ) -#define FIO2SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5BU ) ) -#define FIO3SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7BU ) ) -#define FIO4SET3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9BU ) ) - -#define FIO0SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x18U ) ) -#define FIO1SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x38U ) ) -#define FIO2SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x58U ) ) -#define FIO3SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x78U ) ) -#define FIO4SETL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x98U ) ) - -#define FIO0SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1AU ) ) -#define FIO1SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3AU ) ) -#define FIO2SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5AU ) ) -#define FIO3SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7AU ) ) -#define FIO4SETU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9AU ) ) - -#define FIO0CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) -#define FIO1CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) -#define FIO2CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) -#define FIO3CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) -#define FIO4CLR0 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) - -#define FIO0CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1DU ) ) -#define FIO1CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x2DU ) ) -#define FIO2CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5DU ) ) -#define FIO3CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7DU ) ) -#define FIO4CLR1 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9DU ) ) - -#define FIO0CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) -#define FIO1CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) -#define FIO2CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) -#define FIO3CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) -#define FIO4CLR2 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9EU ) ) - -#define FIO0CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x1FU ) ) -#define FIO1CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x3FU ) ) -#define FIO2CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x5FU ) ) -#define FIO3CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x7FU ) ) -#define FIO4CLR3 ( *(volatile uint8_t *) ( LPC176X_FIO_BASE_ADDR + 0x9FU ) ) - -#define FIO0CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1CU ) ) -#define FIO1CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3CU ) ) -#define FIO2CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5CU ) ) -#define FIO3CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7CU ) ) -#define FIO4CLRL ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x9CU ) ) - -#define FIO0CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x1EU ) ) -#define FIO1CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x3EU ) ) -#define FIO2CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x5EU ) ) -#define FIO3CLRU ( *(volatile uint16_t *) ( LPC176X_FIO_BASE_ADDR + 0x7EU ) ) -#define FIO4CLRU ( *(volatile uint16_t *) ( FIO_BASE_ADDR + 0x9EU ) ) - -#define LPC176X_USB_CLOCK 48000000U -#define LPC176X_MODULE_CLOCK_MASK 0x3U - -/* Pin Connect Block */ -#define PINSEL_BASE_ADDR 0x4002C000U - -#define PINSEL0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x00U ) ) -#define PINSEL1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x04U ) ) -#define PINSEL2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x08U ) ) -#define PINSEL3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x0CU ) ) -#define PINSEL4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x10U ) ) -#define PINSEL5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x14U ) ) -#define PINSEL6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x18U ) ) -#define PINSEL7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x1CU ) ) -#define PINSEL8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x20U ) ) -#define PINSEL9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x24U ) ) -#define PINSEL10 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x28U ) ) -#define PINSEL11 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x2CU ) ) - -#define PINMODE0 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x40U ) ) -#define PINMODE1 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x44U ) ) -#define PINMODE2 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x48U ) ) -#define PINMODE3 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x4CU ) ) -#define PINMODE4 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x50U ) ) -#define PINMODE5 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x54U ) ) -#define PINMODE6 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x58U ) ) -#define PINMODE7 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x5CU ) ) -#define PINMODE8 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x60U ) ) -#define PINMODE9 ( *(volatile uint32_t *) ( PINSEL_BASE_ADDR + 0x64U ) ) - -/* Pulse Width Modulator (PWM) */ -#define PWM0_BASE_ADDR 0x40014000 - -#define PWM0IR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x00 ) ) -#define PWM0TCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x04 ) ) -#define PWM0TC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x08 ) ) -#define PWM0PR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x0C ) ) -#define PWM0PC ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x10 ) ) -#define PWM0MCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x14 ) ) -#define PWM0MR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x18 ) ) -#define PWM0MR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x1C ) ) -#define PWM0MR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x20 ) ) -#define PWM0MR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x24 ) ) -#define PWM0CCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x28 ) ) -#define PWM0CR0 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x2C ) ) -#define PWM0CR1 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x30 ) ) -#define PWM0CR2 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x34 ) ) -#define PWM0CR3 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x38 ) ) -#define PWM0EMR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x3C ) ) -#define PWM0MR4 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x40 ) ) -#define PWM0MR5 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x44 ) ) -#define PWM0MR6 ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x48 ) ) -#define PWM0PCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x4C ) ) -#define PWM0LER ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x50 ) ) -#define PWM0CTCR ( *(volatile uint32_t *) ( PWM0_BASE_ADDR + 0x70 ) ) - -#define PWM1_BASE_ADDR 0x40018000 - -#define PWM1IR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x00 ) ) -#define PWM1TCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x04 ) ) -#define PWM1TC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x08 ) ) -#define PWM1PR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x0C ) ) -#define PWM1PC ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x10 ) ) -#define PWM1MCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x14 ) ) -#define PWM1MR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x18 ) ) -#define PWM1MR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x1C ) ) -#define PWM1MR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x20 ) ) -#define PWM1MR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x24 ) ) -#define PWM1CCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x28 ) ) -#define PWM1CR0 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x2C ) ) -#define PWM1CR1 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x30 ) ) -#define PWM1CR2 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x34 ) ) -#define PWM1CR3 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x38 ) ) -#define PWM1EMR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x3C ) ) -#define PWM1MR4 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x40 ) ) -#define PWM1MR5 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x44 ) ) -#define PWM1MR6 ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x48 ) ) -#define PWM1PCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x4C ) ) -#define PWM1LER ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x50 ) ) -#define PWM1CTCR ( *(volatile uint32_t *) ( PWM1_BASE_ADDR + 0x70 ) ) - -/* Universal Asynchronous Receiver Transmitter 0 (UART0) */ -#define UART0_BASE_ADDR 0x4000C000 - -#define U0RBR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) -#define U0THR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) -#define U0DLL ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x00 ) ) -#define U0DLM ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) -#define U0IER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x04 ) ) -#define U0IIR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) -#define U0FCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x08 ) ) -#define U0LCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x0C ) ) -#define U0LSR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x14 ) ) -#define U0SCR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x1C ) ) -#define U0ACR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x20 ) ) -#define U0ICR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x24 ) ) -#define U0FDR ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x28 ) ) -#define U0TER ( *(volatile uint32_t *) ( UART0_BASE_ADDR + 0x30 ) ) - -/* Universal Asynchronous Receiver Transmitter 1 (UART1) */ -#define UART1_BASE_ADDR 0x40010000 - -#define U1RBR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) -#define U1THR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) -#define U1DLL ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x00 ) ) -#define U1DLM ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) -#define U1IER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x04 ) ) -#define U1IIR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) -#define U1FCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x08 ) ) -#define U1LCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x0C ) ) -#define U1MCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x10 ) ) -#define U1LSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x14 ) ) -#define U1MSR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x18 ) ) -#define U1SCR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x1C ) ) -#define U1ACR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x20 ) ) -#define U1FDR ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x28 ) ) -#define U1TER ( *(volatile uint32_t *) ( UART1_BASE_ADDR + 0x30 ) ) - -/* Universal Asynchronous Receiver Transmitter 2 (UART2) */ -#define UART2_BASE_ADDR 0x40098000 - -#define U2RBR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) -#define U2THR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) -#define U2DLL ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x00 ) ) -#define U2DLM ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) -#define U2IER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x04 ) ) -#define U2IIR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) -#define U2FCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x08 ) ) -#define U2LCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x0C ) ) -#define U2LSR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x14 ) ) -#define U2SCR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x1C ) ) -#define U2ACR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x20 ) ) -#define U2ICR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x24 ) ) -#define U2FDR ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x28 ) ) -#define U2TER ( *(volatile uint32_t *) ( UART2_BASE_ADDR + 0x30 ) ) - -/* Universal Asynchronous Receiver Transmitter 3 (UART3) */ -#define UART3_BASE_ADDR 0x4009C000 - -#define U3RBR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) -#define U3THR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) -#define U3DLL ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x00 ) ) -#define U3DLM ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) -#define U3IER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x04 ) ) -#define U3IIR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) -#define U3FCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x08 ) ) -#define U3LCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x0C ) ) -#define U3LSR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x14 ) ) -#define U3SCR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x1C ) ) -#define U3ACR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x20 ) ) -#define U3ICR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x24 ) ) -#define U3FDR ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x28 ) ) -#define U3TER ( *(volatile uint32_t *) ( UART3_BASE_ADDR + 0x30 ) ) - -/* SPI0 (Serial Peripheral Interface 0) */ -#define SPI0_BASE_ADDR 0xE0020000 -#define S0SPCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x00 ) ) -#define S0SPSR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x04 ) ) -#define S0SPDR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x08 ) ) -#define S0SPCCR ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x0C ) ) -#define S0SPINT ( *(volatile uint32_t *) ( SPI0_BASE_ADDR + 0x1C ) ) - -/* Real Time Clock */ -#define RTC_BASE_ADDR 0x40024000 - -#define RTC_ILR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x00 ) ) -#define RTC_CTC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x04 ) ) -#define RTC_CCR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x08 ) ) -#define RTC_CIIR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x0C ) ) -#define RTC_AMR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x10 ) ) -#define RTC_CTIME0 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x14 ) ) -#define RTC_CTIME1 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x18 ) ) -#define RTC_CTIME2 ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x1C ) ) -#define RTC_SEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x20 ) ) -#define RTC_MIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x24 ) ) -#define RTC_HOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x28 ) ) -#define RTC_DOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x2C ) ) -#define RTC_DOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x30 ) ) -#define RTC_DOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x34 ) ) -#define RTC_MONTH ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x38 ) ) -#define RTC_YEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x3C ) ) -#define RTC_CISS ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x40 ) ) -#define RTC_ALSEC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x60 ) ) -#define RTC_ALMIN ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x64 ) ) -#define RTC_ALHOUR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x68 ) ) -#define RTC_ALDOM ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x6C ) ) -#define RTC_ALDOW ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x70 ) ) -#define RTC_ALDOY ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x74 ) ) -#define RTC_ALMON ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x78 ) ) -#define RTC_ALYEAR ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x7C ) ) -#define RTC_PREINT ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x80 ) ) -#define RTC_PREFRAC ( *(volatile uint32_t *) ( RTC_BASE_ADDR + 0x84 ) ) - -/* A/D Converter 0 (AD0) */ -#define AD0_BASE_ADDR 0x40034000 - -#define AD0CR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x00 ) ) -#define AD0GDR ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x04 ) ) -#define AD0INTEN ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x0C ) ) -#define AD0_DATA_START ( (volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) -#define AD0DR0 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x10 ) ) -#define AD0DR1 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x14 ) ) -#define AD0DR2 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x18 ) ) -#define AD0DR3 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x1C ) ) -#define AD0DR4 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x20 ) ) -#define AD0DR5 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x24 ) ) -#define AD0DR6 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x28 ) ) -#define AD0DR7 ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x2C ) ) -#define AD0STAT ( *(volatile uint32_t *) ( AD0_BASE_ADDR + 0x30 ) ) - -/* D/A Converter */ -#define DAC_BASE_ADDR 0x4008C000 - -#define DACR ( *(volatile uint32_t *) ( DAC_BASE_ADDR + 0x00 ) ) - -/* CAN CONTROLLERS AND ACCEPTANCE FILTER */ -#define CAN_ACCEPT_BASE_ADDR 0x4003C000 - -#define CAN_AFMR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x00 ) ) -#define CAN_SFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x04 ) ) -#define CAN_SFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ - 0x08 ) ) -#define CAN_EFF_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x0C ) ) -#define CAN_EFF_GRP_SA ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ - 0x10 ) ) -#define CAN_EOT ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x14 ) ) -#define CAN_LUT_ERR_ADR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + \ - 0x18 ) ) -#define CAN_LUT_ERR ( *(volatile uint32_t *) ( CAN_ACCEPT_BASE_ADDR + 0x1C ) ) - -#define CAN_CENTRAL_BASE_ADDR 0x40040000 - -#define CAN_TX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x00 ) ) -#define CAN_RX_SR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x04 ) ) -#define CAN_MSR ( *(volatile uint32_t *) ( CAN_CENTRAL_BASE_ADDR + 0x08 ) ) - -#define CAN1_BASE_ADDR 0x40044000 - -#define CAN1MOD ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x00 ) ) -#define CAN1CMR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x04 ) ) -#define CAN1GSR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x08 ) ) -#define CAN1ICR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x0C ) ) -#define CAN1IER ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x10 ) ) -#define CAN1BTR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x14 ) ) -#define CAN1EWL ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x18 ) ) -#define CAN1SR ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x1C ) ) -#define CAN1RFS ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x20 ) ) -#define CAN1RID ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x24 ) ) -#define CAN1RDA ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x28 ) ) -#define CAN1RDB ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x2C ) ) - -#define CAN1TFI1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x30 ) ) -#define CAN1TID1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x34 ) ) -#define CAN1TDA1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x38 ) ) -#define CAN1TDB1 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x3C ) ) -#define CAN1TFI2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x40 ) ) -#define CAN1TID2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x44 ) ) -#define CAN1TDA2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x48 ) ) -#define CAN1TDB2 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x4C ) ) -#define CAN1TFI3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x50 ) ) -#define CAN1TID3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x54 ) ) -#define CAN1TDA3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x58 ) ) -#define CAN1TDB3 ( *(volatile uint32_t *) ( CAN1_BASE_ADDR + 0x5C ) ) - -#define CAN2_BASE_ADDR 0x40048000 - -#define CAN2MOD ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x00 ) ) -#define CAN2CMR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x04 ) ) -#define CAN2GSR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x08 ) ) -#define CAN2ICR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x0C ) ) -#define CAN2IER ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x10 ) ) -#define CAN2BTR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x14 ) ) -#define CAN2EWL ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x18 ) ) -#define CAN2SR ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x1C ) ) -#define CAN2RFS ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x20 ) ) -#define CAN2RID ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x24 ) ) -#define CAN2RDA ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x28 ) ) -#define CAN2RDB ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x2C ) ) - -#define CAN2TFI1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x30 ) ) -#define CAN2TID1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x34 ) ) -#define CAN2TDA1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x38 ) ) -#define CAN2TDB1 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x3C ) ) -#define CAN2TFI2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x40 ) ) -#define CAN2TID2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x44 ) ) -#define CAN2TDA2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x48 ) ) -#define CAN2TDB2 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x4C ) ) -#define CAN2TFI3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x50 ) ) -#define CAN2TID3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x54 ) ) -#define CAN2TDA3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x58 ) ) -#define CAN2TDB3 ( *(volatile uint32_t *) ( CAN2_BASE_ADDR + 0x5C ) ) - -/* MultiMedia Card Interface(MCI) Controller */ -#define MCI_BASE_ADDR 0x400c0000 - -#define MCI_POWER ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x00 ) ) -#define MCI_CLOCK ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x04 ) ) -#define MCI_ARGUMENT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x08 ) ) -#define MCI_COMMAND ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x0C ) ) -#define MCI_RESP_CMD ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x10 ) ) -#define MCI_RESP0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x14 ) ) -#define MCI_RESP1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x18 ) ) -#define MCI_RESP2 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x1C ) ) -#define MCI_RESP3 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x20 ) ) -#define MCI_DATA_TMR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x24 ) ) -#define MCI_DATA_LEN ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x28 ) ) -#define MCI_DATA_CTRL ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x2C ) ) -#define MCI_DATA_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x30 ) ) -#define MCI_STATUS ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x34 ) ) -#define MCI_CLEAR ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x38 ) ) -#define MCI_MASK0 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x3C ) ) -#define MCI_MASK1 ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x40 ) ) -#define MCI_FIFO_CNT ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x48 ) ) -#define MCI_FIFO ( *(volatile uint32_t *) ( MCI_BASE_ADDR + 0x80 ) ) - -/* I2S Interface Controller (I2S) */ -#define I2S_BASE_ADDR 0x400a8000 - -#define I2S_DAO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x00 ) ) -#define I2S_DAI ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x04 ) ) -#define I2S_TX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x08 ) ) -#define I2S_RX_FIFO ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x0C ) ) -#define I2S_STATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x10 ) ) -#define I2S_DMA1 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x14 ) ) -#define I2S_DMA2 ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x18 ) ) -#define I2S_IRQ ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x1C ) ) -#define I2S_TXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x20 ) ) -#define I2S_RXRATE ( *(volatile uint32_t *) ( I2S_BASE_ADDR + 0x24 ) ) - -/* General-purpose DMA Controller */ -#define DMA_BASE_ADDR 0x50004000 - -#define GPDMA_INT_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x000 ) ) -#define GPDMA_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x004 ) ) -#define GPDMA_INT_TCCLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x008 ) ) -#define GPDMA_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x00C ) ) -#define GPDMA_INT_ERR_CLR ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x010 ) ) -#define GPDMA_RAW_INT_TCSTAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ - 0x014 ) ) -#define GPDMA_RAW_INT_ERR_STAT ( *(volatile uint32_t *) ( DMA_BASE_ADDR + \ - 0x018 ) ) -#define GPDMA_ENABLED_CHNS ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x01C ) ) -#define GPDMA_SOFT_BREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x020 ) ) -#define GPDMA_SOFT_SREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x024 ) ) -#define GPDMA_SOFT_LBREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x028 ) ) -#define GPDMA_SOFT_LSREQ ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x02C ) ) -#define GPDMA_CONFIG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x030 ) ) -#define GPDMA_SYNC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x034 ) ) - -/* DMA channel 0 registers */ -#define GPDMA_CH0_BASE_ADDR ( DMA_BASE_ADDR + 0x100 ) -#define GPDMA_CH0_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x100 ) ) -#define GPDMA_CH0_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x104 ) ) -#define GPDMA_CH0_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x108 ) ) -#define GPDMA_CH0_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x10C ) ) -#define GPDMA_CH0_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x110 ) ) - -/* DMA channel 1 registers */ -#define GPDMA_CH1_BASE_ADDR ( DMA_BASE_ADDR + 0x120 ) -#define GPDMA_CH1_SRC ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x120 ) ) -#define GPDMA_CH1_DEST ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x124 ) ) -#define GPDMA_CH1_LLI ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x128 ) ) -#define GPDMA_CH1_CTRL ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x12C ) ) -#define GPDMA_CH1_CFG ( *(volatile uint32_t *) ( DMA_BASE_ADDR + 0x130 ) ) - -/* USB Controller */ -#define USB_INT_BASE_ADDR 0x400fc1c0 -#define USB_BASE_ADDR 0x2008c200 - -#define USB_INT_STAT ( *(volatile uint32_t *) ( USB_INT_BASE_ADDR + 0x00 ) ) - -/* USB Device Interrupt Registers */ -#define DEV_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x00 ) ) -#define DEV_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x04 ) ) -#define DEV_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x08 ) ) -#define DEV_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x0C ) ) -#define DEV_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x2C ) ) - -/* USB Device Endpoint Interrupt Registers */ -#define EP_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x30 ) ) -#define EP_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x34 ) ) -#define EP_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x38 ) ) -#define EP_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x3C ) ) -#define EP_INT_PRIO ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x40 ) ) - -/* USB Device Endpoint Realization Registers */ -#define REALIZE_EP ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x44 ) ) -#define EP_INDEX ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x48 ) ) -#define MAXPACKET_SIZE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x4C ) ) - -/* USB Device Command Reagisters */ -#define CMD_CODE ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x10 ) ) -#define CMD_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x14 ) ) - -/* USB Device Data Transfer Registers */ -#define RX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x18 ) ) -#define TX_DATA ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x1C ) ) -#define RX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x20 ) ) -#define TX_PLENGTH ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x24 ) ) -#define USB_CTRL ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x28 ) ) - -/* USB Device DMA Registers */ -#define DMA_REQ_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x50 ) ) -#define DMA_REQ_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x54 ) ) -#define DMA_REQ_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x58 ) ) -#define UDCA_HEAD ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x80 ) ) -#define EP_DMA_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x84 ) ) -#define EP_DMA_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x88 ) ) -#define EP_DMA_DIS ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x8C ) ) -#define DMA_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x90 ) ) -#define DMA_INT_EN ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0x94 ) ) -#define EOT_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA0 ) ) -#define EOT_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA4 ) ) -#define EOT_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xA8 ) ) -#define NDD_REQ_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xAC ) ) -#define NDD_REQ_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB0 ) ) -#define NDD_REQ_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB4 ) ) -#define SYS_ERR_INT_STAT ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xB8 ) ) -#define SYS_ERR_INT_CLR ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xBC ) ) -#define SYS_ERR_INT_SET ( *(volatile uint32_t *) ( USB_BASE_ADDR + 0xC0 ) ) - -/* USB Host Controller */ -#define USBHC_BASE_ADDR 0x2008c000 - -#define HC_REVISION ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x00 ) ) -#define HC_CONTROL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x04 ) ) -#define HC_CMD_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x08 ) ) -#define HC_INT_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x0C ) ) -#define HC_INT_EN ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x10 ) ) -#define HC_INT_DIS ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x14 ) ) -#define HC_HCCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x18 ) ) -#define HC_PERIOD_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x1C ) ) -#define HC_CTRL_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x20 ) ) -#define HC_CTRL_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x24 ) ) -#define HC_BULK_HEAD_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x28 ) ) -#define HC_BULK_CUR_ED ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x2C ) ) -#define HC_DONE_HEAD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x30 ) ) -#define HC_FM_INTERVAL ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x34 ) ) -#define HC_FM_REMAINING ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x38 ) ) -#define HC_FM_NUMBER ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x3C ) ) -#define HC_PERIOD_START ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x40 ) ) -#define HC_LS_THRHLD ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x44 ) ) -#define HC_RH_DESCA ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x48 ) ) -#define HC_RH_DESCB ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x4C ) ) -#define HC_RH_STAT ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x50 ) ) -#define HC_RH_PORT_STAT1 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x54 ) ) -#define HC_RH_PORT_STAT2 ( *(volatile uint32_t *) ( USBHC_BASE_ADDR + 0x58 ) ) - -/* USB OTG Controller */ -#define USBOTG_BASE_ADDR 0x2008c100 - -#define OTG_INT_STAT ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x00 ) ) -#define OTG_INT_EN ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x04 ) ) -#define OTG_INT_SET ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x08 ) ) -#define OTG_INT_CLR ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x0C ) ) -#define OTG_STAT_CTRL ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x10 ) ) -#define OTG_TIMER ( *(volatile uint32_t *) ( USBOTG_BASE_ADDR + 0x14 ) ) - -#define USBOTG_I2C_BASE_ADDR 0x2008c300 - -#define OTG_I2C_RX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) -#define OTG_I2C_TX ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x00 ) ) -#define OTG_I2C_STS ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x04 ) ) -#define OTG_I2C_CTL ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + 0x08 ) ) -#define OTG_I2C_CLKHI ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ - 0x0C ) ) -#define OTG_I2C_CLKLO ( *(volatile uint32_t *) ( USBOTG_I2C_BASE_ADDR + \ - 0x10 ) ) - -#define USBOTG_CLK_BASE_ADDR 0x2008CFF0U - -#define OTG_CLK_CTRL ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ - 0x04U ) ) -#define OTG_CLK_STAT ( *(volatile uint32_t *) ( USBOTG_CLK_BASE_ADDR + \ - 0x08U ) ) - -/* Register Fields */ -#define GET_FIELD( val, mask, shift ) \ - ( ( ( val ) & ( mask ) ) >> ( shift ) ) - -#define SET_FIELD( val, field, mask, shift ) \ - ( ( ( val ) & ~( mask ) ) | ( ( ( field ) << ( shift ) ) & ( mask ) ) ) - -/* CLKSRCSEL */ -#define CLKSRCSEL_CLKSRC_MASK 0x00000003U - -#define GET_CLKSRCSEL_CLKSRC( reg ) \ - GET_FIELD( reg, CLKSRCSEL_CLKSRC_MASK, 0 ) - -#define SET_CLKSRCSEL_CLKSRC( reg, val ) \ - SET_FIELD( reg, val, CLKSRCSEL_CLKSRC_MASK, 0 ) - -/* PLLCON */ -#define PLLCON_PLLE 0x00000001U - -#define PLLCON_PLLC 0x00000002U - -/* PLLCFG */ -#define PLLCFG_MSEL_MASK 0x00007fffU - -#define GET_PLLCFG_MSEL( reg ) \ - GET_FIELD( reg, PLLCFG_MSEL_MASK, 0 ) - -#define SET_PLLCFG_MSEL( reg, val ) \ - SET_FIELD( reg, val, PLLCFG_MSEL_MASK, 0 ) - -#define PLLCFG_NSEL_MASK 0x00ff0000U - -#define GET_PLLCFG_NSEL( reg ) \ - GET_FIELD( reg, PLLCFG_NSEL_MASK, 16 ) - -#define SET_PLLCFG_NSEL( reg, val ) \ - SET_FIELD( reg, val, PLLCFG_NSEL_MASK, 16 ) - -/* PLLSTAT */ -#define PLLSTAT_MSEL_MASK 0x00007fffU - -#define GET_PLLSTAT_MSEL( reg ) \ - GET_FIELD( reg, PLLSTAT_MSEL_MASK, 0 ) - -#define SET_PLLSTAT_MSEL( reg, val ) \ - SET_FIELD( reg, val, PLLSTAT_MSEL_MASK, 0 ) - -#define PLLSTAT_NSEL_MASK 0x00ff0000U - -#define GET_PLLSTAT_NSEL( reg ) \ - GET_FIELD( reg, PLLSTAT_NSEL_MASK, 16 ) - -#define SET_PLLSTAT_NSEL( reg, val ) \ - SET_FIELD( reg, val, PLLSTAT_NSEL_MASK, 16 ) - -#define PLLSTAT_PLLE 0x01000000U - -#define PLLSTAT_PLLC 0x02000000U - -#define PLLSTAT_PLOCK 0x04000000U - -/* CCLKCFG */ -#define CCLKCFG_CCLKSEL_MASK 0x000000ffU - -#define GET_CCLKCFG_CCLKSEL( reg ) \ - GET_FIELD( reg, CCLKCFG_CCLKSEL_MASK, 0 ) - -#define SET_CCLKCFG_CCLKSEL( reg, val ) \ - SET_FIELD( reg, val, CCLKCFG_CCLKSEL_MASK, 0 ) - -/* MEMMAP */ -#define MEMMAP_MAP_MASK 0x00000003U - -#define GET_MEMMAP_MAP( reg ) \ - GET_FIELD( reg, MEMMAP_MAP_MASK, 0 ) - -#define SET_MEMMAP_MAP( reg, val ) \ - SET_FIELD( reg, val, MEMMAP_MAP_MASK, 0 ) - -/* TIR */ -#define TIR_MR0 0x00000001U -#define TIR_MR1 0x00000002U -#define TIR_MR2 0x00000004U -#define TIR_MR3 0x00000008U -#define TIR_CR0 0x00000010U -#define TIR_CR1 0x00000020U -#define TIR_CR2 0x00000040U -#define TIR_CR3 0x00000080U - -/* TCR */ -#define TCR_EN 0x00000001U -#define TCR_RST 0x00000002U - -/* TMCR */ -#define TMCR_MR0I 0x00000001U -#define TMCR_MR0R 0x00000002U -#define TMCR_MR0S 0x00000004U -#define TMCR_MR1I 0x00000008U -#define TMCR_MR1R 0x00000010U -#define TMCR_MR1S 0x00000020U -#define TMCR_MR2I 0x00000040U -#define TMCR_MR2R 0x00000080U -#define TMCR_MR2S 0x00000100U -#define TMCR_MR3I 0x00000200U -#define TMCR_MR3R 0x00000400U -#define TMCR_MR3S 0x00000800U - -/* PCLKSEL0 */ -#define PCLKSEL0_PCLK_WDT_MASK 0x00000003U - -#define GET_PCLKSEL0_PCLK_WDT( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_WDT_MASK, 0 ) - -#define SET_PCLKSEL0_PCLK_WDT( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_WDT_MASK, 0 ) - -#define PCLKSEL0_PCLK_TIMER0_MASK 0x0000000cU - -#define GET_PCLKSEL0_PCLK_TIMER0( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) - -#define SET_PCLKSEL0_PCLK_TIMER0( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER0_MASK, 2 ) - -#define PCLKSEL0_PCLK_TIMER1_MASK 0x00000030U - -#define GET_PCLKSEL0_PCLK_TIMER1( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) - -#define SET_PCLKSEL0_PCLK_TIMER1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_TIMER1_MASK, 4 ) - -#define PCLKSEL0_PCLK_UART0_MASK 0x000000c0U - -#define GET_PCLKSEL0_PCLK_UART0( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_UART0_MASK, 6 ) - -#define SET_PCLKSEL0_PCLK_UART0( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_UART0_MASK, 6 ) - -#define PCLKSEL0_PCLK_UART1_MASK 0x00000300U - -#define GET_PCLKSEL0_PCLK_UART1( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_UART1_MASK, 8 ) - -#define SET_PCLKSEL0_PCLK_UART1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_UART1_MASK, 8 ) - -#define PCLKSEL0_PCLK_PWM0_MASK 0x00000c00U - -#define GET_PCLKSEL0_PCLK_PWM0( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_PWM0_MASK, 10 ) - -#define SET_PCLKSEL0_PCLK_PWM0( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM0_MASK, 10 ) - -#define PCLKSEL0_PCLK_PWM1_MASK 0x00003000U - -#define GET_PCLKSEL0_PCLK_PWM1( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_PWM1_MASK, 12 ) - -#define SET_PCLKSEL0_PCLK_PWM1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_PWM1_MASK, 12 ) - -#define PCLKSEL0_PCLK_I2C0_MASK 0x0000c000U - -#define GET_PCLKSEL0_PCLK_I2C0( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_I2C0_MASK, 14 ) - -#define SET_PCLKSEL0_PCLK_I2C0( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_I2C0_MASK, 14 ) - -#define PCLKSEL0_PCLK_SPI_MASK 0x00030000U - -#define GET_PCLKSEL0_PCLK_SPI( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_SPI_MASK, 16 ) - -#define SET_PCLKSEL0_PCLK_SPI( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_SPI_MASK, 16 ) - -#define PCLKSEL0_PCLK_RTC_MASK 0x000c0000U - -#define GET_PCLKSEL0_PCLK_RTC( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_RTC_MASK, 18 ) - -#define SET_PCLKSEL0_PCLK_RTC( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_RTC_MASK, 18 ) - -#define PCLKSEL0_PCLK_SSP1_MASK 0x00300000U - -#define GET_PCLKSEL0_PCLK_SSP1( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_SSP1_MASK, 20 ) - -#define SET_PCLKSEL0_PCLK_SSP1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_SSP1_MASK, 20 ) - -#define PCLKSEL0_PCLK_DAC_MASK 0x00c00000U - -#define GET_PCLKSEL0_PCLK_DAC( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_DAC_MASK, 22 ) - -#define SET_PCLKSEL0_PCLK_DAC( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_DAC_MASK, 22 ) - -#define PCLKSEL0_PCLK_ADC_MASK 0x03000000U - -#define GET_PCLKSEL0_PCLK_ADC( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_ADC_MASK, 24 ) - -#define SET_PCLKSEL0_PCLK_ADC( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_ADC_MASK, 24 ) - -#define PCLKSEL0_PCLK_CAN1_MASK 0x0c000000U - -#define GET_PCLKSEL0_PCLK_CAN1( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_CAN1_MASK, 26 ) - -#define SET_PCLKSEL0_PCLK_CAN1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN1_MASK, 26 ) - -#define PCLKSEL0_PCLK_CAN2_MASK 0x30000000U - -#define GET_PCLKSEL0_PCLK_CAN2( reg ) \ - GET_FIELD( reg, PCLKSEL0_PCLK_CAN2_MASK, 28 ) - -#define SET_PCLKSEL0_PCLK_CAN2( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL0_PCLK_CAN2_MASK, 28 ) - -/* PCLKSEL1 */ -#define PCLKSEL1_PCLK_BAT_RAM_MASK 0x00000003U - -#define GET_PCLKSEL1_PCLK_BAT_RAM( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) - -#define SET_PCLKSEL1_PCLK_BAT_RAM( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_BAT_RAM_MASK, 0 ) - -#define PCLKSEL1_PCLK_GPIO_MASK 0x0000000cU - -#define GET_PCLKSEL1_PCLK_GPIO( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_GPIO_MASK, 2 ) - -#define SET_PCLKSEL1_PCLK_GPIO( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_GPIO_MASK, 2 ) - -#define PCLKSEL1_PCLK_PCB_MASK 0x00000030U - -#define GET_PCLKSEL1_PCLK_PCB( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_PCB_MASK, 4 ) - -#define SET_PCLKSEL1_PCLK_PCB( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_PCB_MASK, 4 ) - -#define PCLKSEL1_PCLK_I2C1_MASK 0x000000c0U - -#define GET_PCLKSEL1_PCLK_I2C1( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_I2C1_MASK, 6 ) - -#define SET_PCLKSEL1_PCLK_I2C1( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C1_MASK, 6 ) - -#define PCLKSEL1_PCLK_SSP0_MASK 0x00000c00U - -#define GET_PCLKSEL1_PCLK_SSP0( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_SSP0_MASK, 10 ) - -#define SET_PCLKSEL1_PCLK_SSP0( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_SSP0_MASK, 10 ) - -#define PCLKSEL1_PCLK_TIMER2_MASK 0x00003000U - -#define GET_PCLKSEL1_PCLK_TIMER2( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) - -#define SET_PCLKSEL1_PCLK_TIMER2( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER2_MASK, 12 ) - -#define PCLKSEL1_PCLK_TIMER3_MASK 0x0000c000U - -#define GET_PCLKSEL1_PCLK_TIMER3( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) - -#define SET_PCLKSEL1_PCLK_TIMER3( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_TIMER3_MASK, 14 ) - -#define PCLKSEL1_PCLK_UART2_MASK 0x00030000U - -#define GET_PCLKSEL1_PCLK_UART2( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_UART2_MASK, 16 ) - -#define SET_PCLKSEL1_PCLK_UART2( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_UART2_MASK, 16 ) - -#define PCLKSEL1_PCLK_UART3_MASK 0x000c0000U - -#define GET_PCLKSEL1_PCLK_UART3( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_UART3_MASK, 18 ) - -#define SET_PCLKSEL1_PCLK_UART3( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_UART3_MASK, 18 ) - -#define PCLKSEL1_PCLK_I2C2_MASK 0x00300000U - -#define GET_PCLKSEL1_PCLK_I2C2( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_I2C2_MASK, 20 ) - -#define SET_PCLKSEL1_PCLK_I2C2( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_I2C2_MASK, 20 ) - -#define PCLKSEL1_PCLK_I2S_MASK 0x00c00000U - -#define GET_PCLKSEL1_PCLK_I2S( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_I2S_MASK, 22 ) - -#define SET_PCLKSEL1_PCLK_I2S( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_I2S_MASK, 22 ) - -#define PCLKSEL1_PCLK_MCI_MASK 0x03000000U - -#define GET_PCLKSEL1_PCLK_MCI( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_MCI_MASK, 24 ) - -#define SET_PCLKSEL1_PCLK_MCI( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_MCI_MASK, 24 ) - -#define PCLKSEL1_PCLK_SYSCON_MASK 0x30000000U - -#define GET_PCLKSEL1_PCLK_SYSCON( reg ) \ - GET_FIELD( reg, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) - -#define SET_PCLKSEL1_PCLK_SYSCON( reg, val ) \ - SET_FIELD( reg, val, PCLKSEL1_PCLK_SYSCON_MASK, 28 ) - -/* RTC_ILR */ -#define RTC_ILR_RTCCIF 0x00000001U -#define RTC_ILR_RTCALF 0x00000002U -#define RTC_ILR_RTSSF 0x00000004U - -/* RTC_CCR */ -#define RTC_CCR_CLKEN 0x00000001U -#define RTC_CCR_CTCRST 0x00000002U -#define RTC_CCR_CLKSRC 0x00000010U - -/* GPDMA */ -typedef struct { - uint32_t src; - uint32_t dest; - uint32_t lli; - uint32_t ctrl; -} lpc176x_dma_descriptor; - -typedef struct { - lpc176x_dma_descriptor desc; - uint32_t cfg; -} lpc176x_dma_channel; - -#define GPDMA_CH_NUMBER 2 -#define GPDMA_STATUS_CH_0 0x00000001U -#define GPDMA_STATUS_CH_1 0x00000002U -#define GPDMA_CH_BASE_ADDR( i ) \ - ( (volatile lpc176x_dma_channel *) \ - ( ( i ) ? GPDMA_CH1_BASE_ADDR : GPDMA_CH0_BASE_ADDR ) ) - -/* GPDMA_CONFIG */ -#define GPDMA_CONFIG_EN 0x00000001U -#define GPDMA_CONFIG_MODE 0x00000002U - -/* GPDMA_ENABLED_CHNS */ -#define GPDMA_ENABLED_CHNS_CH0 0x00000001U -#define GPDMA_ENABLED_CHNS_CH1 0x00000002U - -/* GPDMA_CH_CTRL */ -#define GPDMA_CH_CTRL_TSZ_MASK 0x00000fffU - -#define GET_GPDMA_CH_CTRL_TSZ( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_TSZ_MASK, 0 ) - -#define SET_GPDMA_CH_CTRL_TSZ( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_TSZ_MASK, 0 ) - -#define GPDMA_CH_CTRL_TSZ_MAX 0x00000fffU - -#define GPDMA_CH_CTRL_SBSZ_MASK 0x00007000U - -#define GET_GPDMA_CH_CTRL_SBSZ( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) - -#define SET_GPDMA_CH_CTRL_SBSZ( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_SBSZ_MASK, 12 ) - -#define GPDMA_CH_CTRL_DBSZ_MASK 0x00038000U - -#define GET_GPDMA_CH_CTRL_DBSZ( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) - -#define SET_GPDMA_CH_CTRL_DBSZ( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_DBSZ_MASK, 15 ) - -#define GPDMA_CH_CTRL_BSZ_1 0x00000000U - -#define GPDMA_CH_CTRL_BSZ_4 0x00000001U - -#define GPDMA_CH_CTRL_BSZ_8 0x00000002U - -#define GPDMA_CH_CTRL_BSZ_16 0x00000003U - -#define GPDMA_CH_CTRL_BSZ_32 0x00000004U - -#define GPDMA_CH_CTRL_BSZ_64 0x00000005U - -#define GPDMA_CH_CTRL_BSZ_128 0x00000006U - -#define GPDMA_CH_CTRL_BSZ_256 0x00000007U - -#define GPDMA_CH_CTRL_SW_MASK 0x001c0000U - -#define GET_GPDMA_CH_CTRL_SW( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_SW_MASK, 18 ) - -#define SET_GPDMA_CH_CTRL_SW( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_SW_MASK, 18 ) - -#define GPDMA_CH_CTRL_DW_MASK 0x00e00000U - -#define GET_GPDMA_CH_CTRL_DW( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_DW_MASK, 21 ) - -#define SET_GPDMA_CH_CTRL_DW( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_DW_MASK, 21 ) - -#define GPDMA_CH_CTRL_W_8 0x00000000U - -#define GPDMA_CH_CTRL_W_16 0x00000001U - -#define GPDMA_CH_CTRL_W_32 0x00000002U - -#define GPDMA_CH_CTRL_SI 0x04000000U - -#define GPDMA_CH_CTRL_DI 0x08000000U - -#define GPDMA_CH_CTRL_PROT_MASK 0x70000000U - -#define GET_GPDMA_CH_CTRL_PROT( reg ) \ - GET_FIELD( reg, GPDMA_CH_CTRL_PROT_MASK, 28 ) - -#define SET_GPDMA_CH_CTRL_PROT( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CTRL_PROT_MASK, 28 ) - -#define GPDMA_CH_CTRL_ITC 0x80000000U - -/* GPDMA_CH_CFG */ -#define GPDMA_CH_CFG_EN 0x00000001U - -#define GPDMA_CH_CFG_SRCPER_MASK 0x0000001eU - -#define GET_GPDMA_CH_CFG_SRCPER( reg ) \ - GET_FIELD( reg, GPDMA_CH_CFG_SRCPER_MASK, 1 ) - -#define SET_GPDMA_CH_CFG_SRCPER( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CFG_SRCPER_MASK, 1 ) - -#define GPDMA_CH_CFG_DESTPER_MASK 0x000003c0U - -#define GET_GPDMA_CH_CFG_DESTPER( reg ) \ - GET_FIELD( reg, GPDMA_CH_CFG_DESTPER_MASK, 6 ) - -#define SET_GPDMA_CH_CFG_DESTPER( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CFG_DESTPER_MASK, 6 ) - -#define GPDMA_CH_CFG_PER_SSP0_TX 0x00000000U - -#define GPDMA_CH_CFG_PER_SSP0_RX 0x00000001U - -#define GPDMA_CH_CFG_PER_SSP1_TX 0x00000002U - -#define GPDMA_CH_CFG_PER_SSP1_RX 0x00000003U - -#define GPDMA_CH_CFG_PER_SD_MMC 0x00000004U - -#define GPDMA_CH_CFG_PER_I2S_CH0 0x00000005U - -#define GPDMA_CH_CFG_PER_I2S_CH1 0x00000006U - -#define GPDMA_CH_CFG_FLOW_MASK 0x00003800U - -#define GET_GPDMA_CH_CFG_FLOW( reg ) \ - GET_FIELD( reg, GPDMA_CH_CFG_FLOW_MASK, 11 ) - -#define SET_GPDMA_CH_CFG_FLOW( reg, val ) \ - SET_FIELD( reg, val, GPDMA_CH_CFG_FLOW_MASK, 11 ) - -#define GPDMA_CH_CFG_FLOW_MEM_TO_MEM_DMA 0x00000000U - -#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_DMA 0x00000001U - -#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_DMA 0x00000002U - -#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DMA 0x00000003U - -#define GPDMA_CH_CFG_FLOW_PER_TO_PER_DEST 0x00000004U - -#define GPDMA_CH_CFG_FLOW_MEM_TO_PER_PER 0x00000005U - -#define GPDMA_CH_CFG_FLOW_PER_TO_MEM_PER 0x00000006U - -#define GPDMA_CH_CFG_FLOW_PER_TO_PER_SRC 0x00000007U - -#define GPDMA_CH_CFG_IE 0x00004000U - -#define GPDMA_CH_CFG_ITC 0x00008000U - -#define GPDMA_CH_CFG_LOCK 0x00010000U - -#define GPDMA_CH_CFG_ACTIVE 0x00020000U - -#define GPDMA_CH_CFG_HALT 0x00040000U - -/* AHBCFG */ -#define AHBCFG_SCHEDULER_UNIFORM 0x00000001U - -#define AHBCFG_BREAK_BURST_MASK 0x00000006U - -#define GET_AHBCFG_BREAK_BURST( reg ) \ - GET_FIELD( reg, AHBCFG_BREAK_BURST_MASK, 1 ) - -#define SET_AHBCFG_BREAK_BURST( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_BREAK_BURST_MASK, 1 ) - -#define AHBCFG_QUANTUM_BUS_CYCLE 0x00000008U - -#define AHBCFG_QUANTUM_SIZE_MASK 0x000000f0U - -#define GET_AHBCFG_QUANTUM_SIZE( reg ) \ - GET_FIELD( reg, AHBCFG_QUANTUM_SIZE_MASK, 4 ) - -#define SET_AHBCFG_QUANTUM_SIZE( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_QUANTUM_SIZE_MASK, 4 ) - -#define AHBCFG_DEFAULT_MASTER_MASK 0x00000700U - -#define GET_AHBCFG_DEFAULT_MASTER( reg ) \ - GET_FIELD( reg, AHBCFG_DEFAULT_MASTER_MASK, 8 ) - -#define SET_AHBCFG_DEFAULT_MASTER( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_DEFAULT_MASTER_MASK, 8 ) - -#define AHBCFG_EP1_MASK 0x00007000U - -#define GET_AHBCFG_EP1( reg ) \ - GET_FIELD( reg, AHBCFG_EP1_MASK, 12 ) - -#define SET_AHBCFG_EP1( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_EP1_MASK, 12 ) - -#define AHBCFG_EP2_MASK 0x00070000U - -#define GET_AHBCFG_EP2( reg ) \ - GET_FIELD( reg, AHBCFG_EP2_MASK, 16 ) - -#define SET_AHBCFG_EP2( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_EP2_MASK, 16 ) - -#define AHBCFG_EP3_MASK 0x00700000U - -#define GET_AHBCFG_EP3( reg ) \ - GET_FIELD( reg, AHBCFG_EP3_MASK, 20 ) - -#define SET_AHBCFG_EP3( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_EP3_MASK, 20 ) - -#define AHBCFG_EP4_MASK 0x07000000U - -#define GET_AHBCFG_EP4( reg ) \ - GET_FIELD( reg, AHBCFG_EP4_MASK, 24 ) - -#define SET_AHBCFG_EP4( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_EP4_MASK, 24 ) - -#define AHBCFG_EP5_MASK 0x70000000U - -#define GET_AHBCFG_EP5( reg ) \ - GET_FIELD( reg, AHBCFG_EP5_MASK, 28 ) - -#define SET_AHBCFG_EP5( reg, val ) \ - SET_FIELD( reg, val, AHBCFG_EP5_MASK, 28 ) - -/* I2S */ -static volatile lpc_i2s * const lpc176x_i2s = (lpc_i2s *) I2S_BASE_ADDR; - -/* ADC */ -#define ADC_CR_SEL( val ) BSP_FLD32( val, 0, 7 ) -#define ADC_CR_SEL_GET( val ) BSP_FLD32GET( val, 0, 7 ) -#define ADC_CR_SEL_SET( reg, val ) BSP_FLD32SET( reg, val, 0, 7 ) -#define ADC_CR_CLKDIV( val ) BSP_FLD32( val, 8, 15 ) -#define ADC_CR_CLKDIV_GET( reg ) BSP_FLD32GET( reg, 8, 15 ) -#define ADC_CR_CLKDIV_SET( reg, val ) BSP_FLD32SET( reg, val, 8, 15 ) -#define ADC_CR_BURST BSP_BIT32( 16 ) -#define ADC_CR_CLKS( val ) BSP_FLD32( val, 17, 19 ) -#define ADC_CR_PDN BSP_BIT32( 21 ) -#define ADC_CR_START( val ) BSP_FLD32( val, 24, 26 ) -#define ADC_CR_EDGE BSP_BIT32( 27 ) - -#define ADC_DR_VALUE( reg ) BSP_FLD32GET( reg, 6, 15 ) -#define ADC_DR_OVERRUN BSP_BIT32( 30 ) -#define ADC_DR_DONE BSP_BIT32( 31 ) - -/* DAC */ -#define DAC_STEPS 1024 -#define DAC_VALUE( val ) BSP_FLD32( val, 6, 15 ) -#define DAC_BIAS BSP_BIT32( 16 ) - -#endif /* LIBBSP_ARM_LPC176X_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/mbed-pinmap.h b/c/src/lib/libbsp/arm/lpc176x/include/mbed-pinmap.h deleted file mode 100755 index 3556bc5fbf..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/mbed-pinmap.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file mbed-pinmap.h - * - * @ingroup lpc176x - * - * @brief Pins of the mbed lpc1768 - * See http://mbed.org/media/uploads/chris/mbed-005.1.pdf for references - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#define DIP5 9U -#define DIP6 8U -#define DIP7 7U -#define DIP8 6U -#define DIP9 0U -#define DIP10 1U -#define DIP11 18U -#define DIP12 17U -#define DIP13 15U -#define DIP14 16U -#define DIP15 23U -#define DIP16 24U -#define DIP17 25U -#define DIP18 26U -#define DIP19 62U -#define DIP20 63U -#define DIP21 69U -#define DIP22 68U -#define DIP23 67U -#define DIP24 66U -#define DIP25 65U -#define DIP26 64U -#define DIP27 11U -#define DIP28 10U -#define DIP29 5U -#define DIP30 4U -#define LED1 50U -#define LED2 52U -#define LED3 53U -#define LED4 55U diff --git a/c/src/lib/libbsp/arm/lpc176x/include/pwmout-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/pwmout-defs.h deleted file mode 100755 index f55b154a05..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/pwmout-defs.h +++ /dev/null @@ -1,105 +0,0 @@ -/** - * @file pwmout-defs.h - * - * @ingroup lpc176x - * - * @brief PWM-Out controller for the mbed lpc1768 board. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LPC176X_PWMOUT_DEFS_H -#define LPC176X_PWMOUT_DEFS_H - -#include <bsp/lpc176x.h> -#include <bsp/pwmout.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define PWM_DEFAULT_PERIOD 20000u -#define PWM_DEFAULT_PULSEWIDTH 0u - -#define PWM_PRESCALER_USECOND ( LPC176X_CCLK / 1000000 ) -#define PWM_MCR_RESET_ON_MATCH0 ( 1 << 1 ) -#define PWM_PCR_ENABLE_PWM( pwmout ) ( 1 << ( 9 + pwmout ) ) -#define PWM_TCR_RESET ( 1 << 1 ) -#define PWM_TCR_ENABLE ( 1u ) -#define PWM_TCR_PWM ( 1 << 3 ) -#define PWM_LER_LATCH_MATCH_0 1u -#define PWM_LER_LATCH( match ) ( 1 << ( ( match ) + 1 ) ) - -/** - * @brief The low-level PWM output device. - */ -typedef struct { - volatile uint32_t IR; - volatile uint32_t TCR; - volatile uint32_t TC; - volatile uint32_t PR; - volatile uint32_t PC; - volatile uint32_t MCR; - volatile uint32_t MR0; - volatile uint32_t MR1; - volatile uint32_t MR2; - volatile uint32_t MR3; - volatile uint32_t CCR; - volatile uint32_t CR0; - volatile uint32_t CR1; - volatile uint32_t CR2; - volatile uint32_t CR3; - volatile uint32_t RESERVED0; - volatile uint32_t MR4; - volatile uint32_t MR5; - volatile uint32_t MR6; - volatile uint32_t PCR; - volatile uint32_t LER; - volatile uint32_t RESERVED1[ 7 ]; - volatile uint32_t CTCR; -} lpc176x_pwm_device; - -/** - * @brief Represents one pin and the respective function to be set - * for each PWM output. - */ -typedef struct { - uint32_t pin_number; - lpc176x_pin_function pin_function; -} lpc176x_pwm_pin; - -/** - * @brief The PWM outputs of the board. - */ -typedef enum { - PWMO_1, - PWMO_2, - PWMO_3, - PWMO_4, - PWMO_5, - PWMO_6, - PWM_OUTPUT_NUMBER -} lpc176x_pwm_number; - -/** - * @brief A pin for each PWM output. - */ -typedef enum { - PWM_FIRST_PIN, - PWM_SECOND_PIN, - PWM_NUMBER_OF_PINS -} lpc176x_pwm_pin_number; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/c/src/lib/libbsp/arm/lpc176x/include/pwmout.h b/c/src/lib/libbsp/arm/lpc176x/include/pwmout.h deleted file mode 100755 index 1427fc5f3e..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/pwmout.h +++ /dev/null @@ -1,73 +0,0 @@ -/** - * @file pwmout.h - * - * @ingroup lpc176x - * - * @brief PWM-Out controller for the mbed lpc1768 board. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LPC176X_PWMOUT_H -#define LPC176X_PWMOUT_H - -#include <bsp.h> -#include <bsp/io.h> -#include <bsp/lpc176x.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Initializes the PWM output device and sets an initial period - * of 20000us. - * - * @param pin_number The PWM output pin. - * @return RTEMS_SUCCESSFULL if the PWM initialization was OK, - * RTEMS_INVALID_NUMBER for a wrong parameter. - */ -rtems_status_code pwm_init( const lpc176x_pin_number pin_number ); - -/** - * @brief Sets a period for the PWM output. (Note that this changes the period - * for all the PWM outputs.) - * - * @param pin_number The pin whose period we want to change. - * @param period The desired period in microseconds. - * - * @return RTEMS_SUCCESSFULL if the period's setting was OK, - * RTEMS_INVALID_NUMBER for a bad parameter. - */ -rtems_status_code pwm_period( - const lpc176x_pin_number pin_number, - const lpc176x_microseconds period -); - -/** - * @brief Sets a pulsewidth for the PWM output. - * - * @param pin_number The pin whose pulsewidth we want to change. - * @param pwidth The desired pulsewidth in microseconds. - * - * @return RTEMS_SUCCESSFULL if the pulsewidth's setting was OK, - * RTEMS_INVALID_NUMBER for a wrong parameter. - */ -rtems_status_code pwm_pulsewidth( - const lpc176x_pin_number pin_number, - const lpc176x_microseconds pwidth -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif diff --git a/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h b/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h deleted file mode 100644 index 26087ff3e9..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/system-clocks.h +++ /dev/null @@ -1,91 +0,0 @@ -/** - * @file - * - * @ingroup lpc176x_clocks - * - * @brief System clocks. - */ - -/* - * Copyright (c) 2008, 2009 - * embedded brains GmbH - * Obere Lagerstr. 30 - * D-82178 Puchheim - * Germany - * <rtems@embedded-brains.de> - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H -#define LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H - -#include <bsp/lpc176x.h> -#include <bsp/timer-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @defgroup lpc176x_clock System Clocks - * - * @ingroup lpc176x - * - * @brief System clocks. - * - * @{ - */ - -/** - * @brief Initializes the standard timer. - * - * This function uses Timer 1. - */ -void lpc176x_timer_initialize( void ); - -/** - * @brief Returns current standard timer value in CPU clocks. - * - * @return This function uses Timer 1. - */ -static inline unsigned lpc176x_get_timer1( void ) -{ - return LPC176X_T1TC; -} - -/** - * @brief Delay for @a us micro seconds. - * - * This function uses the standard timer and assumes that the CPU - * frequency is in whole MHz numbers. The delay value @a us will be - * converted to CPU ticks and there is no protection against integer - * overflows. - * - * This function uses Timer 1. - */ -void lpc176x_micro_seconds_delay( unsigned us ); - -/** - * @brief Returns the PLL output clock frequency in [Hz]. - * - * @return Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc176x_pllclk( void ); - -/** - * @brief Returns the CPU clock frequency in [Hz]. - * - * @return Returns zero in case of an unexpected PLL input frequency. - */ -unsigned lpc176x_cclk( void ); - -/** @} */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_SYSTEM_CLOCKS_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/timer-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/timer-defs.h deleted file mode 100644 index 3827aa9279..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/timer-defs.h +++ /dev/null @@ -1,449 +0,0 @@ -/** - * @file timer-defs.h - * - * @ingroup lpc176x - * - * @brief API definitions of the for the timer of the lpc176x bsp. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H -#define LIBBSP_ARM_LPC176X_TIMER_DEFS_H - -#include <bsp/common-types.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Timer 0 */ -#define LPC176X_TMR0_BASE_ADDR 0x40004000U - -#define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x00U ) ) -#define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x04U ) ) -#define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x08U ) ) -#define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x0CU ) ) -#define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x10U ) ) -#define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x14U ) ) -#define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x18U ) ) -#define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x1CU ) ) -#define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x20U ) ) -#define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x24U ) ) -#define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x28U ) ) -#define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x2CU ) ) -#define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x30U ) ) -#define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x34U ) ) -#define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x38U ) ) -#define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x3CU ) ) -#define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \ - 0x70U ) ) - -/* Timer 1 */ -#define LPC176X_TMR1_BASE_ADDR 0x40008000U - -#define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x00U ) ) -#define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x04U ) ) -#define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x08U ) ) -#define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x0CU ) ) -#define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x10U ) ) -#define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x14U ) ) -#define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x18U ) ) -#define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x1CU ) ) -#define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x20U ) ) -#define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x24U ) ) -#define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x28U ) ) -#define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x2CU ) ) -#define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x30U ) ) -#define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x34U ) ) -#define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x38U ) ) -#define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x3CU ) ) -#define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \ - 0x70U ) ) - -/* Timer 2 */ -#define LPC176X_TMR2_BASE_ADDR 0x40090000U - -#define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x00U ) ) -#define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x04U ) ) -#define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x08U ) ) -#define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x0CU ) ) -#define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x10U ) ) -#define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x14U ) ) -#define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x18U ) ) -#define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x1CU ) ) -#define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x20U ) ) -#define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x24U ) ) -#define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x28U ) ) -#define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x2CU ) ) -#define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x30U ) ) -#define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x34U ) ) -#define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x38U ) ) -#define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x3CU ) ) -#define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \ - 0x70U ) ) - -/* Timer 3 */ -#define LPC176X_TMR3_BASE_ADDR 0x40094000U - -#define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x00U ) ) -#define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x04U ) ) -#define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x08U ) ) -#define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x0CU ) ) -#define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x10U ) ) -#define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x14U ) ) -#define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x18U ) ) -#define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x1CU ) ) -#define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x20U ) ) -#define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x24U ) ) -#define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x28U ) ) -#define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x2CU ) ) -#define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x30U ) ) -#define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x34U ) ) -#define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x38U ) ) -#define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x3CU ) ) -#define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \ - 0x70U ) ) - -/** - * @brief Represents the timer device registers. - */ -typedef struct { - /** - * @brief Interrupt Register. - */ - volatile uint32_t IR; - /** - * @brief Timer Control Register. - */ - volatile uint32_t TCR; - /** - * @brief Timer Counter. - */ - volatile uint32_t TC; - /** - * @brief Prescale Register. - */ - volatile uint32_t PR; - /** - * @brief Prescale Counter. - */ - volatile uint32_t PC; - /** - * @brief Match Control Register. - */ - volatile uint32_t MCR; - /** - * @brief Match Register (0, 1, 2, 3) - */ - volatile uint32_t MR[ 4 ]; - /** - * @brief Capture Control Register. - */ - volatile uint32_t CCR; - /** - * @brief Capture Register (0, 1) - */ - volatile uint32_t CR[ 2 ]; - volatile uint32_t reserved0; - volatile uint32_t reserved1; - /** - * @brief External Match Register. - */ - volatile uint32_t EMR; - volatile uint32_t reserved2[ 12 ]; - /** - * @brief Count Control Register. - */ - volatile uint32_t CTCR; -} lpc176x_timer_device; - -#define LPC176X_PIN_SELECT_TIMER 3U -#define LPC176X_PINSEL_NO_PORT 999U - -#define LPC176X_TIMER_RESET ( 1U << 1U ) -#define LPC176X_TIMER_START 1U -#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U -#define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U ) -#define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U } -#define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U } -#define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U } -#define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U } -#define LPC176X_TIMER0_EMATCH_PORTS { 60U, \ - 61U, \ - LPC176X_PINSEL_NO_PORT, \ - LPC176X_PINSEL_NO_PORT } -#define LPC176X_TIMER1_EMATCH_PORTS { 54U, \ - 57U, \ - LPC176X_PINSEL_NO_PORT, \ - LPC176X_PINSEL_NO_PORT } -#define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U } -#define LPC176X_TIMER3_EMATCH_PORTS { 10U, \ - 11U, \ - LPC176X_PINSEL_NO_PORT, \ - LPC176X_PINSEL_NO_PORT } -#define LPC176X_TIMER_DEFAULT_RESOLUTION 1U -#define LPC176X_TIMER_MCR_MASK 7U -#define LPC176X_TIMER_MCR_MASK_SIZE 3U -#define LPC176X_TIMER_CCR_MASK 7U -#define LPC176X_TIMER_CCR_MASK_SIZE 3U -#define LPC176X_TIMER_EMR_MASK 3U -#define LPC176X_TIMER_EMR_MASK_SIZE 2U -#define LPC176X_TIMER_EMR_MASK_OFFSET 4U -#define LPC176X_TIMER_CLEAR_FUNCTION 0U -#define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U -#define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U ) -#define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i ) -#define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U -#define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U - -#define LPC176X_ISR_NAME_STRING_SIZE 10U - -#define LPC176X_SET_MCR( mcr, match_port, function ) \ - SET_FIELD( mcr, \ - function, \ - ( 0x7U << ( 3U * match_port ) ), \ - ( 3U * match_port ) ) -#define LPC176X_SET_CCR( mcr, capture_port, function ) \ - SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \ - ( 3U * capture_port ) ) -#define LPC176X_SET_EMR( mcr, match_port, function ) \ - SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \ - ( 2U * match_port + 4U ) ) - -/** - * @brief Capture ports of a timer. - * - * Enumerated type to define the set of capture ports for a timer device. - */ -typedef enum { - LPC176X_CAPn_0, - LPC176X_CAPn_1, - LPC176X_CAPTURE_PORTS_COUNT -} lpc176x_capture_port; - -/** - * @brief Match ports of a timer. - * - * Enumerated type to define the set of match ports for a timer device. - */ -typedef enum { - LPC176X_MATn_0, - LPC176X_MATn_1, - LPC176X_MATn_2, - LPC176X_MATn_3, - LPC176X_EMATCH_PORTS_COUNT -} lpc176x_match_port; - -/** - * @brief Timer modes of a timer. - * - * Enumerated type to define the set of modes for a timer device. - */ -typedef enum { - LPC176X_TIMER_MODE_TIMER, - LPC176X_TIMER_MODE_COUNTER_RISING_CAP0, - LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0, - LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0, - LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ), - LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ), - LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ), -} lpc176x_timer_mode; - -/** - * @brief The timer devices in the board. - * - * Enumerated type to define the timer device's numbers. - */ -typedef enum { - LPC176X_TIMER_0, - LPC176X_TIMER_1, - LPC176X_TIMER_2, - LPC176X_TIMER_3, - LPC176X_TIMER_COUNT -} lpc176x_timer_number; - -/** - * @brief The index for the isr_funct_vector representing the functions - * that attends each possible interrupt source for a timer. - * - * Enumerated type to define the set of isr timer functions . - */ -typedef enum { - LPC176X_MAT0_ISR_FUNCTION, - LPC176X_MAT1_ISR_FUNCTION, - LPC176X_MAT2_ISR_FUNCTION, - LPC176X_MAT3_ISR_FUNCTION, - LPC176X_CAP0_ISR_FUNCTION, - LPC176X_CAP1_ISR_FUNCTION, - LPC176X_ISR_FUNCTIONS_COUNT -} lpc176x_isr_function; - -/** - * @brief The possible functions at match. This options could be - * used together. - * - * Enumerated type to define the set of functions at mach for a - * timer device. - */ -typedef enum { - LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U, - LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U, - LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ), - LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U ) -} lpc176x_match_function; - -/** - * @brief The possible functions at capture. This options could - * be used together. - * - * Enumerated type to define the set of functions at capture for - * a timer device. - */ -typedef enum { - LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U, - LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U, - LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ), - LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U ) -} lpc176x_capture_function; - -/** - * @brief The possible functions at match, for the external ports. - * - * Enumerated type to define the set of functions at match, for external - * ports, for a timer device. - */ -typedef enum { - LPC176X_TIMER_EXTMATCH_FUNCTION_NONE, - LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR, - LPC176X_TIMER_EXTMATCH_FUNCTION_SET, - LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE -} lpc176x_ext_match_function; - -/** - * @brief A function that attends an interruption for a timer. - * - * @param tnumber Timer number. - * @return Pointer to the match function. - */ -typedef void (*lpc176x_isr_funct) ( const lpc176x_timer_number tnumber ); - -/** - * @brief The vector of functions that attends each possible interrupt - * source for a timer. - */ -typedef lpc176x_isr_funct const lpc176x_isr_funct_vector[ - LPC176X_ISR_FUNCTIONS_COUNT ]; - -/** - * @brief The Timer device representation. - */ -typedef struct { - /** - * @brief The address of the controlling registers for the timer. - */ - lpc176x_timer_device *const device; - /** - * @brief The module for the RTEMS module starting (power and clock). - */ - const lpc176x_module module; - /** - * @brief The Pins for the Capture ports of this timer. - */ - const lpc176x_pin_number pinselcap[ LPC176X_CAPTURE_PORTS_COUNT ]; - /** - * @brief The Pins for the external match ports of this timer. - */ - const lpc176x_pin_number pinselemat[ LPC176X_EMATCH_PORTS_COUNT ]; -} lpc176x_timer; - -/** - * @brief The Timer functions. - */ -typedef struct { - /** - * @brief The vector of isr functions for this timer. - */ - const lpc176x_isr_funct_vector *funct_vector; -} lpc176x_timer_functions; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_TIMER_DEFS_H */
\ No newline at end of file diff --git a/c/src/lib/libbsp/arm/lpc176x/include/timer.h b/c/src/lib/libbsp/arm/lpc176x/include/timer.h deleted file mode 100644 index 6805b55f0e..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/timer.h +++ /dev/null @@ -1,195 +0,0 @@ -/** - * @file timer.h - * - * @ingroup lpc176x - * - * @brief Timer API for the lpc176x bsp. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_TIMER_H -#define LIBBSP_ARM_LPC176X_TIMER_H - -#include <bsp/timer-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief resets timer counter and stops it. - * - * @param tnumber the device to be reseted - * @return RTEMS_SUCCESSFUL if the timer was reseted successfuly. - */ -rtems_status_code lpc176x_timer_reset( lpc176x_timer_number tnumber ); - -/** - * @brief Sets mode of the timer (timer, counter rising, counter falling - * or counter both edges) - * - * @param tnumber: the device to be setted - * @param mode: the desired mode - * @return RTEMS_SUCCESSFUL if the timer's mode was setted successfuly. - */ -rtems_status_code lpc176x_timer_set_mode( - lpc176x_timer_number tnumber, - lpc176x_timer_mode mode -); - -/** - * @brief Starts the timer counter - * - * @param tnumber: the device to be started - * @return RTEMS_SUCCESSFUL if the timer's was started successfuly. - */ -rtems_status_code lpc176x_timer_start( lpc176x_timer_number tnumber ); - -/** - * @brief true if timer is started. - * - * @param tnumber: the timer number to check. - * @param is_started: TRUE if the timer is running. - * @return RTEMS_SUCCESSFUL if the started timer check was successfuly. - */ -rtems_status_code lpc176x_timer_is_started( - lpc176x_timer_number tnumber, - bool *is_started -); - -/** - * @brief sets the resolution in microseconds of the timer - * - * @param tnumber: the device to be modified. - * @param resolution: how many microseconds will mean each timer - * counter unit. - * @return RTEMS_SUCCESSFUL if the timer resolution was setted successfuly. - */ -rtems_status_code lpc176x_timer_set_resolution( - lpc176x_timer_number tnumber, - lpc176x_microseconds resolution -); - -/** - * @brief Configures the timer match - * - * @param tnumber: the device to be modified - * @param match_port: which port of this timer will be setted - * @param function: what the timer should do when match: stop timer, clear, - * and/or interrupt - * @param match_value: the value that the timer should match. - * @return RTEMS_SUCCESSFUL if the timer was configured successfuly. - */ -rtems_status_code lpc176x_timer_match_config( - lpc176x_timer_number tnumber, - lpc176x_match_port match_port, - lpc176x_match_function function, - uint32_t match_value -); - -/** - * @brief Configures the capture ports - * - * @param tnumber: the device to be modified - * @param capture_port: which port of this timer will be setted - * @param function: At which edge/s will the capture work, and - * if it will interrupt - */ -rtems_status_code lpc176x_timer_capture_config( - lpc176x_timer_number tnumber, - lpc176x_capture_port capture_port, - lpc176x_capture_function function -); - -/** - * @brief Configures the external match ports - * - * @param tnumber: the device to be modified - * @param match_port: which match for this timer - * @param function: what should do when match: set, clear toggle or nothing - */ -rtems_status_code lpc176x_timer_external_match_config( - lpc176x_timer_number tnumber, - lpc176x_match_port match_port, - lpc176x_ext_match_function function -); - -/** - * @brief Gets the captured value - * - * @param tnumber: the device to be modified - * @param capnumber: which capture port for this timer - * @return the captured value - */ -uint32_t lpc176x_timer_get_capvalue( - lpc176x_timer_number tnumber, - lpc176x_capture_port capnumber -); - -/** - * @brief Gets the timer value - * - * @param tnumber: the device - * @return the timer value - */ -uint32_t lpc176x_timer_get_timer_value( lpc176x_timer_number tnumber ); - -/** - * @brief Sets the timer value - * - * @param tnumber: the timer to modify. - * @param timer_value the value to set. - */ -rtems_status_code lpc176x_timer_set_timer_value( - lpc176x_timer_number tnumber, - uint32_t lpc176x_timer_value -); - -/** - * @brief Timer generic isroutine. - * - * @param timernumber the number of timer. - */ -void lpc176x_timer_isr( void *lpc176x_timer_number ); - -/** - * @brief Initializes timer in timer mode and resets counter but - * without starting it, and without any capture or - * match function. - * - * @param tnumber which timer - * @return RTEMS_SUCCESSFUL when everything ok. - */ -rtems_status_code lpc176x_timer_init( lpc176x_timer_number tnumber ); - -/** - * @brief Initializes timer in timer mode and resets counter but - * without starting it, and without any capture or - * match function. - * - * @param tnumber which timer to init - * @param vector the functions to be used by the isr. - * @return RTEMS_SUCCESSFUL when everything ok. - */ -rtems_status_code lpc176x_timer_init_with_interrupt( - lpc176x_timer_number tnumber, - const lpc176x_isr_funct_vector *vector -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_TIMER_H */
\ No newline at end of file diff --git a/c/src/lib/libbsp/arm/lpc176x/include/tm27.h b/c/src/lib/libbsp/arm/lpc176x/include/tm27.h deleted file mode 100644 index 0dfa7bf628..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/tm27.h +++ /dev/null @@ -1 +0,0 @@ -#include <rtems/tm27-default.h> diff --git a/c/src/lib/libbsp/arm/lpc176x/include/watchdog-defs.h b/c/src/lib/libbsp/arm/lpc176x/include/watchdog-defs.h deleted file mode 100644 index 44ea80527e..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/watchdog-defs.h +++ /dev/null @@ -1,65 +0,0 @@ -/** - * @file watchdog-defs.h - * - * @ingroup lpc176x - * - * @brief API definitions of the Watchdog driver for the lpc176x bsp in RTEMS. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H -#define LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H - -#include <rtems/score/cpu.h> -#include <bsp.h> -#include <bspopts.h> -#include <bsp/utility.h> -#include <bsp/irq.h> -#include <bsp/common-types.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -#define LPC176X_WDMOD_BASE 0x40000000U -#define LPC176X_WDFEED_CON 0XAAU -#define LPC176X_WDFEED_CFG 0X55U -#define LPC176X_WD_PRESCALER_DIVISOR 4000000U -#define LPC176X_WWDT_MOD_WDEN BSP_BIT32( 0 ) -#define LPC176X_WWDT_MOD_WDRESET BSP_BIT32( 1 ) -#define LPC176X_WWDT_MOD_WDTOF BSP_BIT32( 2 ) -#define LPC176X_WWDT_MOD_WDINT BSP_BIT32( 3 ) -#define LPC176X_WWDT_CLKSEL_WDSEL_IRC 0x0U -#define LPC176X_WWDT_CLKSEL_WDSEL_PCLK 0x1U -#define LPC176X_WWDT_CLKSEL_WDSEL_RTC 0x2U -#define LPC176X_WD_INTERRUPT_VECTOR_NUMBER 0U -#define LPC176X_WDMOD ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x00U ) ) -#define LPC176X_WDTC ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x04U ) ) -#define LPC176X_WDFEED ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ - 0x08U ) ) -#define LPC176X_WDTV ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + 0x0CU ) ) -#define LPC176X_WDCLKSEL ( *(volatile uint32_t *) ( LPC176X_WDMOD_BASE + \ - 0x10U ) ) - -/** - * @brief A function that attends an interruption for a watchdog. - */ -typedef rtems_interrupt_handler lpc176x_wd_isr_funct; - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_DEFS_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h b/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h deleted file mode 100644 index 8b5f033605..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/include/watchdog.h +++ /dev/null @@ -1,70 +0,0 @@ -/** - * @file watchdog.h - * - * @ingroup lpc176x - * - * @brief API of the Watchdog driver for the lpc176x bsp in RTEMS. - */ - -/* - * Copyright (c) 2014 Taller Technologies. - * - * @author Boretto Martin (martin.boretto@tallertechnologies.com) - * @author Diaz Marcos (marcos.diaz@tallertechnologies.com) - * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com) - * @author Daniel Chicco (daniel.chicco@tallertechnologies.com) - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.org/license/LICENSE. - */ - -#ifndef LIBBSP_ARM_LPC176X_WATCHDOG_H -#define LIBBSP_ARM_LPC176X_WATCHDOG_H - -#include <bsp/watchdog-defs.h> - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/** - * @brief Checks if the watchdog was executed by software or not. Set when - * the watchdog timer times out, cleared by software. - * - * @return TRUE if the watchdog was executed. - * FALSE otherwise. - */ -bool lpc176x_been_reset_by_watchdog( void ); - -/** - * @brief Resets the watchdog timer. - */ -void lpc176x_watchdog_reset( void ); - -/** - * @brief Configures the watchdog's timer. - * - * @param tcount Timer's out value. - * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully. - */ -rtems_status_code lpc176x_watchdog_config( lpc176x_microseconds tcount ); - -/** - * @brief Configures the timer watchdog using interrupt. - * - * @param tcount Timer's out value. - * @param interrupt Interrupt to register. - * @return RTEMS_SUCCESSFUL if the watchdog was configured successfully - * with interrupts. - */ -rtems_status_code lpc176x_watchdog_config_with_interrupt( - lpc176x_wd_isr_funct interrupt, - lpc176x_microseconds tcount -); - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* LIBBSP_ARM_LPC176X_WATCHDOG_H */ diff --git a/c/src/lib/libbsp/arm/lpc176x/preinstall.am b/c/src/lib/libbsp/arm/lpc176x/preinstall.am deleted file mode 100644 index 1ecae367c7..0000000000 --- a/c/src/lib/libbsp/arm/lpc176x/preinstall.am +++ /dev/null @@ -1,187 +0,0 @@ -## Automatically generated by ampolish3 - Do not edit - -if AMPOLISH3 -$(srcdir)/preinstall.am: Makefile.am - $(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am -endif - -PREINSTALL_DIRS = -DISTCLEANFILES += $(PREINSTALL_DIRS) - -all-am: $(PREINSTALL_FILES) - -PREINSTALL_FILES = -CLEANFILES = $(PREINSTALL_FILES) - -all-local: $(TMPINSTALL_FILES) - -TMPINSTALL_FILES = -CLEANFILES += $(TMPINSTALL_FILES) - -$(PROJECT_LIB)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_LIB) - @: > $(PROJECT_LIB)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_LIB)/$(dirstamp) - -$(PROJECT_INCLUDE)/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE) - @: > $(PROJECT_INCLUDE)/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/$(dirstamp) - -$(PROJECT_INCLUDE)/bsp/$(dirstamp): - @$(MKDIR_P) $(PROJECT_INCLUDE)/bsp - @: > $(PROJECT_INCLUDE)/bsp/$(dirstamp) -PREINSTALL_DIRS += $(PROJECT_INCLUDE)/bsp/$(dirstamp) - -$(PROJECT_LIB)/bsp_specs: bsp_specs $(PROJECT_LIB)/$(dirstamp) - $(INSTALL_DATA) $< $(PROJECT_LIB)/bsp_specs -PREINSTALL_FILES += $(PROJECT_LIB)/bsp_specs - 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diff --git a/c/src/lib/libbsp/arm/lpc176x/bsp_specs b/c/src/lib/libbsp/arm/lpc176x/startup/bsp_specs index 47dd31d46b..47dd31d46b 100644 --- a/c/src/lib/libbsp/arm/lpc176x/bsp_specs +++ b/c/src/lib/libbsp/arm/lpc176x/startup/bsp_specs |