2011-09-24 Sebastian Huber <sebastian.huber@embedded-brains.de>

	* 0001-Fixed-interrupt-handling-for-ARMv7M.patch,
	0002-Fixed-system-handler-priority-register-access.patch,
	0003-Disable-priority_mask-unused-for-NVIC.patch, 0004-Typo.patch,
	0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch,
	0006-Evil-hack-to-increase-the-RAM-size.patch, bsp_specs, ChangeLog,
	clock/clock-config.c, configure.ac, console/console-config.c,
	console/uart.c, .cvsignore, include/bsp.h, include/.cvsignore,
	include/irq.h, include/lm3s69xx.h, include/uart.h, irq/irq.c,
	make/custom/lm3s6965.cfg, make/custom/lm3s69xx.inc, Makefile.am,
	README, start/start.S, startup/bspreset.c, startup/bspstart.c,
	startup/bspstarthook.c, startup/linkcmds.lm3s6965, timer/timer.c: New
	files.

1 files changed, 102 insertions, 0 deletions

diff --git a/c/src/lib/libbsp/arm/lm3s69xx/0002-Fixed-system-handler-priority-register-access.patch b/c/src/lib/libbsp/arm/lm3s69xx/0002-Fixed-system-handler-priority-register-access.patch
new file mode 100644
index 0000000000..4502000603
--- /dev/null
+++ b/c/src/lib/libbsp/arm/lm3s69xx/0002-Fixed-system-handler-priority-register-access.patch
@@ -0,0 +1,102 @@
+From 403b4e0718a815b425a964cfbf7f4117a9278d88 Mon Sep 17 00:00:00 2001
+From: Sebastian Huber <sebastian.huber@embedded-brains.de>
+Date: Sun, 19 Jun 2011 15:33:17 +0200
+Subject: [PATCH 2/6] Fixed system handler priority register access.
+
+According to "ARMv7-M Architecture Reference Manual" issue D section
+"B3.2.10 System Handler Prioriy Register 1, SHPR1", "B3.2.11 System
+Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
+Register 3, SHPR3".
+---
+ hw/arm_gic.c     |   16 ++++++++++++++--
+ hw/armv7m_nvic.c |   19 -------------------
+ 2 files changed, 14 insertions(+), 21 deletions(-)
+
+diff --git a/hw/arm_gic.c b/hw/arm_gic.c
+index 0e934ec..9f75fcc 100644
+--- a/hw/arm_gic.c
++++ b/hw/arm_gic.c
+@@ -341,6 +341,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+             if (GIC_TEST_TRIGGER(irq + i))
+                 res |= (2 << (i * 2));
+         }
++#else
++    } else if (0xd18 <= offset && offset < 0xd24) {
++        /* System Handler Priority.  */
++        irq = offset - 0xd14;
++        res = GIC_GET_PRIORITY(irq, cpu);
+ #endif
+     } else if (offset < 0xfe0) {
+         goto bad_reg;
+@@ -372,7 +377,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+     gic_state *s = (gic_state *)opaque;
+     uint32_t addr;
+     addr = offset;
+-    if (addr < 0x100 || addr > 0xd00)
++    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
++        && addr != 0xd20)) {
+         return nvic_readl(s, addr);
+ #endif
+     val = gic_dist_readw(opaque, offset);
+@@ -507,6 +513,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+                 GIC_CLEAR_TRIGGER(irq + i);
+             }
+         }
++#else
++    } else if (0xd18 <= offset && offset < 0xd24) {
++        /* System Handler Priority.  */
++        irq = offset - 0xd14;
++        s->priority1[irq][0] = value & 0xff;
+ #endif
+     } else {
+         /* 0xf00 is only handled for 32-bit writes.  */
+@@ -532,7 +543,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+ #ifdef NVIC
+     uint32_t addr;
+     addr = offset;
+-    if (addr < 0x100 || (addr > 0xd00 && addr != 0xf00)) {
++    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
++        && addr != 0xd20 && addr != 0xf00)) {
+         nvic_writel(s, addr, value);
+         return;
+     }
+diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
+index d06eec9..a2d1404 100644
+--- a/hw/armv7m_nvic.c
++++ b/hw/armv7m_nvic.c
+@@ -194,14 +194,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
+     case 0xd14: /* Configuration Control.  */
+         /* TODO: Implement Configuration Control bits.  */
+         return 0;
+-    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
+-        irq = offset - 0xd14;
+-        val = 0;
+-        val |= s->gic.priority1[irq++][0];
+-        val |= s->gic.priority1[irq++][0] << 8;
+-        val |= s->gic.priority1[irq++][0] << 16;
+-        val |= s->gic.priority1[irq][0] << 24;
+-        return val;
+     case 0xd24: /* System Handler Status.  */
+         val = 0;
+         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
+@@ -334,17 +326,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
+     case 0xd14: /* Configuration Control.  */
+         /* TODO: Implement control registers.  */
+         goto bad_reg;
+-    case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority.  */
+-        {
+-            int irq;
+-            irq = offset - 0xd14;
+-            s->gic.priority1[irq++][0] = value & 0xff;
+-            s->gic.priority1[irq++][0] = (value >> 8) & 0xff;
+-            s->gic.priority1[irq++][0] = (value >> 16) & 0xff;
+-            s->gic.priority1[irq][0] = (value >> 24) & 0xff;
+-            gic_update(&s->gic);
+-        }
+-        break;
+     case 0xd24: /* System Handler Control.  */
+         /* TODO: Real hardware allows you to set/clear the active bits
+            under some circumstances.  We don't implement this.  */
+-- 
+1.7.1
+