bsp/csb336: Move libcpu files to BSP

Update #3254.

8 files changed, 874 insertions, 5 deletions

diff --git a/c/src/lib/libbsp/arm/csb336/Makefile.am b/c/src/lib/libbsp/arm/csb336/Makefile.am
index b91d8f7049..2faa7175ef 100644
--- a/c/src/lib/libbsp/arm/csb336/Makefile.am
+++ b/c/src/lib/libbsp/arm/csb336/Makefile.am
@@ -8,6 +8,7 @@ dist_project_lib_DATA = bsp_specs
 
 include_HEADERS = include/bsp.h
 include_HEADERS += include/tm27.h
+include_HEADERS += include/mc9328mxl.h
 
 include_bsp_HEADERS =
 libbsp_a_CPPFLAGS =
@@ -36,17 +37,21 @@ libbsp_a_SOURCES += \
     ../../shared/sbrk.c ../../shared/gnatinstallhandler.c
 libbsp_a_SOURCES += ../../shared/cpucounterread.c
 libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
+libbsp_a_SOURCES += clock/clockdrv.c
+libbsp_a_SOURCES += timer/timer.c
 # console
 libbsp_a_SOURCES += console/uart.c
 # IRQ
 include_bsp_HEADERS += ../../shared/include/irq-generic.h \
 	../../shared/include/irq-info.h
+include_bsp_HEADERS += include/bsp/irq.h
 libbsp_a_SOURCES += ../../shared/src/irq-default-handler.c
 libbsp_a_SOURCES += ../../shared/src/irq-generic.c
 libbsp_a_SOURCES += ../../shared/src/irq-info.c
 libbsp_a_SOURCES += ../../shared/src/irq-legacy.c
 libbsp_a_SOURCES += ../../shared/src/irq-server.c
 libbsp_a_SOURCES += ../../shared/src/irq-shell.c
+libbsp_a_SOURCES += irq/irq.c
 
 # Cache
 libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
@@ -62,10 +67,7 @@ network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
 endif
 
-libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/clock.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/timer.rel \
-    ../../../libcpu/@RTEMS_CPU@/@RTEMS_CPU_MODEL@/irq.rel
+libbsp_a_LIBADD = ../../../libcpu/@RTEMS_CPU@/shared/arm920.rel
 
 if HAS_NETWORKING
 libbsp_a_LIBADD += network.rel
diff --git a/c/src/lib/libbsp/arm/csb336/clock/clockdrv.c b/c/src/lib/libbsp/arm/csb336/clock/clockdrv.c
new file mode 100644
index 0000000000..576a8278d5
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/clock/clockdrv.c
@@ -0,0 +1,134 @@
+/*
+ *  MC9328MXL clock specific using the System Timer
+ */
+
+/*
+ *  Copyright (c) 2004 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <mc9328mxl.h>
+#include <rtems/bspIo.h>  /* for printk */
+
+/* this is defined in ../../../shared/clockdrv_shell.h */
+void Clock_isr(rtems_irq_hdl_param arg);
+static void clock_isr_on(const rtems_irq_connect_data *unused);
+static void clock_isr_off(const rtems_irq_connect_data *unused);
+static int clock_isr_is_on(const rtems_irq_connect_data *irq);
+
+/* Replace the first value with the clock's interrupt name. */
+rtems_irq_connect_data clock_isr_data = {
+  .name   = BSP_INT_TIMER1,
+  .hdl    = Clock_isr,
+  .handle = (void *)BSP_INT_TIMER1,
+  .on     = clock_isr_on,
+  .off    = clock_isr_off,
+  .isOn   = clock_isr_is_on,
+};
+
+/**
+ * When we get the clock interrupt
+ *    - clear the interrupt bit?
+ *    - restart the timer?
+ */
+#define Clock_driver_support_at_tick()               \
+  do {                                               \
+    uint32_t reg;                                    \
+                                                     \
+    reg = MC9328MXL_TMR1_TSTAT;                      \
+    (void) reg; /* avoid set but not used warning */ \
+    MC9328MXL_TMR1_TSTAT = 0;                        \
+  } while(0)
+
+/**
+ * Installs the clock ISR. You shouldn't need to change this.
+ */
+#define Clock_driver_support_install_isr( _new ) \
+  BSP_install_rtems_irq_handler(&clock_isr_data)
+
+/**
+ * Initialize the hardware for the clock
+ *   - Set the frequency
+ *   - enable it
+ *   - clear any pending interrupts
+ *
+ * Since you may want the clock always running, you can
+ * enable interrupts here. If you do so, the clock_isr_on(),
+ * clock_isr_off(), and clock_isr_is_on() functions can be
+ * NOPs.
+ */
+#define Clock_driver_support_initialize_hardware() \
+  do { \
+        int freq; \
+        int cnt; \
+        freq = get_perclk1_freq(); \
+        printk("perclk1 freq is %d\n", freq); \
+        cnt = ((long long)freq * rtems_configuration_get_microseconds_per_tick() + 500000) / 1000000;\
+        printk("cnt freq is %d\n", cnt); \
+        MC9328MXL_TMR1_TCMP = cnt; \
+        /* use PERCLK1 as input, enable timer */ \
+        MC9328MXL_TMR1_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 | \
+                               MC9328MXL_TMR_TCTL_TEN | \
+                               MC9328MXL_TMR_TCTL_IRQEN); \
+        /* set prescaler to 1 (register value + 1) */ \
+        MC9328MXL_TMR1_TPRER = 0; \
+     } while (0)
+
+/**
+ * Do whatever you need to shut the clock down and remove the
+ * interrupt handler. Since this normally only gets called on
+ * RTEMS shutdown, you may not need to do anything other than
+ * remove the ISR.
+ */
+#define Clock_driver_support_shutdown_hardware()                        \
+  do {                                                                  \
+    /* Disable timer */ \
+    MC9328MXL_TMR1_TCTL = 0; \
+    BSP_remove_rtems_irq_handler(&clock_isr_data);                  \
+  } while (0)
+
+/**
+ * Enables clock interrupt.
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_on(const rtems_irq_connect_data *unused)
+{
+  MC9328MXL_TMR1_TCTL |= MC9328MXL_TMR_TCTL_IRQEN;
+  MC9328MXL_AITC_INTENNUM = MC9328MXL_INT_TIMER1;
+}
+
+/**
+ * Disables clock interrupts
+ *
+ * If the interrupt is always on, this can be a NOP.
+ */
+static void clock_isr_off(const rtems_irq_connect_data *unused)
+{
+  MC9328MXL_TMR1_TCTL &= ~MC9328MXL_TMR_TCTL_IRQEN;
+  MC9328MXL_AITC_INTDISNUM = MC9328MXL_INT_TIMER1;
+}
+
+/**
+ * Tests to see if clock interrupt is enabled, and returns 1 if so.
+ * If interrupt is not enabled, returns 0.
+ *
+ * If the interrupt is always on, this always returns 1.
+ */
+static int clock_isr_is_on(const rtems_irq_connect_data *irq)
+{
+  return MC9328MXL_TMR1_TCTL & MC9328MXL_TMR_TCTL_IRQEN;
+}
+
+#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER
+
+/* Make sure to include this, and only at the end of the file */
+
+#include "../../../../libbsp/shared/clockdrv_shell.h"
diff --git a/c/src/lib/libbsp/arm/csb336/include/bsp/irq.h b/c/src/lib/libbsp/arm/csb336/include/bsp/irq.h
new file mode 100644
index 0000000000..eb56fdd887
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/include/bsp/irq.h
@@ -0,0 +1,95 @@
+/*
+ * Interrupt handler Header file
+ *
+ * Copyright (c) 2010 embedded brains GmbH.
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __IRQ_H__
+#define __IRQ_H__
+
+#ifndef __asm__
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#endif /* __asm__ */
+
+/* possible interrupt sources on the MC9328MXL */
+#define BSP_INT_UART3_PFERR       0
+#define BSP_INT_UART3_RTS         1
+#define BSP_INT_UART3_DTR         2
+#define BSP_INT_UART3_UARTC       3
+#define BSP_INT_UART3_TX          4
+#define BSP_INT_PEN_UP            5
+#define BSP_INT_CSI               6
+#define BSP_INT_MMA_MAC           7
+#define BSP_INT_MMA               8
+#define BSP_INT_COMP              9
+#define BSP_INT_MSIRQ            10
+#define BSP_INT_GPIO_PORTA       11
+#define BSP_INT_GPIO_PORTB       12
+#define BSP_INT_GPIO_PORTC       13
+#define BSP_INT_LCDC             14
+#define BSP_INT_SIM_IRQ          15
+#define BSP_INT_SIM_DATA         16
+#define BSP_INT_RTC              17
+#define BSP_INT_RTC_SAM          18
+#define BSP_INT_UART2_PFERR      19
+#define BSP_INT_UART2_RTS        20
+#define BSP_INT_UART2_DTR        21
+#define BSP_INT_UART2_UARTC      22
+#define BSP_INT_UART2_TX         23
+#define BSP_INT_UART2_RX         24
+#define BSP_INT_UART1_PFERR      25
+#define BSP_INT_UART1_RTS        26
+#define BSP_INT_UART1_DTR        27
+#define BSP_INT_UART1_UARTC      28
+#define BSP_INT_UART1_TX         29
+#define BSP_INT_UART1_RX         30
+#define BSP_INT_RES31            31
+#define BSP_INT_RES32            32
+#define BSP_INT_PEN_DATA         33
+#define BSP_INT_PWM              34
+#define BSP_INT_MMC_IRQ          35
+#define BSP_INT_SSI2_TX          36
+#define BSP_INT_SSI2_RX          37
+#define BSP_INT_SSI2_ERR         38
+#define BSP_INT_I2C              39
+#define BSP_INT_SPI2             40
+#define BSP_INT_SPI1             41
+#define BSP_INT_SSI_TX           42
+#define BSP_INT_SSI_TX_ERR       43
+#define BSP_INT_SSI_RX           44
+#define BSP_INT_SSI_RX_ERR       45
+#define BSP_INT_TOUCH            46
+#define BSP_INT_USBD0            47
+#define BSP_INT_USBD1            48
+#define BSP_INT_USBD2            49
+#define BSP_INT_USBD3            50
+#define BSP_INT_USBD4            51
+#define BSP_INT_USBD5            52
+#define BSP_INT_USBD6            53
+#define BSP_INT_UART3_RX         54
+#define BSP_INT_BTSYS            55
+#define BSP_INT_BTTIM            56
+#define BSP_INT_BTWUI            57
+#define BSP_INT_TIMER2           58
+#define BSP_INT_TIMER1           59
+#define BSP_INT_DMA_ERR          60
+#define BSP_INT_DMA              61
+#define BSP_INT_GPIO_PORTD       62
+#define BSP_INT_WDT              63
+#define BSP_MAX_INT              64
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define BSP_INTERRUPT_VECTOR_MAX (BSP_MAX_INT - 1)
+
+#endif /* __IRQ_H__ */
diff --git a/c/src/lib/libbsp/arm/csb336/include/mc9328mxl.h b/c/src/lib/libbsp/arm/csb336/include/mc9328mxl.h
new file mode 100644
index 0000000000..dd0516283a
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/include/mc9328mxl.h
@@ -0,0 +1,486 @@
+/*
+ * Motorola MC9328MXL Register definitions
+ *
+ * Copyright (c) 2003 by Cogent Computer Systems
+ * Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+#ifndef __MC9328MXL_H__
+#define __MC9328MXL_H__
+
+#include <stdint.h>
+
+#define bit(_x_) (1 << (_x_))
+
+/* Define some constants relating to the CPU */
+#define MC9328MXL_NUM_INTS  64        /* CPU supports 64 interrupts */
+
+/* Define the base addresses of the internal registers */
+#define MC9328MXL_AIPI1_BASE    0x00200000
+#define MC9328MXL_AIPI2_BASE    0x00210000
+#define MC9328MXL_WDOG_BASE     0x00201000
+#define MC9328MXL_TMR1_BASE     0x00202000
+#define MC9328MXL_TMR2_BASE     0x00203000
+#define MC9328MXL_RTC_BASE      0x00204000
+#define MC9328MXL_LCDC_BASE     0x00205000
+#define MC9328MXL_UART1_BASE    0x00206000
+#define MC9328MXL_UART2_BASE    0x00207000
+#define MC9328MXL_PWM_BASE      0x00208000
+#define MC9328MXL_DMAC_BASE     0x00209000
+#define MC9328MXL_USBD_BASE     0x00212000
+#define MC9328MXL_SPI1_BASE     0x00213000
+#define MC9328MXL_SPI2_BASE     0x00219000
+#define MC9328MXL_MMC_BASE      0x00214000
+#define MC9328MXL_I2C_BASE      0x00217000
+#define MC9328MXL_SSI_BASE      0x00218000
+#define MC9328MXL_MSHC_BASE     0x0021a000
+#define MC9328MXL_PLL_BASE      0x0021b000
+#define MC9328MXL_RESET_BASE    0x0021b800
+#define MC9328MXL_SYSCTRL_BASE  0x0021b804
+#define MC9328MXL_GPIOA_BASE    0x0021c000
+#define MC9328MXL_GPIOB_BASE    0x0021c100
+#define MC9328MXL_GPIOC_BASE    0x0021c200
+#define MC9328MXL_GPIOD_BASE    0x0021c300
+#define MC9328MXL_EIM_BASE      0x00220000
+#define MC9328MXL_SDRAM_BASE    0x00221000
+#define MC9328MXL_MMA_BASE      0x00222000
+#define MC9328MXL_AITC_BASE     0x00223000
+#define MC9328MXL_CSI_BASE      0x00224000
+
+
+#define MC9328MXL_TMR1_TCTL   (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x00)))
+#define MC9328MXL_TMR1_TPRER  (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x04)))
+#define MC9328MXL_TMR1_TCMP   (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x08)))
+#define MC9328MXL_TMR1_TCR    (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x0c)))
+#define MC9328MXL_TMR1_TCN    (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x10)))
+#define MC9328MXL_TMR1_TSTAT  (*((volatile uint32_t *)((MC9328MXL_TMR1_BASE) + 0x14)))
+
+#define MC9328MXL_TMR2_TCTL   (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x00)))
+#define MC9328MXL_TMR2_TPRER  (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x04)))
+#define MC9328MXL_TMR2_TCMP   (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x08)))
+#define MC9328MXL_TMR2_TCR    (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x0c)))
+#define MC9328MXL_TMR2_TCN    (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x10)))
+#define MC9328MXL_TMR2_TSTAT  (*((volatile uint32_t *)((MC9328MXL_TMR2_BASE) + 0x14)))
+
+#define MC9328MXL_TMR_TCTL_SWR                (bit(15))
+#define MC9328MXL_TMR_TCTL_FRR                (bit(8))
+#define MC9328MXL_TMR_TCTL_CAP_DIS            (0 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_RISE           (1 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_FALL           (2 << 6)
+#define MC9328MXL_TMR_TCTL_CAP_ANY            (3 << 6)
+#define MC9328MXL_TMR_TCTL_OM                 (bit(5))
+#define MC9328MXL_TMR_TCTL_IRQEN              (bit(4))
+#define MC9328MXL_TMR_TCTL_CLKSRC_STOP        (0 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK1       (1 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_PCLK_DIV16  (2 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_TIN         (3 << 1)
+#define MC9328MXL_TMR_TCTL_CLKSRC_32KHX       (4 << 1)
+#define MC9328MXL_TMR_TCTL_TEN                (bit(0))
+
+#define MC9328MXL_UART1_RXD   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x00)))
+#define MC9328MXL_UART1_TXD   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x40)))
+#define MC9328MXL_UART1_CR1   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x80)))
+#define MC9328MXL_UART1_CR2   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x84)))
+#define MC9328MXL_UART1_CR3   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x88)))
+#define MC9328MXL_UART1_CR4   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x8c)))
+#define MC9328MXL_UART1_FCR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x90)))
+#define MC9328MXL_UART1_SR1   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x94)))
+#define MC9328MXL_UART1_SR2   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x98)))
+#define MC9328MXL_UART1_ESC   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0x9c)))
+#define MC9328MXL_UART1_TIM   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa0)))
+#define MC9328MXL_UART1_BIR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa4)))
+#define MC9328MXL_UART1_BMR   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xa8)))
+#define MC9328MXL_UART1_BRC   (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xac)))
+#define MC9328MXL_UART1_IPR1  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb0)))
+#define MC9328MXL_UART1_IPR2  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb4)))
+#define MC9328MXL_UART1_IPR3  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xb8)))
+#define MC9328MXL_UART1_IPR4  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xbc)))
+#define MC9328MXL_UART1_MPR1  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc0)))
+#define MC9328MXL_UART1_MPR2  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc4)))
+#define MC9328MXL_UART1_MPR3  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xc8)))
+#define MC9328MXL_UART1_MPR4  (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xcc)))
+#define MC9328MXL_UART1_TS    (*((volatile uint32_t *)((MC9328MXL_UART1_BASE) + 0xd0)))
+
+#define MC9328MXL_UART2_RXD   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x00)))
+#define MC9328MXL_UART2_TXD   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x40)))
+#define MC9328MXL_UART2_CR1   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x80)))
+#define MC9328MXL_UART2_CR2   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x84)))
+#define MC9328MXL_UART2_CR3   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x88)))
+#define MC9328MXL_UART2_CR4   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x8c)))
+#define MC9328MXL_UART2_FCR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x90)))
+#define MC9328MXL_UART2_SR1   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x94)))
+#define MC9328MXL_UART2_SR2   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x98)))
+#define MC9328MXL_UART2_ESC   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0x9c)))
+#define MC9328MXL_UART2_TIM   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa0)))
+#define MC9328MXL_UART2_BIR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa4)))
+#define MC9328MXL_UART2_BMR   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xa8)))
+#define MC9328MXL_UART2_BRC   (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xac)))
+#define MC9328MXL_UART2_IPR1  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb0)))
+#define MC9328MXL_UART2_IPR2  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb4)))
+#define MC9328MXL_UART2_IPR3  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xb8)))
+#define MC9328MXL_UART2_IPR4  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xbc)))
+#define MC9328MXL_UART2_MPR1  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc0)))
+#define MC9328MXL_UART2_MPR2  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc4)))
+#define MC9328MXL_UART2_MPR3  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xc8)))
+#define MC9328MXL_UART2_MPR4  (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xcc)))
+#define MC9328MXL_UART2_TS    (*((volatile uint32_t *)((MC9328MXL_UART2_BASE) + 0xd0)))
+
+typedef struct {
+    volatile uint32_t rxd;
+    volatile uint32_t _res0[15];
+    volatile uint32_t txd;
+    volatile uint32_t _res1[15];
+    volatile uint32_t cr1;
+    volatile uint32_t cr2;
+    volatile uint32_t cr3;
+    volatile uint32_t cr4;
+    volatile uint32_t fcr;
+    volatile uint32_t sr1;
+    volatile uint32_t sr2;
+    volatile uint32_t esc;
+    volatile uint32_t tim;
+    volatile uint32_t bir;
+    volatile uint32_t bmr;
+    volatile uint32_t brc;
+    volatile uint32_t ipr1;
+    volatile uint32_t ipr2;
+    volatile uint32_t ipr3;
+    volatile uint32_t ipr4;
+    volatile uint32_t mpr1;
+    volatile uint32_t mpr2;
+    volatile uint32_t mpr3;
+    volatile uint32_t mpr4;
+    volatile uint32_t ts;
+} mc9328mxl_uart_regs_t;
+
+#define MC9328MXL_UART_RXD_CHARRDY    (bit(15))
+#define MC9328MXL_UART_RXD_ERR        (bit(14))
+#define MC9328MXL_UART_RXD_OVRRUN     (bit(13))
+#define MC9328MXL_UART_RXD_FRMERR     (bit(12))
+#define MC9328MXL_UART_RXD_BRK        (bit(11))
+#define MC9328MXL_UART_RXD_PRERR      (bit(10))
+#define MC9328MXL_UART_RXD_CHARMASK   (0xff)
+
+#define MC9328MXL_UART_CR1_ADEN       (bit(15))
+#define MC9328MXL_UART_CR1_ADBR       (bit(14))
+#define MC9328MXL_UART_CR1_TRDYEN     (bit(13))
+#define MC9328MXL_UART_CR1_IDEN       (bit(12))
+#define MC9328MXL_UART_CR1_ICD4       (0x0 << 10)
+#define MC9328MXL_UART_CR1_ICD8       (0x1 << 10)
+#define MC9328MXL_UART_CR1_ICD16      (0x2 << 10)
+#define MC9328MXL_UART_CR1_ICD32      (0x3 << 10)
+#define MC9328MXL_UART_CR1_RRDYEN     (bit(9))
+#define MC9328MXL_UART_CR1_RDMAEN     (bit(8))
+#define MC9328MXL_UART_CR1_IREN       (bit(7))
+#define MC9328MXL_UART_CR1_TXMPTYEN   (bit(6))
+#define MC9328MXL_UART_CR1_RTSDEN     (bit(5))
+#define MC9328MXL_UART_CR1_SNDBRK     (bit(4))
+#define MC9328MXL_UART_CR1_TDMAEN     (bit(3))
+#define MC9328MXL_UART_CR1_UARTCLKEN  (bit(2))
+#define MC9328MXL_UART_CR1_DOZE       (bit(1))
+#define MC9328MXL_UART_CR1_UARTEN     (bit(0))
+
+
+#define MC9328MXL_UART_CR2_ESCI       (bit(15))
+#define MC9328MXL_UART_CR2_IRTS       (bit(14))
+#define MC9328MXL_UART_CR2_CTSC       (bit(13))
+#define MC9328MXL_UART_CR2_CTS        (bit(12))
+#define MC9328MXL_UART_CR2_ESCEN      (bit(11))
+#define MC9328MXL_UART_CR2_RTEC_RE    (0 << 9)
+#define MC9328MXL_UART_CR2_RTEC_FE    (1 << 9)
+#define MC9328MXL_UART_CR2_RTEC_ANY   (2 << 9)
+#define MC9328MXL_UART_CR2_PREN       (bit(8))
+#define MC9328MXL_UART_CR2_PROE       (bit(7))
+#define MC9328MXL_UART_CR2_STPB       (bit(6))
+#define MC9328MXL_UART_CR2_WS         (bit(5))
+#define MC9328MXL_UART_CR2_RTSEN      (bit(4))
+#define MC9328MXL_UART_CR2_TXEN       (bit(2))
+#define MC9328MXL_UART_CR2_RXEN       (bit(1))
+#define MC9328MXL_UART_CR2_SRST       (bit(0))
+
+#define MC9328MXL_UART_CR3_DPEC_RE    (0 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DPEC_FE    (1 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DPEC_ANY   (2 << 14)  /* UART2 only */
+#define MC9328MXL_UART_CR3_DTREN      (bit(13))  /* UART2 only */
+#define MC9328MXL_UART_CR3_PARERREN   (bit(12))
+#define MC9328MXL_UART_CR3_FRAERREN   (bit(11))
+#define MC9328MXL_UART_CR3_DSR        (bit(10))  /* UART2 only */
+#define MC9328MXL_UART_CR3_DCD        (bit(9))   /* UART2 only */
+#define MC9328MXL_UART_CR3_RI         (bit(8))   /* UART2 only */
+#define MC9328MXL_UART_CR3_RXDSEN     (bit(6))
+#define MC9328MXL_UART_CR3_AIRINTEN   (bit(5))
+#define MC9328MXL_UART_CR3_AWAKEN     (bit(4))
+#define MC9328MXL_UART_CR3_REF25      (bit(3))
+#define MC9328MXL_UART_CR3_REF30      (bit(2))
+#define MC9328MXL_UART_CR3_INVT       (bit(1))
+#define MC9328MXL_UART_CR3_BPEN       (bit(0))
+
+#define MC9328MXL_UART_CR4_CTSTL(_x_) (((_x_) & 0x3f) << 10)
+#define MC9328MXL_UART_CR4_INVR       (bit(9))
+#define MC9328MXL_UART_CR4_ENIRI      (bit(8))
+#define MC9328MXL_UART_CR4_WKEN       (bit(7))
+#define MC9328MXL_UART_CR4_REF16      (bit(6))
+#define MC9328MXL_UART_CR4_IRSC       (bit(5))
+#define MC9328MXL_UART_CR4_TCEN       (bit(3))
+#define MC9328MXL_UART_CR4_BKEN       (bit(2))
+#define MC9328MXL_UART_CR4_OREN       (bit(1))
+#define MC9328MXL_UART_CR4_DREN       (bit(0))
+
+#define MC9328MXL_UART_FCR_TXTL(x)    (((x) & 0x3f) << 10)
+#define MC9328MXL_UART_FCR_RFDIV_1    (5 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_2    (4 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_3    (3 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_4    (2 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_5    (1 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_6    (0 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_7    (6 << 7)
+#define MC9328MXL_UART_FCR_RFDIV_MASK (7 << 7)
+#define MC9328MXL_UART_FCR_RXTL(x)    (((x) & 0x3f) << 0)
+
+#define MC9328MXL_UART_SR1_PARERR     (bit(15))
+#define MC9328MXL_UART_SR1_RTSS       (bit(14))
+#define MC9328MXL_UART_SR1_TRDY       (bit(13))
+#define MC9328MXL_UART_SR1_RTSD       (bit(12))
+#define MC9328MXL_UART_SR1_ESCF       (bit(11))
+#define MC9328MXL_UART_SR1_FRMERR     (bit(10))
+#define MC9328MXL_UART_SR1_RRDY       (bit(9))
+#define MC9328MXL_UART_SR1_RXDS       (bit(6))
+#define MC9328MXL_UART_SR1_AIRINT     (bit(5))
+#define MC9328MXL_UART_SR1_AWAKE      (bit(4))
+
+#define MC9328MXL_UART_SR2_ADET       (bit(15))
+#define MC9328MXL_UART_SR2_TXFE       (bit(14))
+#define MC9328MXL_UART_SR2_DTRF       (bit(13))
+#define MC9328MXL_UART_SR2_IDLE       (bit(12))
+#define MC9328MXL_UART_SR2_IRINT      (bit(8))
+#define MC9328MXL_UART_SR2_WAKE       (bit(7))
+#define MC9328MXL_UART_SR2_RTSF       (bit(4))
+#define MC9328MXL_UART_SR2_TXDC       (bit(3))
+#define MC9328MXL_UART_SR2_BRCD       (bit(2))
+#define MC9328MXL_UART_SR2_ORE        (bit(1))
+#define MC9328MXL_UART_SR2_RDR        (bit(0))
+
+
+#define MC9328MXL_PLL_CSCR   (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x00)))
+#define MC9328MXL_PLL_MPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x04)))
+#define MC9328MXL_PLL_MPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x08)))
+#define MC9328MXL_PLL_SPCTL0 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x0c)))
+#define MC9328MXL_PLL_SPCTL1 (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x10)))
+#define MC9328MXL_PLL_PCDR   (*((volatile uint32_t *)((MC9328MXL_PLL_BASE) + 0x20)))
+
+#define MC9328MXL_PLL_CSCR_CLKOSEL_PERCLK1 (0 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_HCLK    (1 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK48M  (2 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_CLK16M  (3 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_PREMCLK (4 << 29)
+#define MC9328MXL_PLL_CSCR_CLKOSEL_FCLK    (5 << 29)
+
+#define MC9328MXL_PLL_CSCR_USBDIV(_x_)     (((_x_) & 0x7) << 26)
+#define MC9328MXL_PLL_CSCR_SDCNT_1         (0 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_2         (1 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_3         (2 << 24)
+#define MC9328MXL_PLL_CSCR_SDCNT_4         (3 << 24)
+
+#define MC9328MXL_PLL_CSCR_SPLLRSTRT       (bit(22))
+#define MC9328MXL_PLL_CSCR_MPLLRSTRT       (bit(21))
+#define MC9328MXL_PLL_CSCR_CLK16SEL        (bit(18))
+#define MC9328MXL_PLL_CSCR_OSCEN           (bit(17))
+#define MC9328MXL_PLL_CSCR_SYSSEL          (bit(16))
+#define MC9328MXL_PLL_CSCR_PRESC           (bit(15))
+#define MC9328MXL_PLL_CSCR_BLKDIV(_x_)     (((_x_) & 0xf) << 10)
+#define MC9328MXL_PLL_CSCR_SPEN            (bit(1))
+#define MC9328MXL_PLL_CSCR_MPEN            (bit(0))
+
+#define MC9328MXL_PLL_PCDR_PCLK1_MASK      (0x0000000f)
+#define MC9328MXL_PLL_PCDR_PCLK1_SHIFT     (0)
+#define MC9328MXL_PLL_PCDR_PCLK2_MASK      (0x000000f0)
+#define MC9328MXL_PLL_PCDR_PCLK2_SHIFT     (4)
+#define MC9328MXL_PLL_PCDR_PCLK3_MASK      (0x007f0000)
+#define MC9328MXL_PLL_PCDR_PCLK3_SHIFT     (16)
+
+
+#define MC9328MXL_PLL_SPCTL_PD_MASK        (0x3c000000)
+#define MC9328MXL_PLL_SPCTL_PD_SHIFT       (26)
+#define MC9328MXL_PLL_SPCTL_MFD_MASK       (0x03ff0000)
+#define MC9328MXL_PLL_SPCTL_MFD_SHIFT      (16)
+#define MC9328MXL_PLL_SPCTL_MFI_MASK       (0x00003c00)
+#define MC9328MXL_PLL_SPCTL_MFI_SHIFT      (10)
+#define MC9328MXL_PLL_SPCTL_MFN_MASK       (0x000003ff)
+#define MC9328MXL_PLL_SPCTL_MFN_SHIFT      (0)
+
+
+#define MC9328MXL_GPIOA_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x00)))
+#define MC9328MXL_GPIOA_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x04)))
+#define MC9328MXL_GPIOA_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x08)))
+#define MC9328MXL_GPIOA_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x0c)))
+#define MC9328MXL_GPIOA_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x10)))
+#define MC9328MXL_GPIOA_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x14)))
+#define MC9328MXL_GPIOA_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x18)))
+#define MC9328MXL_GPIOA_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x1c)))
+#define MC9328MXL_GPIOA_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x20)))
+#define MC9328MXL_GPIOA_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x24)))
+#define MC9328MXL_GPIOA_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x28)))
+#define MC9328MXL_GPIOA_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x2c)))
+#define MC9328MXL_GPIOA_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x30)))
+#define MC9328MXL_GPIOA_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x34)))
+#define MC9328MXL_GPIOA_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x38)))
+#define MC9328MXL_GPIOA_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x3c)))
+#define MC9328MXL_GPIOA_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOA_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOB_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x00)))
+#define MC9328MXL_GPIOB_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x04)))
+#define MC9328MXL_GPIOB_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x08)))
+#define MC9328MXL_GPIOB_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x0c)))
+#define MC9328MXL_GPIOB_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x10)))
+#define MC9328MXL_GPIOB_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x14)))
+#define MC9328MXL_GPIOB_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x18)))
+#define MC9328MXL_GPIOB_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x1c)))
+#define MC9328MXL_GPIOB_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x20)))
+#define MC9328MXL_GPIOB_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x24)))
+#define MC9328MXL_GPIOB_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x28)))
+#define MC9328MXL_GPIOB_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x2c)))
+#define MC9328MXL_GPIOB_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x30)))
+#define MC9328MXL_GPIOB_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x34)))
+#define MC9328MXL_GPIOB_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x38)))
+#define MC9328MXL_GPIOB_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x3c)))
+#define MC9328MXL_GPIOB_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOB_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOC_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x00)))
+#define MC9328MXL_GPIOC_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x04)))
+#define MC9328MXL_GPIOC_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x08)))
+#define MC9328MXL_GPIOC_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x0c)))
+#define MC9328MXL_GPIOC_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x10)))
+#define MC9328MXL_GPIOC_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x14)))
+#define MC9328MXL_GPIOC_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x18)))
+#define MC9328MXL_GPIOC_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x1c)))
+#define MC9328MXL_GPIOC_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x20)))
+#define MC9328MXL_GPIOC_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x24)))
+#define MC9328MXL_GPIOC_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x28)))
+#define MC9328MXL_GPIOC_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x2c)))
+#define MC9328MXL_GPIOC_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x30)))
+#define MC9328MXL_GPIOC_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x34)))
+#define MC9328MXL_GPIOC_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x38)))
+#define MC9328MXL_GPIOC_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x3c)))
+#define MC9328MXL_GPIOC_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOC_BASE) + 0x40)))
+
+#define MC9328MXL_GPIOD_DDIR    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x00)))
+#define MC9328MXL_GPIOD_OCR1    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x04)))
+#define MC9328MXL_GPIOD_OCR2    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x08)))
+#define MC9328MXL_GPIOD_ICONFA1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x0c)))
+#define MC9328MXL_GPIOD_ICONFA2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x10)))
+#define MC9328MXL_GPIOD_ICONFB1 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x14)))
+#define MC9328MXL_GPIOD_ICONFB2 (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x18)))
+#define MC9328MXL_GPIOD_DR      (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x1c)))
+#define MC9328MXL_GPIOD_GIUS    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x20)))
+#define MC9328MXL_GPIOD_SSR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x24)))
+#define MC9328MXL_GPIOD_ICR1    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x28)))
+#define MC9328MXL_GPIOD_ICR2    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x2c)))
+#define MC9328MXL_GPIOD_IMR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x30)))
+#define MC9328MXL_GPIOD_ISR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x34)))
+#define MC9328MXL_GPIOD_GPR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x38)))
+#define MC9328MXL_GPIOD_SWR     (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x3c)))
+#define MC9328MXL_GPIOD_PUEN    (*((volatile uint32_t *)((MC9328MXL_GPIOD_BASE) + 0x40)))
+
+#define MC9328MXL_AITC_INTCNTL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x00)))
+#define MC9328MXL_AITC_NIMASK     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE) + 0x04)))
+#define MC9328MXL_AITC_INTENNUM   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x08)))
+#define MC9328MXL_AITC_INTDISNUM  (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x0c)))
+#define MC9328MXL_AITC_INTENABLEH (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x10)))
+#define MC9328MXL_AITC_INTENABLEL (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x14)))
+#define MC9328MXL_AITC_INTTYPEH   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x18)))
+#define MC9328MXL_AITC_INTTYPEL   (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x1c)))
+#define MC9328MXL_AITC_NIPIR7     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x20)))
+#define MC9328MXL_AITC_NIPRI6     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x24)))
+#define MC9328MXL_AITC_NIPRI5     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x28)))
+#define MC9328MXL_AITC_NIPRI4     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x2c)))
+#define MC9328MXL_AITC_NIPRI3     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x30)))
+#define MC9328MXL_AITC_NIPRI2     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x34)))
+#define MC9328MXL_AITC_NIPRI1     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x38)))
+#define MC9328MXL_AITC_NIPRI0     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x3c)))
+#define MC9328MXL_AITC_NIVECSR    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x40)))
+#define MC9328MXL_AITC_FIVECSR    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x44)))
+#define MC9328MXL_AITC_INTSRCH    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x48)))
+#define MC9328MXL_AITC_INTSRCL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x4c)))
+#define MC9328MXL_AITC_INTFRCH    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x50)))
+#define MC9328MXL_AITC_INTFRCL    (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x54)))
+#define MC9328MXL_AITC_NIPNDH     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x58)))
+#define MC9328MXL_AITC_NIPNDL     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x5c)))
+#define MC9328MXL_AITC_FIPNDH     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x60)))
+#define MC9328MXL_AITC_FIPNDL     (*((volatile uint32_t *)((MC9328MXL_AITC_BASE)+ 0x64)))
+
+#define MC9328MXL_INT_UART3_PFERR          (0)
+#define MC9328MXL_INT_UART3_RTS            (1)
+#define MC9328MXL_INT_UART3_DTR            (2)
+#define MC9328MXL_INT_UART3_UARTC          (3)
+#define MC9328MXL_INT_UART3_TX             (4)
+#define MC9328MXL_INT_PEN_UP               (5)
+#define MC9328MXL_INT_CSI                  (6)
+#define MC9328MXL_INT_MMA_MAC              (7)
+#define MC9328MXL_INT_MMA                  (8)
+#define MC9328MXL_INT_COMP                 (9)
+#define MC9328MXL_INT_MSIRQ                (10)
+#define MC9328MXL_INT_GPIO_PORTA           (11)
+#define MC9328MXL_INT_GPIO_PORTB           (12)
+#define MC9328MXL_INT_GPIO_PORTC           (13)
+#define MC9328MXL_INT_LCDC                 (14)
+#define MC9328MXL_INT_SIM_IRQ              (15)
+#define MC9328MXL_INT_SIM_DATA             (16)
+#define MC9328MXL_INT_RTC                  (17)
+#define MC9328MXL_INT_RTC_SAM              (18)
+#define MC9328MXL_INT_UART2_PFERR          (19)
+#define MC9328MXL_INT_UART2_RTS            (20)
+#define MC9328MXL_INT_UART2_DTR            (21)
+#define MC9328MXL_INT_UART2_UARTC          (22)
+#define MC9328MXL_INT_UART2_TX             (23)
+#define MC9328MXL_INT_UART2_RX             (24)
+#define MC9328MXL_INT_UART1_PFERR          (25)
+#define MC9328MXL_INT_UART1_RTS            (26)
+#define MC9328MXL_INT_UART1_DTR            (27)
+#define MC9328MXL_INT_UART1_UARTC          (28)
+#define MC9328MXL_INT_UART1_TX             (29)
+#define MC9328MXL_INT_UART1_RX             (30)
+#define MC9328MXL_INT_PEN_DATA             (33)
+#define MC9328MXL_INT_PWM                  (34)
+#define MC9328MXL_INT_MMC_IRQ              (35)
+#define MC9328MXL_INT_SSI2_TX              (36)
+#define MC9328MXL_INT_SSI2_RX              (37)
+#define MC9328MXL_INT_SSI2_ERR             (38)
+#define MC9328MXL_INT_I2C                  (39)
+#define MC9328MXL_INT_SPI2                 (40)
+#define MC9328MXL_INT_SPI1                 (41)
+#define MC9328MXL_INT_SSI_TX               (42)
+#define MC9328MXL_INT_SSI_TX_ERR           (43)
+#define MC9328MXL_INT_SSI_RX               (44)
+#define MC9328MXL_INT_SSI_RX_ERR           (45)
+#define MC9328MXL_INT_TOUCH                (46)
+#define MC9328MXL_INT_USBD0                (47)
+#define MC9328MXL_INT_USBD1                (48)
+#define MC9328MXL_INT_USBD2                (49)
+#define MC9328MXL_INT_USBD3                (50)
+#define MC9328MXL_INT_USBD4                (51)
+#define MC9328MXL_INT_USBD5                (52)
+#define MC9328MXL_INT_USBD6                (53)
+#define MC9328MXL_INT_UART3_RX             (54)
+#define MC9328MXL_INT_BTSYS                (55)
+#define MC9328MXL_INT_BTTIM                (56)
+#define MC9328MXL_INT_BTWUI                (57)
+#define MC9328MXL_INT_TIMER2               (58)
+#define MC9328MXL_INT_TIMER1               (59)
+#define MC9328MXL_INT_DMA_ERR              (60)
+#define MC9328MXL_INT_DMA                  (61)
+#define MC9328MXL_INT_GPIO_PORTD           (62)
+#define MC9328MXL_INT_WDT                  (63)
+
+#define MC9328MXL_AITC_INTCTL_NIAD    BIT(20)
+#define MC9328MXL_AITC_INTCTL_FIAD    BIT(19)
+#define MC9328MXL_AITC_NIMASK_MASK (0X1F)
+#define MC9328MXL_AITC_INTENNUM_MASK  (0X3F)
+#define MC9328MXL_AITC_INTDISNUM_MASK (0X3F)
+#define MC9328MXL_AITC_NIPRIORITY(_int_, _pri_) \
+           (((_pri_) & 0xf) << ((_int_) & 0x7) * 4)
+
+
+#endif /* __MC9328MXL_H__ */
diff --git a/c/src/lib/libbsp/arm/csb336/irq/irq.c b/c/src/lib/libbsp/arm/csb336/irq/irq.c
new file mode 100644
index 0000000000..e5887b9717
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/irq/irq.c
@@ -0,0 +1,51 @@
+/*
+ * Motorola MC9328MXL Interrupt handler
+ *
+ * Copyright (c) 2010 embedded brains GmbH.
+ *
+ * Copyright (c) 2004 by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/score/armv4.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+#include <mc9328mxl.h>
+
+void bsp_interrupt_dispatch(void)
+{
+
+  rtems_vector_number vector = MC9328MXL_AITC_NIVECSR >> 16;
+
+  bsp_interrupt_handler_dispatch(vector);
+}
+
+void bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+
+  if (vector < MC9328MXL_NUM_INTS)
+    MC9328MXL_AITC_INTENNUM = vector;
+}
+
+void bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+
+  if (vector < MC9328MXL_NUM_INTS)
+    MC9328MXL_AITC_INTDISNUM = vector;
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+
+  _CPU_ISR_install_vector(ARM_EXCEPTION_IRQ, _ARMV4_Exception_interrupt, NULL);
+
+  return RTEMS_SUCCESSFUL;
+}
diff --git a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
index 535b66610d..bc2f65cc9c 100644
--- a/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
+++ b/c/src/lib/libbsp/arm/csb336/make/custom/csb336.cfg
@@ -5,7 +5,7 @@
 include $(RTEMS_ROOT)/make/custom/default.cfg
 
 RTEMS_CPU=arm
-RTEMS_CPU_MODEL=mc9328mxl
+RTEMS_CPU_MODEL=shared
 
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it. 
diff --git a/c/src/lib/libbsp/arm/csb336/preinstall.am b/c/src/lib/libbsp/arm/csb336/preinstall.am
index b3c0f66fe8..dbdb788360 100644
--- a/c/src/lib/libbsp/arm/csb336/preinstall.am
+++ b/c/src/lib/libbsp/arm/csb336/preinstall.am
@@ -45,6 +45,10 @@ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
 
+$(PROJECT_INCLUDE)/mc9328mxl.h: include/mc9328mxl.h $(PROJECT_INCLUDE)/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/mc9328mxl.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/mc9328mxl.h
+
 $(PROJECT_INCLUDE)/bspopts.h: include/bspopts.h $(PROJECT_INCLUDE)/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bspopts.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bspopts.h
@@ -69,3 +73,7 @@ $(PROJECT_INCLUDE)/bsp/irq-info.h: ../../shared/include/irq-info.h $(PROJECT_INC
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq-info.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
 
+$(PROJECT_INCLUDE)/bsp/irq.h: include/bsp/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
+
diff --git a/c/src/lib/libbsp/arm/csb336/timer/timer.c b/c/src/lib/libbsp/arm/csb336/timer/timer.c
new file mode 100644
index 0000000000..66ff4a0bf4
--- /dev/null
+++ b/c/src/lib/libbsp/arm/csb336/timer/timer.c
@@ -0,0 +1,93 @@
+/**
+ *  @file
+ *  @brief Cogent CSB336 Timer driver
+ *
+ * This uses timer 2 for timing measurments.
+ */
+
+/*
+ * Copyright (c) 2004 Cogent Computer Systems
+ *        Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <bsp.h>
+#include <rtems/btimer.h>
+#include <mc9328mxl.h>
+
+uint32_t g_start;
+uint32_t g_freq;
+
+bool benchmark_timer_find_average_overhead;
+
+
+/*
+ * Set up Timer 1
+ */
+void benchmark_timer_initialize( void )
+{
+    MC9328MXL_TMR2_TCTL = (MC9328MXL_TMR_TCTL_CLKSRC_PCLK1 |
+                            MC9328MXL_TMR_TCTL_FRR |
+                            MC9328MXL_TMR_TCTL_TEN);
+    /* set prescaler to 1 (register value + 1) */ \
+    MC9328MXL_TMR2_TPRER = 0;
+
+    /* get freq of counter in KHz */
+    g_freq = get_perclk1_freq() / 1000;
+
+    g_start =  MC9328MXL_TMR2_TCN;
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVEREHAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      0  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       1  /* Don't trust a clicks value lower than this */
+
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint32_t t;
+  unsigned long long total;
+
+  t =  MC9328MXL_TMR2_TCN;
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = (t - g_start);
+
+  /* convert to nanoseconds */
+  total = (total * 1000)/ g_freq;
+
+  if ( benchmark_timer_find_average_overhead == 1 ) {
+    return (int) total;
+  } else if ( total < LEAST_VALID ) {
+      return 0;
+  }
+  /*
+   *  Somehow convert total into microseconds
+   */
+
+  return (total - AVG_OVERHEAD);
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
+