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authorAlexander Krutwig <alexander.krutwig@embedded-brains.de>2016-06-28 10:47:15 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2016-06-29 10:38:19 +0200
commit891fa3eb5b51940a83ad33ce54929917fa6809df (patch)
tree9f7fa95e7b491d4331d6b236001ebe1e56cfe035 /c/src/lib/libbsp/arm/atsam/libraries/libchip/include
parentscore: Fix SMP message handling (diff)
downloadrtems-891fa3eb5b51940a83ad33ce54929917fa6809df.tar.bz2
bsp/atsam: Add support for TCM
Diffstat (limited to 'c/src/lib/libbsp/arm/atsam/libraries/libchip/include')
-rw-r--r--c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h15
1 files changed, 15 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h b/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h
index f2c32c1bf1..cef031aa4c 100644
--- a/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h
+++ b/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h
@@ -29,6 +29,9 @@
#ifndef _MPU_H_
#define _MPU_H_
+#ifdef __rtems__
+#include <bsp.h>
+#endif /* __rtems__ */
/*----------------------------------------------------------------------------
* Definitions
@@ -125,17 +128,29 @@
#endif
/* Regions should be a 2^(N+1) where 4 < N < 31 */
+#ifdef __rtems__
+#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin)
+#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1)
+#else /* __rtems__ */
#define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS)
#define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB
+#endif /* __rtems__ */
#if defined MPU_HAS_NOCACHE_REGION
+#ifdef __rtems__
+ #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin)
+ #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1)
+#else /* __rtems__ */
#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1)
#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB
#define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1)
#define SRAM_NOCACHE_END_ADDRESS (SRAM_END_ADDRESS)
+#endif /* __rtems__ */
#else
+#ifndef __rtems__
#define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS + 1)
#define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS) // (2^17) 128 KB
+#endif /* __rtems__ */
#endif
/************** Peripherals memory region macros ********/
#define PERIPHERALS_START_ADDRESS 0x40000000UL