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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-06 15:32:40 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-12-06 15:32:40 +0000 |
| commit | 5d7bfce333f0ef42400e9970adb3b144eb73bbc0 (patch) | |
| tree | c6352e42ab757ecf524c1c366e7d05982623ae1d /c/src/lib/libbsp/arm/arm_bare_bsp/configure.in | |
| parent | 2000-12-06 Joel Sherrill <joel@OARcorp.com> (diff) | |
| download | rtems-5d7bfce333f0ef42400e9970adb3b144eb73bbc0.tar.bz2 | |
2000-12-06 Joel Sherrill <joel@OARcorp.com>
* rtems/score/cpu.h: When mips ISA level is 1, registers in the
context should be 32 not 64 bits.
Diffstat (limited to 'c/src/lib/libbsp/arm/arm_bare_bsp/configure.in')
0 files changed, 0 insertions, 0 deletions