diff options
| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-11-19 15:30:24 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-11-20 11:36:03 +0100 |
| commit | 50440c065e247899ee739d56cb1392c259289031 (patch) | |
| tree | ea5e398d045d623e990d3efdbdf1d6f15151e5f0 /c/src/lib/libbsp/arm/altera-cyclone-v | |
| parent | bsps/arm: L2C 310 drop exclusive cache support (diff) | |
| download | rtems-50440c065e247899ee739d56cb1392c259289031.tar.bz2 | |
bsps/arm: Enable L2C for Cortex-A9 MPCore BSPs
Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v')
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am | 1 | ||||
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | 6 | ||||
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c | 47 |
3 files changed, 7 insertions, 47 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am index 6e2d4311b9..3e02200470 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/Makefile.am @@ -174,6 +174,7 @@ libbsp_a_SOURCES += startup/bspstarthooks.c libbsp_a_SOURCES += startup/nocache-heap.c libbsp_a_SOURCES += startup/mmu-config.c if HAS_SMP +libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c libbsp_a_SOURCES += startup/bspsmp.c endif diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac index fc2b4b08c1..04ebe3af11 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @@ -24,6 +24,12 @@ AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) +RTEMS_BSPOPTS_SET([BSP_DATA_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_DATA_CACHE_ENABLED],[enable data cache]) + +RTEMS_BSPOPTS_SET([BSP_INSTRUCTION_CACHE_ENABLED],[*],[1]) +RTEMS_BSPOPTS_HELP([BSP_INSTRUCTION_CACHE_ENABLED],[enable instruction cache]) + RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U]) RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c index 591e1cd2e8..0d95218c5b 100644 --- a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspsmp.c @@ -12,14 +12,8 @@ * http://www.rtems.org/license/LICENSE. */ -#include <assert.h> - #include <rtems/score/smpimpl.h> -#include <libcpu/arm-cp15.h> - -#include <bsp/irq.h> -#include <bsp/linker-symbols.h> #include <bsp/start.h> #include <socal/alt_rstmgr.h> @@ -27,19 +21,6 @@ #include <socal/hps.h> #include <socal/socal.h> -static void bsp_inter_processor_interrupt(void *arg) -{ - _SMP_Inter_processor_interrupt_handler(); -} - -uint32_t _CPU_SMP_Initialize(void) -{ - uint32_t hardware_count = arm_gic_irq_processor_count(); - uint32_t linker_count = (uint32_t) bsp_processor_count; - - return hardware_count <= linker_count ? hardware_count : linker_count; -} - bool _CPU_SMP_Start_processor(uint32_t cpu_index) { bool started; @@ -66,31 +47,3 @@ bool _CPU_SMP_Start_processor(uint32_t cpu_index) return started; } - -void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) -{ - if (cpu_count > 0) { - rtems_status_code sc; - - sc = rtems_interrupt_handler_install( - ARM_GIC_IRQ_SGI_0, - "IPI", - RTEMS_INTERRUPT_UNIQUE, - bsp_inter_processor_interrupt, - NULL - ); - assert(sc == RTEMS_SUCCESSFUL); - - /* Enable unified L2 cache */ - rtems_cache_enable_data(); - } -} - -void _CPU_SMP_Send_interrupt(uint32_t target_processor_index) -{ - arm_gic_irq_generate_software_irq( - ARM_GIC_IRQ_SGI_0, - ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, - (uint8_t) (1U << target_processor_index) - ); -} |