diff options
| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2013-07-31 09:45:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:22:00 +0100 |
| commit | f73cfe99d099e600be3205efae7980e426ad9ea0 (patch) | |
| tree | c000783a4c6eec14f9ecd7b5fbaf9c34fe9bfbed /c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit | |
| parent | libchip: Add dwmac 10/100/1000 network driver (diff) | |
| download | rtems-f73cfe99d099e600be3205efae7980e426ad9ea0.tar.bz2 | |
bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit')
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit new file mode 100644 index 0000000000..60f99a04f9 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/startup/linkcmds.altcycv_devkit @@ -0,0 +1,18 @@ +MEMORY { + RAM_MMU : ORIGIN = 0x00100000, LENGTH = 16k + NOCACHE : ORIGIN = 0x00200000, LENGTH = 1M + RAM : ORIGIN = 0x00300000, LENGTH = 1024M - 1M - 1M - 1M +} + +SECTIONS { + .nocache : { + bsp_section_nocache_begin = .; + *(SORT(.bsp_nocache*)) + bsp_section_nocache_end = .; + } > NOCACHE AT > NOCACHE + bsp_section_nocache_size = bsp_section_nocache_end - bsp_section_nocache_begin; + bsp_section_nocache_load_begin = LOADADDR (.nocache); + bsp_section_nocache_load_end = bsp_section_nocache_load_begin + bsp_section_nocache_size; +} + +INCLUDE linkcmds.altcycv |