diff options
| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2013-07-31 09:45:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:22:00 +0100 |
| commit | f73cfe99d099e600be3205efae7980e426ad9ea0 (patch) | |
| tree | c000783a4c6eec14f9ecd7b5fbaf9c34fe9bfbed /c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h | |
| parent | libchip: Add dwmac 10/100/1000 network driver (diff) | |
| download | rtems-f73cfe99d099e600be3205efae7980e426ad9ea0.tar.bz2 | |
bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h')
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h b/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h new file mode 100644 index 0000000000..96ab469033 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/include/tm27.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2013 embedded brains GmbH. All rights reserved. + * + * embedded brains GmbH + * Dornierstr. 4 + * 82178 Puchheim + * Germany + * <info@embedded-brains.de> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + */ + +#ifndef _RTEMS_TMTEST27 +#error "This is an RTEMS internal file you must not include directly." +#endif + +#ifndef __tm27_h +#define __tm27_h + +#include <bsp/arm-gic-tm27.h> + +#endif /* __tm27_h */ |