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| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2013-07-31 09:45:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:22:00 +0100 |
| commit | f73cfe99d099e600be3205efae7980e426ad9ea0 (patch) | |
| tree | c000783a4c6eec14f9ecd7b5fbaf9c34fe9bfbed /c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | |
| parent | libchip: Add dwmac 10/100/1000 network driver (diff) | |
| download | rtems-f73cfe99d099e600be3205efae7980e426ad9ea0.tar.bz2 | |
bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac')
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac new file mode 100644 index 0000000000..561a1929e5 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/configure.ac @@ -0,0 +1,56 @@ +## +# +# @file +# +# @brief Configure script of LibBSP for the Altera Cyclone-V platform. +# + +AC_PREREQ([2.69]) +AC_INIT([rtems-c-src-lib-libbsp-arm-xilinx-zynq-a9],[_RTEMS_VERSION],[http://www.rtems.org/bugzilla]) +AC_CONFIG_SRCDIR([bsp_specs]) +RTEMS_TOP(../../../../../..) + +RTEMS_CANONICAL_TARGET_CPU +AM_INIT_AUTOMAKE([no-define nostdinc foreign 1.12.2]) +RTEMS_BSP_CONFIGURE + +RTEMS_PROG_CC_FOR_TARGET +RTEMS_CANONICALIZE_TOOLS +RTEMS_PROG_CCAS + +RTEMS_CHECK_NETWORKING +AM_CONDITIONAL(HAS_NETWORKING,test "$HAS_NETWORKING" = "yes") + +RTEMS_BSPOPTS_SET([BSP_START_RESET_VECTOR],[*],[]) +RTEMS_BSPOPTS_HELP([BSP_START_RESET_VECTOR],[reset vector address for BSP start]) + +RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[altcycv_devkit*],[200000000U]) +RTEMS_BSPOPTS_SET([BSP_ARM_A9MPCORE_PERIPHCLK],[*],[100000000U]) +RTEMS_BSPOPTS_HELP([BSP_ARM_A9MPCORE_PERIPHCLK],[ARM Cortex-A9 MPCore PERIPHCLK clock frequency in Hz]) + +RTEMS_BSPOPTS_SET([CLOCK_DRIVER_USE_FAST_IDLE],[*qemu],[1]) +RTEMS_BSPOPTS_HELP([CLOCK_DRIVER_USE_FAST_IDLE], +[This sets a mode where the time runs as fast as possible when a clock ISR +occurs while the IDLE thread is executing. This can significantly reduce +simulation times.]) + +RTEMS_BSPOPTS_SET([BSP_CONSOLE_MINOR],[*],[0]) +RTEMS_BSPOPTS_HELP([BSP_CONSOLE_MINOR],[minor number of console device]) + +RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_CONSOLE],[*],[0]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_CONSOLE],[configuration for console (UART 0)]) + +RTEMS_BSPOPTS_SET([CYCLONE_V_CONFIG_UART_1],[*],[0]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_CONFIG_UART_1],[configuration for UART 1]) + +RTEMS_BSPOPTS_SET([CYCLONE_V_UART_BAUD],[*],[115200U]) +RTEMS_BSPOPTS_HELP([CYCLONE_V_UART_BAUD],[baud for UARTs]) + +RTEMS_CHECK_SMP +AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"]) + +RTEMS_BSP_CLEANUP_OPTIONS(0, 1) +RTEMS_BSP_LINKCMDS + +AC_CONFIG_FILES([Makefile]) +AC_OUTPUT |