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| author | Ralf Kirchner <ralf.kirchner@embedded-brains.de> | 2013-07-31 09:45:59 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2014-03-13 16:22:00 +0100 |
| commit | f73cfe99d099e600be3205efae7980e426ad9ea0 (patch) | |
| tree | c000783a4c6eec14f9ecd7b5fbaf9c34fe9bfbed /c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs | |
| parent | libchip: Add dwmac 10/100/1000 network driver (diff) | |
| download | rtems-f73cfe99d099e600be3205efae7980e426ad9ea0.tar.bz2 | |
bsp/altera-cyclone-v: New BSP
Implemented so far:
- nocache heap for uncached RAM
- basic timer
- level 1 cache handling for arm cache controller
in arm-cache-l1.h
- level 2 L2C-310 cache controller
- MMU
- DWMAC 1000 ethernet controller
- basic errata handling
- smp startup for second core
Diffstat (limited to 'c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs')
| -rw-r--r-- | c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs b/c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs new file mode 100644 index 0000000000..082653ad22 --- /dev/null +++ b/c/src/lib/libbsp/arm/altera-cyclone-v/bsp_specs @@ -0,0 +1,13 @@ +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{!nostdlib: %{qrtems: start.o%s crti.o%s crtbegin.o%s -e _start}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N} + +*endfile: +%{!qrtems: *(old_endfiles)} %{qrtems: crtend.o%s crtn.o%s } |