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author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1996-09-18 20:56:35 +0000 |
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committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1996-09-18 20:56:35 +0000 |
commit | d6b2bbaf1b5f86c29ddc20c5e698fa0f426a8e9a (patch) | |
tree | 89e6ed7e90c3ce124aeb0b25a933d147a173a612 /c/src/lib/libbsp/a29k/portsw/start | |
parent | pointer arithmetic reworked to be more portable (diff) | |
download | rtems-d6b2bbaf1b5f86c29ddc20c5e698fa0f426a8e9a.tar.bz2 |
new files submitted by Craig Lebakken (lebakken@minn.net) and Derrick Ostertag
(ostertag@transition.com)
Diffstat (limited to 'c/src/lib/libbsp/a29k/portsw/start')
-rw-r--r-- | c/src/lib/libbsp/a29k/portsw/start/amd.ah | 517 | ||||
-rw-r--r-- | c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah | 442 | ||||
-rw-r--r-- | c/src/lib/libbsp/a29k/portsw/start/register.ah | 214 |
3 files changed, 1173 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/a29k/portsw/start/amd.ah b/c/src/lib/libbsp/a29k/portsw/start/amd.ah new file mode 100644 index 0000000000..69f34f173e --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/amd.ah @@ -0,0 +1,517 @@ +; /* @(#)amd.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; Initialization values for registers after RESET +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ +; +;* File information and includes. + + .file "amd.ah" + .ident "@(#)amd.ah 1.1 96/05/23 08:56:58, TEI" + + + +; +;* AMD PROCESSOR SPECIFIC VALUES... +; + +; +;* Processor revision levels... +; + +; PRL values: 31-28 27-24 +; Am29000 0 x +; Am29005 1 x +; Am29050 2 x +; Am29035 3 x +; Am29030 4 x +; Am29200 5 x +; Am29205 5 1x +; Am29240 6 0 +; Manx 7 0 +; Cougar 8 0 + + + .equ AM29000_PRL, 0x00 + + .equ AM29005_PRL, 0x10 + + .equ AM29050_PRL, 0x20 + + .equ AM29035_PRL, 0x30 + + .equ AM29030_PRL, 0x40 + + .equ AM29200_PRL, 0x50 + + .equ AM29205_PRL, 0x58 + + .equ AM29240_PRL, 0x60 + + .equ AM29040_PRL, 0x70 + + .equ MANX_PRL, 0x70 + + .equ COUGAR_PRL, 0x80 + +; +;* data structures sizes. +; + .equ CFGINFO_SIZE, 16*4 + + .equ PGMINFO_SIZE, 16*4 + + .equ VARARGS_SPACE, 16*4 + + .equ WINDOWSIZE, 0x80 +; +;* Am29027 Mode registers +; + + .equ Am29027Mode1, 0x0fc00820 + + .equ Am29027Mode2, 0x00001375 + + + +;* Processor Based Equates and Defines + + .equ SIG_SYNC, -1 + + .equ ENABLE, (SM) + + .equ DISABLE, (ENABLE | DI | DA) + + .equ DISABLE_FZ, (FZ | ENABLE | DI | DA) + + .equ CLR_TRAP, (FZ | DA) + + .equ InitOPS, (TD | SM | (3<<IMShift) | DI | DA) + + .equ InitCPS, (TD | SM | (0<<IMShift) | DI | DA) + + .equ InitCPS1, (TD | SM | (0<<IMShift) | DI ) + + .equ CPS_TMR, (SM | (0<<IMShift) | DI) + + .equ CPS_INT0, (TD | SM | (0<<IMShift)) + + .equ CPS_TMRINT0, (SM | (0<<IMShift)) + + .equ InitCFG, 0x0 + + .equ InitRBP, (B0|B1|B2|B3|B4|B5) + + .equ TMC_VALUE, 0xFFFFFF + + .equ TMR_VALUE, (IE | TMC_VALUE) + + + + + + +;* 29205 specific (internal) peripheral initialization constants. + +; Current Processor Status (CPS) Register. +; Old Processor Status Register (OPS). + + .equ DA, 0x00001 + .equ DI, 0x00002 + .equ IMShift,0x2 + .equ SM, 0x00010 + .equ PI, 0x00020 + .equ PD, 0x00040 + .equ WM, 0x00080 + .equ RE, 0x00100 + .equ LK, 0x00200 + .equ FZ, 0x00400 + .equ TU, 0x00800 + .equ TP, 0x01000 + .equ TE, 0x02000 + .equ IP, 0x04000 + .equ CA, 0x08000 + .equ MM, 0x10000 + .equ TD, 0x20000 + +; Configuration Register (CFG) + + .equ CD, 0x01 + .equ CP, 0x02 + .equ BO, 0x04 + .equ RV, 0x08 + .equ VF, 0x10 + .equ DW, 0x20 + .equ CO, 0x40 + .equ EE, 0x80 + .equ IDShift, 8 + .equ CFG_ID, 0x100 + .equ ILShift, 9 + .equ CFG_ILMask, 0x600 + .equ DDShift, 11 + .equ CFG_DD, 0x800 + .equ DLShift, 12 + .equ CFG_DLMask, 0x3000 + .equ PCEShift, 14 + .equ CFG_PCE, 0x4000 + .equ PMBShift, 16 + .equ D16, 0x8000 + .equ TBOShift, 23 + .equ PRLShift, 24 + +; Channel Control Register (CHC) + + .equ CV, 0x1 + .equ NN, 0x2 + .equ TRShift, 2 + .equ TF, 0x400 + .equ PER, 0x800 + .equ LA, 0x1000 + .equ ST, 0x2000 + .equ ML, 0x4000 + .equ LS, 0x8000 + .equ CRShift, 16 + .equ CNTLShift, 24 + .equ CEShift, 31 + .equ WBERShift, 31 + +; Register Bank Protect (RBP) + .equ B0, 0x1 + .equ B1, 0x2 + .equ B2, 0x4 + .equ B3, 0x8 + .equ B4, 0x10 + .equ B5, 0x20 + .equ B6, 0x40 + .equ B7, 0x80 + .equ B8, 0x100 + .equ B9, 0x200 + .equ B10, 0x400 + .equ B11, 0x800 + .equ B12, 0x1000 + .equ B13, 0x2000 + .equ B14, 0x4000 + .equ B15, 0x8000 + +; Timer Counter + + .equ TCVMask, 0xffffff + +; Timer Reload Register + + .equ IE, 0x1000000 + .equ IN, 0x2000000 + .equ OV, 0x4000000 + .equ TRVMAsk, 0xffffff + +; MMU Configuration + + .equ PSShift, 8 + .equ PS0Shift, 8 + .equ PS1Shift, 12 + +; LRU Recommendation (LRU) + .equ LRUMask, 0xff + +; Reason Vector (RSN) + .equ RSNMask, 0xff + +; Region Mapping Address (RMA0 | RMA1) + .equ PBAMask,0xffff + .equ VBAShift, 16 + +; Region Mapping Control (RMC0 | RMC1) + .equ TIDMask, 0xff + .equ RMC_UE, 0x100 + .equ RMC_UW, 0x200 + .equ RMC_UR, 0x400 + .equ RMC_SE, 0x800 + .equ RMC_SW, 0x1000 + .equ RMC_SR, 0x2000 + .equ RMC_VE, 0x4000 + .equ RMC_IO, 0x10000 + .equ RGSShift, 17 + .equ RMC_PGMShift, 22 + +; Instruction breakpoint Control (IBC0 | IBC1) + .equ BPIDMask, 0xff + .equ BTE, 0x100 + .equ BRM, 0x200 + .equ IBC_BSY, 0x400 + .equ BEN, 0x800 + .equ BHO, 0x1000 + +; Cache Data Register (CDR) + .equ CDR_US, 0x1 + .equ P, 0x2 + .equ CDR_V, 0x4 + .equ IATAGShift, 20 + +; Cache Interface Register (CIR) + .equ CPTRShift, 2 + .equ CIR_RW, 0x1000000 + .equ FSELShift, 28 + +; Indirect Pointer A, B, C (IPA, IPB, IPC) + .equ IPShift, 2 + +; ALU Status (ALU) + .equ FCMask, 0x1F + .equ BPShift, 5 + .equ C, 0x80 + .equ Z, 0x100 + .equ N, 0x200 + .equ ALU_V, 0x400 + .equ DF, 0x800 + +; Byte Pointer + .equ BPMask, 0x3 + +; Load/Store Count Remaining (CR) + .equ CRMask, 0xff + +; Floating Point Environment (FPE) + .equ NM, 0x1 + .equ RM, 0x2 + .equ VM, 0x4 + .equ UM, 0x8 + .equ XM, 0x10 + .equ DM, 0x20 + .equ FRMShift, 6 + .equ FF, 0x100 + .equ ACFShift, 9 + +; Integer Environment (INTE) + .equ MO, 0x1 + .equ DO, 0x2 + +; Floating Point Status (FPS) + .equ NS, 0x1 + .equ RS, 0x2 + .equ VS, 0x4 + .equ FPS_US, 0x8 + .equ XS, 0x10 + .equ DS, 0x20 + .equ NT, 0x100 + .equ RT, 0x200 + .equ VT, 0x400 + .equ UT, 0x800 + .equ XT, 0x1000 + .equ DT, 0x2000 + +; Exception Opcode (EXOP) + .equ IOPMask, 0xff + +; TLB Entry Word 0 +; .equ TIDMask, 0xff already defined above + .equ TLB_UE, 0x100 + .equ TLB_UW, 0x200 + .equ TLB_UR, 0x400 + .equ TLB_SE, 0x800 + .equ TLB_SW, 0x1000 + .equ TLB_SR, 0x2000 + .equ TLB_VE, 0x4000 + .equ VTAGShift, 15 + +; TLB Entry Word 1 + .equ TLB_IO, 0x1 + .equ U, 0x2 + .equ TLB_PGMShift, 6 + .equ RPNShift, 10 + +; Am29200 ROM Control bits. + .equ RMCT_DW0Shift, 29 + .equ RMCT_DW1Shift, 21 + .equ RMCT_DW2Shift, 13 + .equ RMCT_DW3Shift, 5 + +; Am29200 DRAM Control bits. + .equ DW3, (1<<18) + .equ DW2, (1<<22) + .equ DW1, (1<<26) + .equ DW0, (1<<30) + + ; Internal peripheral address assignments. + .equ RMCT, 0x80000000 + .equ RMCF, 0x80000004 + .equ DRCT, 0x80000008 + .equ DRCF, 0x8000000C + .equ DRM0, 0x80000010 + .equ DRM1, 0x80000014 + .equ DRM2, 0x80000018 + .equ DRM3, 0x8000001C + .equ PIACT0, 0x80000020 + .equ PIACT1, 0x80000020 + .equ ICT, 0x80000028 + .equ DMCT0, 0x80000030 + .equ DMAD0, 0x80000034 + .ifdef revA + .equ TAD0, 0x80000036 + .equ TCN0, 0x8000003A + .else + .equ TAD0, 0x80000070 ; default + .equ TCN0, 0x8000003C ; default + .endif + .equ DMCN0, 0x80000038 + .equ DMCT1, 0x80000040 + .equ DMAD1, 0x80000044 + .equ DMCN1, 0x80000048 + .equ SPCT, 0x80000080 + .equ SPST, 0x80000084 + .equ SPTH, 0x80000088 + .equ SPRB, 0x8000008C + .equ BAUD, 0x80000090 + .equ PPCT, 0x800000C0 + .equ PPST, 0x800000C1 + .equ PPDT, 0x800000C4 + .equ POCT, 0x800000D0 + .equ PIN, 0x800000D4 + .equ POUT, 0x800000D8 + .equ POEN, 0x800000DC + .equ VCT, 0x800000E0 + .equ TOP, 0x800000E4 + .equ SIDE, 0x800000E8 + .equ VDT, 0x800000EC + + ; Interrupt Controller Register bits. + .equ TXDI, (1<<5) + .equ RXDI, (1<<6) + .equ RXSI, (1<<7) + .equ PPI, (1<<11) + .equ DMA1I, (1<<13) + .equ DMA0I, (1<<14) + .equ IOPIMask, (0xFF<<16) + .equ VDI, (1<<27) + .equ ICT200_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) + .equ ICT205_I, (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI) + + ; Serial port Initialization bits + .equ NO_PARITY, 0 + + + ; SPST bits + .equ THREShift, 22 + +;* REGISTER Addresses + + .equ ROMCntlRegAddr, 0x80000000 + + .equ ROMCfgRegAddr, 0x80000004 + + .equ DRAMCntlRegAddr, 0x80000008 + + .equ DRAMCfgRegAddr, 0x8000000C + + .equ DRAMMap0RegAddr, 0x80000010 + + .equ DRAMMap1RegAddr, 0x80000014 + + .equ DRAMMap2RegAddr, 0x80000018 + + .equ DRAMMap3RegAddr, 0x8000001C + + .equ PIACntl0RegAddr, 0x80000020 + + .equ PIACntl1RegAddr, 0x80000024 + + .equ INTRCntlRegAddr, 0x80000028 + + .equ DMACntl0RegAddr, 0x80000030 + + .equ DMACntl1RegAddr, 0x80000040 + + .equ SERPortCntlRegAddr, 0x80000080 + + .equ SERPortStatRegAddr, 0x80000084 + + .equ SERPortTHLDRegAddr, 0x80000088 + + .equ SERPortRbufRegAddr, 0x8000008C + + .equ SERPortBaudRegAddr, 0x80000090 + + .equ PARPortCntlRegAddr, 0x800000C0 + + .equ PIOCntlRegAddr, 0x800000D0 + + .equ PIOInpRegAddr, 0x800000D4 + + .equ PIOOutRegAddr, 0x800000D8 + + .equ PIOOutEnaRegAddr, 0x800000DC + + .equ VCTCntlRegAddr, 0x800000E0 + +; +;* Control constants +; + +;* AM29030 Timer related constants. + + .equ TMR_IE, 0x01000000 + + .equ TMR_IN, 0x02000000 + + .equ TMR_OV, 0x04000000 + + .equ TMC_INITCNT, 1613 + +; +;* System initialization values. +; + + .equ __os_version, 0x0001 ; + + .equ STACKSize, 0x8000 ; + + .equ PGMExecMode, 0x0000 ; + + .equ TSTCK_OFST, 28 * 4 + + .equ CSTCK_OFST, 29 * 4 + + .equ TMSTCK_OFST, 30 * 4 + + .equ CMSTCK_OFST, 31 * 4 + + .equ CTXSW_OK, 0xA55A ; ctx switch ok + + .set NV_STARTOFST, 0x20 ; 32 bytes + + .set NV_BAUDOFST, 0x00 ; 00 bytes + + .set reg_cir, 29 + + .set reg_cdr, 30 + + .equ MSG_BUFSIZE, 0x1000 ; serial buffer size + + .equ ILLOPTRAP, 0 + + .equ UATRAP, 1 + + .equ PVTRAP, 5 + + .equ UITLBMISSTRAP, 8 + + .equ UDTLBMISSTRAP, 9 + + .equ TIMERTRAP, 14 + + .equ TRACETRAP, 15 + + .equ XLINXTRAP, 16 + + .equ SERIALTRAP, 17 + + .equ SLOWTMRTRAP, 18 + + .equ PORTTRAP, 19 + + .equ SVSCTRAP, 80 + + .equ SVSCTRAP1, 81 + + .equ V_CACHETRAP, 66 ; + + .equ V_SETSERVICE, 67 ; diff --git a/c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah b/c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah new file mode 100644 index 0000000000..a994719c58 --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/pswmacro.ah @@ -0,0 +1,442 @@ +; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; macros: Do_install and init_TLB +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ + +;* File information and includes. + + .file "macro.ah" + .ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI" + + + .macro CONST32, RegName, RegValue + const RegName, RegValue + consth RegName, RegValue + .endm + + .macro CONSTX, RegName, RegValue + .if (RegValue) <= 0x0000ffff + const RegName, RegValue + .else + const RegName, RegValue + consth RegName, RegValue + .endif + .endm + + .macro PRODEV, RegName + srl RegName, RegName, 24 + .endm + +; +;* MACRO TO INSTALL VECTOR TABLE ENTRIES +; + +;* Assumes vector table address in v0 + + .macro _setvec, trapnum, trapaddr + mfsr v0, vab ; + const v2, trapnum ; + sll v1, v2, 2 ; + add v1, v1, v0 ; v0 has location of vector tab + + const v2, trapaddr ; + consth v2, trapaddr ; + store 0, 0, v2, v1 ; + nop ; + .endm + + .macro syscall, name + const tav, HIF_@name ; + asneq V_SYSCALL, gr1, gr1 ; + nop ; + nop ; + .endm + + + +;* MACRO TO INSTALL VECTOR TABLE ENTRIES + + .macro Do_Install, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_Install + nop + .endm + + .macro Do_InstallX, V_Number, V_Address + const lr4, V_Address + consth lr4, V_Address + const lr3, V_Number * 4 + consth lr3, V_Number * 4 + call lr0, V_InstallX + nop + .endm + + + +; push a register onto the stack + .macro pushreg, reg, sp + sub sp, sp, 4 ; adjust stack pointer + store 0, 0, reg, sp ; push register + .endm + + .macro push, sp, reg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop the register from stack + .macro popreg, reg, sp + load 0, 0, reg, sp ; pop register + add sp, sp, 4 ; adjust stack pointer + .endm + .macro pop, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + .endm + +; push a special register onto stack + .macro pushspcl, spcl, tmpreg, sp + sub sp, sp, 4 ; adjust stack pointer + mfsr tmpreg, spcl ; get spcl reg + store 0, 0, tmpreg, sp ; push onto stack + .endm + + .macro pushsr, sp, reg, sreg + mfsr reg, sreg + sub sp, sp, 4 + store 0, 0, reg, sp + .endm + +; pop a special register from stack + .macro popspcl, spcl, tmpreg, sp + load 0, 0, tmpreg, sp ; pop from stack + add sp, sp, 4 ; adjust stack pointer + mtsr spcl, tmpreg ; set spcl reg + .endm + + .macro popsr, sreg, reg, sp + load 0, 0, reg, sp + add sp, sp, 4 + mtsr sreg, reg + .endm + +; +; save freeze mode registers on memory stack. +; + + .macro SaveFZState, tmp1, tmp2 + + ; save freeze mode registers. + + pushspcl pc0, tmp1, msp + pushspcl pc1, tmp1, msp + pushspcl alu, tmp1, msp + + pushspcl cha, tmp1, msp + pushspcl chd, tmp1, msp + pushspcl chc, tmp1, msp + + pushspcl ops, tmp1, msp + + ; turn freeze off + + const tmp2, FZ + mfsr tmp1, cps + andn tmp1, tmp1, tmp2 + mtsr cps, tmp1 + .endm + +; restore freeze mode registers from memory stack. + + .macro RestoreFZState, tmp1, tmp2 + + ; turn freeze on + + const tmp2, (FZ|DI|DA) + mfsr tmp1, cps + or tmp1, tmp1, tmp2 + mtsr cps, tmp1 + + ; restore freeze mode registers. + + popspcl ops, tmp1, msp + popspcl chc, tmp1, msp + popspcl chd, tmp1, msp + popspcl cha, tmp1, msp + popspcl alu, tmp1, msp + popspcl pc1, tmp1, msp + popspcl pc0, tmp1, msp + .endm + +; +;* +; + .equ WS, 512 ; window size + .equ RALLOC, 4 * 4 ; stack alloc for C + .equ SIGCTX_UM_SIZE, 40 * 4 ; + .equ SIGCTX_RFB, (38) * 4 ; user mode saved + .equ SIGCTX_SM_SIZE, 12 * 4 ; + .equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ; + .equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ; + + .macro sup_sv + add it2, trapreg, 0 ; transfer signal # + sub msp, msp, 4 ; + store 0, 0, it2, msp ; save signal number + sub msp, msp, 4 ; push gr1 + + store 0, 0, gr1, msp ; + sub msp, msp, 4 ; push rab + store 0, 0, rab, msp ; + const it0, WS ; Window size + + sub rab, rfb, it0 ; set rab = rfb-512 + pushsr msp, it0, PC0 ; save program counter0 + pushsr msp, it0, PC1 ; save program counter1 + pushsr msp, it0, PC2 ; save program counter2 + + pushsr msp, it0, CHA ; save channel address + pushsr msp, it0, CHD ; save channel data + pushsr msp, it0, CHC ; save channel control + pushsr msp, it0, ALU ; save alu + + pushsr msp, it0, OPS ; save ops + sub msp, msp, 4 ; + store 0, 0, tav, msp ; push tav + mtsrim chc, 0 ; no loadm/storem + + mfsr it0, ops ; get ops value + const it1, (TD | DI) ; disable interrupts + consth it1, (TD | DI) ; disable interrupts + or it0, it0, it1 ; set bits + + mtsr ops, it0 ; set new ops + const it0, sigcode ; signal handler + consth it0, sigcode ; signal handler + mtsr pc1, it0 ; store pc1 + + add it1, it0, 4 ; next addr + mtsr pc0, it1 ; store pc1 location + iret ; return + nop ; ALIGN + .endm + + .macro sig_return + mfsr it0, cps ; get processor status + const it1, FZ|DA ; Freeze + traps disable + or it0, it0, it1 ; to set FZ+DA + mtsr cps, it0 ; in freeze mode + + load 0, 0, tav, msp ; restore tav + add msp, msp, 4 ; + + popsr OPS,it0, msp ; + popsr ALU,it0, msp ; + popsr CHC,it0, msp ; + popsr CHD,it0, msp ; + + popsr CHA,it0, msp ; + popsr PC2,it0, msp ; + popsr PC1,it0, msp ; + popsr PC0,it0, msp ; + + load 0, 0, rab, msp ; + add msp, msp, 4 ; + load 0, 0, it0, msp ; + add gr1, it0, 0 ; pop rsp + + add msp, msp, 8 ; discount signal # + iret + .endm + + .macro repair_R_stack + add v0, msp, SIGCTX_GR1 ; interrupted gr1 + load 0, 0, v2, v0 ; + add v0, msp, SIGCTX_RFB ; + load 0, 0, v3, v0 ; interupted rfb + + const v1, WS ; + sub v1, v3, v1 ; rfb-512 + cpltu v0, v2, v1 ; test gr1 < rfb-512 + jmpf v0, $1 ; + + add gr1, rab, 0 ; + add v2, v1, 0 ; set LB = rfb-512 +$1: +;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill +;* if no, LB=gr1 interrupted cache < 126 registers + cpleu v0, v2, rfb ; test LB<=rfb + jmpf v0, $2 ; + nop ; + add v2, rfb, 0 ; +$2: + cpeq v0, v3, rfb ; fill rfb->'rfb + jmpt v0, $3 ; if rfb==rfb' + const tav, (0x80<<2) ; prepare for fill + or tav, tav, v2 ; + + mtsr IPA, tav ; IPA=LA<<2 + sub tav, v3, gr98 ; cache fill LA->rfb + srl tav, tav, 2 ; convert to words + sub tav, tav, 1 ; + + mtsr cr, tav ; + loadm 0, 0, gr0, v2 ; fill from LA->rfb +$3: + add rfb, v3, 0 ; move rfb upto 'rfb + sub rab, v1, 0 ; assign rab to rfb-512 + + add v0, msp, SIGCTX_GR1 ; + load 0, 0, v2, v0 ; v0 = interrupted gr1 + add gr1, v2, 0 ; move gr1 upto 'gr1 + nop ; + .endm + + .macro repair_regs + mtsrim cr, 29 - 1 ; to restore locals + loadm 0, 0, v0, msp ; + add msp, msp, 29*4 ; + popsr Q, tav, msp ; + + popsr IPC, tav, msp ; + popsr IPB, tav, msp ; + popsr IPA, tav, msp ; + pop FPStat3, msp ; floating point regs + + pop FPStat2, msp ; floating point regs + pop FPStat1, msp ; floating point regs + pop FPStat0, msp ; floating point regs + + add msp, msp, 3*4 ; R-stack repaired + .endm + +; +;*HIF related... +; + + + + +; send the message in bufaddr to Montip. + .macro SendMessageToMontip, bufaddr + const lr2, bufaddr +$1: + call lr0, _msg_send + consth lr2, bufaddr + cpeq gr96, gr96, 0 + jmpf gr96, $1 + const lr2, bufaddr + .endm + +; build a HIF_CALL message in bufaddr to send to montip. + .macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2 + const tmp1, bufaddr + consth tmp1, bufaddr + const tmp2, HIF_CALL_MSGCODE + store 0, 0, tmp2, tmp1 ; msg code + add tmp1, tmp1, 4 + const tmp2, HIF_CALL_MSGLEN + store 0, 0, tmp2, tmp1 ; msg len + add tmp1, tmp1, 4 + store 0, 0, gr121, tmp1 ; service number + add tmp1, tmp1, 4 + store 0, 0, lr2, tmp1 ; lr2 + add tmp1, tmp1, 4 + store 0, 0, lr3, tmp1 ; lr3 + add tmp1, tmp1, 4 + store 0, 0, lr4, tmp1 ; lr4 + .endm + +; +;* +;* All the funky AMD style macros go in here...simply for +;* compatility +; +; + .macro IMPORT, symbol + .extern symbol + .endm + + .macro GLOBAL, symbol + .global symbol + .endm + + .macro USESECT, name, type + .sect name, type + .use name + .endm + + .macro SECTION, name, type + .sect name, type + .endm + + .macro FUNC, fname, lineno + .global fname +fname: + .endm + + .macro ENDFUNC, fname, lineno + .endm + +;*************************************LONG + .macro LONG, varname +varname: + .block 4 + .endm + +;*************************************UNSIGNED LONG + .macro ULONG, varname +varname: + .block 4 + .endm + +;*************************************SHORT + .macro SHORT, varname +varname: + .block 2 + .endm + +;*************************************CHAR + .macro CHAR, varname +varname: + .block 1 + .endm + +;*************************************LONGARRAY + .macro LONGARRAY, name, count +name: + .block count*4 + .endm + +;*************************************SHORTARRAY + + .macro SHORTARRAY, name, count +name: + .block count*2 + .endm + +;*************************************CHARARRAY + + .macro CHARARRAY, name, count +name: + .block count + .endm + + +;*************************************VOID_FPTR + + .macro VOID_FPTR, name +name: + .block 4 + .endm diff --git a/c/src/lib/libbsp/a29k/portsw/start/register.ah b/c/src/lib/libbsp/a29k/portsw/start/register.ah new file mode 100644 index 0000000000..1dced5b043 --- /dev/null +++ b/c/src/lib/libbsp/a29k/portsw/start/register.ah @@ -0,0 +1,214 @@ +; /* @(#)register.ah 1.1 96/05/23 08:56:57, TEI */ +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; naming of various registers +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +; /* $Id$ */ + +;* File information and includes. + + .file "register.ah" + .ident "@(#)register.ah 1.1 96/05/23 08:56:57, TEI\n" + +;* Register Stack pointer and frame pointer registers. + + .extern Rrsp, Rfp + + .reg regsp, %%Rrsp + .reg fp, %%Rfp + + + .extern RTrapReg + .extern Rtrapreg + + .reg TrapReg, %%RTrapReg + .reg trapreg, %%Rtrapreg + + +;* Operating system Interrupt handler registers (gr64-gr67) + + .extern ROSint0, ROSint1, ROSint2, ROSint3 + + .reg OSint0, %%ROSint0 + .reg OSint1, %%ROSint1 + .reg OSint2, %%ROSint2 + .reg OSint3, %%ROSint3 + + .reg it0, %%ROSint0 + .reg it1, %%ROSint1 + .reg it2, %%ROSint2 + .reg it3, %%ROSint3 + + + +;* Operating system temporary (or scratch) registers (gr68-gr79) + + .extern ROStmp0, ROStmp1, ROStmp2, ROStmp3 + .extern ROStmp4, ROStmp5, ROStmp6, ROStmp7 + .extern ROStmp8, ROStmp9, ROStmp10, ROStmp11 + + .reg OStmp0, %%ROStmp0 + .reg OStmp1, %%ROStmp1 + .reg OStmp2, %%ROStmp2 + .reg OStmp3, %%ROStmp3 + + .reg OStmp4, %%ROStmp4 + .reg OStmp5, %%ROStmp5 + .reg OStmp6, %%ROStmp6 + .reg OStmp7, %%ROStmp7 + + .reg OStmp8, %%ROStmp8 + .reg OStmp9, %%ROStmp9 + .reg OStmp10, %%ROStmp10 + .reg OStmp11, %%ROStmp11 + + + .reg kt0, %%ROStmp0 + .reg kt1, %%ROStmp1 + .reg kt2, %%ROStmp2 + .reg kt3, %%ROStmp3 + + .reg kt4, %%ROStmp4 + .reg kt5, %%ROStmp5 + .reg kt6, %%ROStmp6 + .reg kt7, %%ROStmp7 + + .reg kt8, %%ROStmp8 + .reg kt9, %%ROStmp9 + .reg kt10, %%ROStmp10 + .reg kt11, %%ROStmp11 + + + .reg TempReg0, %%ROSint0 + .reg TempReg1, %%ROSint1 + .reg TempReg2, %%ROSint2 + .reg TempReg3, %%ROSint3 + + .reg TempReg4, %%ROStmp0 + .reg TempReg5, %%ROStmp1 + .reg TempReg6, %%ROStmp2 + .reg TempReg7, %%ROStmp3 + + .reg TempReg8, %%ROStmp4 + .reg TempReg9, %%ROStmp5 + .reg TempReg10, %%ROStmp6 + .reg TempReg11, %%ROStmp7 + + .reg TempReg12, %%ROStmp8 + .reg TempReg13, %%ROStmp9 + .reg TempReg14, %%ROStmp10 + .reg TempReg15, %%ROStmp11 + + +;* Assigned static registers + + .extern RSpillAddrReg, RFillAddrReg, RSignalAddrReg + .extern Rpcb, Retc + .extern RTimerExt, RTimerUtil, RLEDReg, RERRReg + .extern Ret0, Ret1, Ret2, Ret3, Ret4, Ret5, Ret6, Ret7, Reta, Retb + .extern Retx, Rety, Retz + + + .reg SpillAddrReg, %%RSpillAddrReg + .reg FillAddrReg, %%RFillAddrReg + .reg SignalAddrReg, %%RSignalAddrReg + .reg pcb, %%Rpcb + + .reg etx, %%Retx + .reg ety, %%Rety + .reg etz, %%Retz + .reg eta, %%Reta + + .reg etb, %%Retb + .reg etc, %%Retc + .reg TimerExt, %%RTimerExt + .reg TimerUtil, %%RTimerUtil + + .reg LEDReg, %%RLEDReg + .reg ERRReg, %%RERRReg + + + .reg et0, %%Ret0 + .reg et1, %%Ret1 + .reg et2, %%Ret2 + .reg et3, %%Ret3 + + .reg et4, %%Ret4 + .reg et5, %%Ret5 + .reg et6, %%Ret6 + .reg et7, %%Ret7 + +; + .equ SCB1REG_NUM, 88 + .reg SCB1REG_PTR, %%Ret0 + +; The floating point trap handlers need a few static registers + + .extern RFPStat0, RFPStat1, RFPStat2, RFPStat3 + .extern Rheapptr, RHeapPtr, RArgvPtr + + .reg FPStat0, %%RFPStat0 + .reg FPStat1, %%RFPStat1 + .reg FPStat2, %%RFPStat2 + .reg FPStat3, %%RFPStat3 + + .reg heapptr, %%Rheapptr + .reg HeapPtr, %%RHeapPtr + .reg ArgvPtr, %%RArgvPtr + + .extern RXLINXReg, RVMBCReg, RUARTReg, RETHERReg + + .reg XLINXReg, %%RXLINXReg + .reg VMBCReg, %%RVMBCReg + .reg UARTReg, %%RUARTReg + .reg ETHERReg, %%RXLINXReg + +;* Compiler and programmer registers. (gr96-gr127) + + .extern Rv0, Rv1, Rv2, Rv3, Rv4, Rv5, Rv6, Rv7, Rv8, Rv9 + .extern Rv10, Rv11, Rv12, Rv13, Rv14, Rv15 + + .reg v0, %%Rv0 + .reg v1, %%Rv1 + .reg v2, %%Rv2 + .reg v3, %%Rv3 + + .reg v4, %%Rv4 + .reg v5, %%Rv5 + .reg v6, %%Rv6 + .reg v7, %%Rv7 + + .reg v8, %%Rv8 + .reg v9, %%Rv9 + .reg v10, %%Rv10 + .reg v11, %%Rv11 + + .reg v12, %%Rv12 + .reg v13, %%Rv13 + .reg v14, %%Rv14 + .reg v15, %%Rv15 + + .extern Rtv0, Rtv1, Rtv2, Rtv3, Rtv4 + + .reg tv0, %%Rtv0 + .reg tv1, %%Rtv1 + .reg tv2, %%Rtv2 + .reg tv3, %%Rtv3 + .reg tv4, %%Rtv4 + +; **************************************************************************** +; For uatrap +; register definitions -- since this trap handler must allow for +; nested traps and interrupts such as TLB miss, protection violation, +; or Data Access Exception, and these trap handlers use the shared +; Temp registers, we must maintain our own that are safe over user- +; mode loads and stores. The following must be assigned global +; registers which are not used in INTR[0-3], TRAP[0-1], TLB miss, +; TLB protection violation, or data exception trap handlers. + +; .reg cha_cpy, OStmp4 ; copy of CHA +; .reg chd_cpy, OStmp5 ; copy of CHD +; .reg chc_cpy, OStmp6 ; copy of CHC +; .reg LTemp0, OStmp7 ; local temp 0 +; .reg LTemp1, OStmp8 ; local temp 1 + +; **************************************************************************** |