diff options
author | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-13 21:53:38 +0000 |
---|---|---|
committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 2000-06-13 21:53:38 +0000 |
commit | cf1f72ea339287cf6f780b2e34b8092ce08da6b0 (patch) | |
tree | 3b6eee762364ef5304ebae3bf5da4e9296eafa29 /c/src/exec | |
parent | Added .cvsignore. (diff) | |
download | rtems-cf1f72ea339287cf6f780b2e34b8092ce08da6b0.tar.bz2 |
Moved i386 and m68k cache management code to libcpu. Everything
now is an implementation of the prototypes in rtems/rtems/cache.h.
The libcpu/i386/wrapup directory is no longer needed.
The PowerPC needs this done to it.
Diffstat (limited to 'c/src/exec')
-rw-r--r-- | c/src/exec/libcsupport/src/malloc.c | 22 | ||||
-rw-r--r-- | c/src/exec/rtems/include/rtems.h | 1 | ||||
-rw-r--r-- | c/src/exec/rtems/include/rtems/rtems/cache.h | 140 | ||||
-rw-r--r-- | c/src/exec/rtems/src/Makefile.am | 2 | ||||
-rw-r--r-- | c/src/exec/rtems/src/cache.c | 252 | ||||
-rw-r--r-- | c/src/exec/score/cpu/i386/rtems/score/i386.h | 95 | ||||
-rw-r--r-- | c/src/exec/score/cpu/m68k/rtems/score/m68k.h | 211 |
7 files changed, 2 insertions, 721 deletions
diff --git a/c/src/exec/libcsupport/src/malloc.c b/c/src/exec/libcsupport/src/malloc.c index dc6824891a..0396b051be 100644 --- a/c/src/exec/libcsupport/src/malloc.c +++ b/c/src/exec/libcsupport/src/malloc.c @@ -419,26 +419,4 @@ void _free_r( free( ptr ); } - -/* - * rtems_cache_aligned_malloc - * - * DESCRIPTION: - * - * This function is used to allocate storage that spans an - * integral number of cache blocks. - */ -RTEMS_INLINE_ROUTINE void * rtems_cache_aligned_malloc ( - size_t nbytes -) -{ - /* - * Arrange to have the user storage start on the first cache - * block beyond the header. - */ - return (void *) ((((unsigned long) malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 )) - + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) ); -} - #endif - diff --git a/c/src/exec/rtems/include/rtems.h b/c/src/exec/rtems/include/rtems.h index 0d82b3d4d0..16b6e64705 100644 --- a/c/src/exec/rtems/include/rtems.h +++ b/c/src/exec/rtems/include/rtems.h @@ -42,6 +42,7 @@ extern "C" { #include <rtems/init.h> #include <rtems/rtems/tasks.h> #include <rtems/rtems/intr.h> +#include <rtems/rtems/cache.h> #include <rtems/rtems/clock.h> #include <rtems/extension.h> #include <rtems/rtems/timer.h> diff --git a/c/src/exec/rtems/include/rtems/rtems/cache.h b/c/src/exec/rtems/include/rtems/rtems/cache.h deleted file mode 100644 index 1e71a9bf3a..0000000000 --- a/c/src/exec/rtems/include/rtems/rtems/cache.h +++ /dev/null @@ -1,140 +0,0 @@ -/* cache.h - * - * Cache Manager - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * - * The functions in this file define the API to the RTEMS Cache Manager and - * are divided into data cache and instruction cache functions. Data cache - * functions are only declared if a data cache is supported. Instruction - * cache functions are only declared if an instruction cache is supported. - * Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is - * defined, where x E {DATA, INST}. These definitions are found in the CPU - * dependent source files in the supercore, often - * - * rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h - * - * The functions below are implemented with CPU dependent inline routines - * also found in the above file. In the event that a CPU does not support a - * specific function, the CPU dependent routine does nothing (but does exist). - * - * At this point, the Cache Manager makes no considerations, and provides no - * support for BSP specific issues such as a secondary cache. In such a system, - * the CPU dependent routines would have to be modified, or a BSP layer added - * to this Manager. - */ - -#ifndef __CACHE_h -#define __CACHE_h - -#ifdef __cplusplus -extern "C" { -#endif - -#include <rtems/system.h> -#include <sys/types.h> - - -/* THESE FUNCTIONS ONLY EXIST IF WE HAVE A DATA CACHE */ -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - -/* - * This function is called to flush the data cache by performing cache - * copybacks. It must determine how many cache lines need to be copied - * back and then perform the copybacks. - */ -void rtems_flush_multiple_data_cache_lines( const void *, size_t ); - -/* - * This function is responsible for performing a data cache invalidate. - * It must determine how many cache lines need to be invalidated and then - * perform the invalidations. - */ -void rtems_invalidate_multiple_data_cache_lines( const void *, size_t ); - -/* - * This function is responsible for performing a data cache flush. - * It flushes the entire cache. - */ -void rtems_flush_entire_data_cache( void ); - -/* - * This function is responsible for performing a data cache - * invalidate. It invalidates the entire cache. - */ -void rtems_invalidate_entire_data_cache( void ); - -/* - * This function returns the data cache granularity. - */ -int rtems_get_data_cache_line_size( void ); - -/* - * This function freezes the data cache. - */ -void rtems_freeze_data_cache( void ); - -/* - * This function unfreezes the data cache. - */ -void rtems_unfreeze_data_cache( void ); - -/* - * These functions enable/disable the data cache. - */ -void rtems_enable_data_cache( void ); -void rtems_disable_data_cache( void ); -#endif - - -/* THESE FUNCTIONS ONLY EXIST IF WE HAVE AN INSTRUCTION CACHE */ -#if defined(_CPU_INST_CACHE_ALIGNMENT) - -/* - * This function is responsible for performing an instruction cache - * invalidate. It must determine how many cache lines need to be invalidated - * and then perform the invalidations. - */ -void rtems_invalidate_multiple_inst_cache_lines( const void *, size_t ); - -/* - * This function is responsible for performing an instruction cache - * invalidate. It invalidates the entire cache. - */ -void rtems_invalidate_entire_inst_cache( void ); - -/* - * This function returns the instruction cache granularity. - */ -int rtems_get_inst_cache_line_size( void ); - -/* - * This function freezes the instruction cache. - */ -void rtems_freeze_inst_cache( void ); - -/* - * This function unfreezes the instruction cache. - */ -void rtems_unfreeze_inst_cache( void ); - -/* - * These functions enable/disable the instruction cache. - */ -void rtems_enable_inst_cache( void ); -void rtems_disable_inst_cache( void ); -#endif - - -#ifdef __cplusplus -} -#endif - -#endif -/* end of include file */ diff --git a/c/src/exec/rtems/src/Makefile.am b/c/src/exec/rtems/src/Makefile.am index f2b13c2aa9..f597292be1 100644 --- a/c/src/exec/rtems/src/Makefile.am +++ b/c/src/exec/rtems/src/Makefile.am @@ -50,7 +50,7 @@ PARTITION_C_FILES = part.c partcreate.c partdelete.c partgetbuffer.c \ DPMEM_C_FILES = dpmem.c dpmemcreate.c dpmemdelete.c dpmemexternal2internal.c \ dpmemident.c dpmeminternal2external.c -STD_C_FILES = attr.c cache.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \ +STD_C_FILES = attr.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \ $(CLOCK_C_FILES) $(TIMER_C_FILES) $(SEMAPHORE_C_FILES) \ $(MESSAGE_QUEUE_C_FILES) $(EVENT_C_FILES) $(SIGNAL_C_FILES) \ $(PARTITION_C_FILES) $(REGION_C_FILES) $(DPMEM_C_FILES) diff --git a/c/src/exec/rtems/src/cache.c b/c/src/exec/rtems/src/cache.c deleted file mode 100644 index 82d6410a92..0000000000 --- a/c/src/exec/rtems/src/cache.c +++ /dev/null @@ -1,252 +0,0 @@ -/* cache.c - * - * Cache Manager - * - * COPYRIGHT (c) 1989-1999. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.OARcorp.com/rtems/license.html. - * - * - * The functions in this file define the API to the RTEMS Cache Manager and - * are divided into data cache and instruction cache functions. Data cache - * functions are only declared if a data cache is supported. Instruction - * cache functions are only declared if an instruction cache is supported. - * Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is - * defined, where x E {DATA, INST}. These definitions are found in the CPU - * dependent source files in the supercore, often - * - * rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h - * - * The functions below are implemented with CPU dependent inline routines - * also found in the above file. In the event that a CPU does not support a - * specific function, the CPU dependent routine does nothing (but does exist). - * - * At this point, the Cache Manager makes no considerations, and provides no - * support for BSP specific issues such as a secondary cache. In such a system, - * the CPU dependent routines would have to be modified, or a BSP layer added - * to this Manager. - */ - -#include <rtems/system.h> -#include <sys/types.h> -#include <rtems/rtems/cache.h> - - -/* - * THESE FUNCTIONS ONLY EXIST IF WE HAVE A DATA CACHE - */ -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - -/* - * This function is called to flush the data cache by performing cache - * copybacks. It must determine how many cache lines need to be copied - * back and then perform the copybacks. - */ -void -rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) -{ - const void * final_address; - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be pushed. Increment d_addr and push - * the resulting line until final_address is passed. - */ - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1)); - while( d_addr <= final_address ) { - _CPU_flush_1_data_cache_line( d_addr ); - d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT); - } -} - - -/* - * This function is responsible for performing a data cache invalidate. - * It must determine how many cache lines need to be invalidated and then - * perform the invalidations. - */ -void -rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) -{ - const void * final_address; - /* - * Set d_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be invalidated. Increment d_addr and - * invalidate the resulting line until final_address is passed. - */ - final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1)); - while( final_address > d_addr ) { - _CPU_invalidate_1_data_cache_line( d_addr ); - d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT); - } -} - - -/* - * This function is responsible for performing a data cache flush. - * It flushes the entire cache. - */ -void -rtems_flush_entire_data_cache( void ) -{ - /* - * Call the CPU-specific routine - */ - _CPU_flush_entire_data_cache(); - -} - - -/* - * This function is responsible for performing a data cache - * invalidate. It invalidates the entire cache. - */ -void -rtems_invalidate_entire_data_cache( void ) -{ - /* - * Call the CPU-specific routine - */ - _CPU_invalidate_entire_data_cache(); -} - - -/* - * This function returns the data cache granularity. - */ -int -rtems_get_data_cache_line_size( void ) -{ - return _CPU_DATA_CACHE_ALIGNMENT; -} - - -/* - * This function freezes the data cache; cache lines - * are not replaced. - */ -void -rtems_freeze_data_cache( void ) -{ - _CPU_freeze_data_cache(); -} - - -/* - * This function unfreezes the instruction cache. - */ -void rtems_unfreeze_data_cache( void ) -{ - _CPU_unfreeze_data_cache(); -} - - -/* Turn on the data cache. */ -void -rtems_enable_data_cache( void ) -{ - _CPU_enable_data_cache(); -} - - -/* Turn off the data cache. */ -void -rtems_disable_data_cache( void ) -{ - _CPU_disable_data_cache(); -} -#endif - - - -/* - * THESE FUNCTIONS ONLY EXIST IF WE HAVE AN INSTRUCTION CACHE - */ -#if defined(_CPU_INST_CACHE_ALIGNMENT) - -/* - * This function is responsible for performing an instruction cache - * invalidate. It must determine how many cache lines need to be invalidated - * and then perform the invalidations. - */ -void -rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes ) -{ - const void * final_address; - /* - * Set i_addr to the beginning of the cache line; final_address indicates - * the last address_t which needs to be invalidated. Increment i_addr and - * invalidate the resulting line until final_address is passed. - */ - final_address = (void *)((size_t)i_addr + n_bytes - 1); - i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1)); - while( final_address > i_addr ) { - _CPU_invalidate_1_inst_cache_line( i_addr ); - i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT); - } -} - - -/* - * This function is responsible for performing an instruction cache - * invalidate. It invalidates the entire cache. - */ -void -rtems_invalidate_entire_inst_cache( void ) -{ - /* - * Call the CPU-specific routine - */ - _CPU_invalidate_entire_inst_cache(); -} - - -/* - * This function returns the instruction cache granularity. - */ -int -rtems_get_inst_cache_line_size( void ) -{ - return _CPU_INST_CACHE_ALIGNMENT; -} - - -/* - * This function freezes the instruction cache; cache lines - * are not replaced. - */ -void -rtems_freeze_inst_cache( void ) -{ - _CPU_freeze_inst_cache(); -} - - -/* - * This function unfreezes the instruction cache. - */ -void rtems_unfreeze_inst_cache( void ) -{ - _CPU_unfreeze_inst_cache(); -} - - -/* Turn on the instruction cache. */ -void -rtems_enable_inst_cache( void ) -{ - _CPU_enable_inst_cache(); -} - - -/* Turn off the instruction cache. */ -void -rtems_disable_inst_cache( void ) -{ - _CPU_disable_inst_cache(); -} -#endif diff --git a/c/src/exec/score/cpu/i386/rtems/score/i386.h b/c/src/exec/score/cpu/i386/rtems/score/i386.h index ca1af66fff..bc486da473 100644 --- a/c/src/exec/score/cpu/i386/rtems/score/i386.h +++ b/c/src/exec/score/cpu/i386/rtems/score/i386.h @@ -185,101 +185,6 @@ static inline void i386_set_cr3(unsigned int segment) asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) ); } -/* - * Disable the entire cache - */ -void _CPU_disable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 1; - regCr0.cr0.no_write_through = 1; - i386_set_cr0( regCr0.i ); - rtems_flush_entire_data_cache(); -} - -/* - * Enable the entire cache - */ -static inline void _CPU_enable_cache() { - cr0 regCr0; - - regCr0.i = i386_get_cr0(); - regCr0.cr0.page_level_cache_disable = 0; - regCr0.cr0.no_write_through = 0; - i386_set_cr0( regCr0.i ); - /*rtems_flush_entire_data_cache();*/ -} - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - * - * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for - * each CPU. The routines below should be implemented per CPU, - * to accomodate the capabilities of each. - */ - -/* FIXME: I don't belong here. */ -#define I386_CACHE_ALIGNMENT 16 - -#if defined(I386_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT - -static inline void _CPU_flush_1_data_cache_line (const void * d_addr) {} -static inline void _CPU_invalidate_1_data_cache_line (const void * d_addr) {} -static inline void _CPU_freeze_data_cache (void) {} -static inline void _CPU_unfreeze_data_cache (void) {} -static inline void _CPU_invalidate_1_inst_cache_line const void * d_addr() {} -static inline void _CPU_freeze_inst_cache (void) {} -static inline void _CPU_unfreeze_inst_cache (void) {} - -static inline void _CPU_flush_entire_data_cache ( - const void * d_addr ) -{ - asm ("wbinvd"); -} -static inline void _CPU_invalidate_entire_data_cache ( - const void * d_addr ) -{ - asm ("invd"); -} - -static inline void _CPU_enable_data_cache ( - void ) -{ - _CPU_enable_cache(); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - _CPU_disable_cache(); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - const void * i_addr ) -{ - asm ("invd"); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - _CPU_enable_cache(); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - _CPU_disable_cache(); -} -#endif - - /* routines */ /* diff --git a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h b/c/src/exec/score/cpu/m68k/rtems/score/m68k.h index c38a9a13ed..bd8ec20475 100644 --- a/c/src/exec/score/cpu/m68k/rtems/score/m68k.h +++ b/c/src/exec/score/cpu/m68k/rtems/score/m68k.h @@ -373,217 +373,6 @@ static inline void * _CPU_virtual_to_physical ( } -/* - * Since the cacr is common to all mc680x0, provide macros - * for masking values in that register. - */ - -/* - * Used to clear bits in the cacr. - */ -#define _CPU_CACR_AND(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ - andl %2, %0; /* and with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * Used to set bits in the cacr. - */ -#define _CPU_CACR_OR(mask) \ - { \ - register unsigned long _value = mask; \ - register unsigned long _ctl = 0; \ - asm volatile ( "movec %%cacr, %0; /* read the cacr */ \ - orl %2, %0; /* or with _val */ \ - movec %1, %%cacr" /* write the cacr */ \ - : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" ); \ - } - - -/* - * CACHE MANAGER: The following functions are CPU-specific. - * They provide the basic implementation for the rtems_* cache - * management routines. If a given function has no meaning for the CPU, - * it does nothing by default. - */ -#if ( defined(__mc68020__) || defined(__mc68030__) ) -#define M68K_INST_CACHE_ALIGNMENT 16 - -#if defined(__mc68030__) -#define M68K_DATA_CACHE_ALIGNMENT 16 - -/* Only the mc68030 has a data cache; it is writethrough only. */ - -static inline void _CPU_flush_1_data_cache_line ( const void * d_addr ) {} -static inline void _CPU_flush_entire_data_cache ( const void * d_addr ) {} - -static inline void _CPU_invalidate_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR(0x00000400); -} - -static inline void _CPU_invalidate_entire_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000800 ); -} - -static inline void _CPU_freeze_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000200 ); -} - -static inline void _CPU_unfreeze_data_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFFFDFF ); -} - -static inline void _CPU_enable_data_cache ( void ) -{ - _CPU_CACR_OR( 0x00000100 ); -} -static inline void _CPU_disable_data_cache ( void ) -{ - _CPU_CACR_AND( 0xFFFFFEFF ); -} -#endif - - -/* Both the 68020 and 68030 have instruction caches */ - -static inline void _CPU_invalidate_1_inst_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "movec %0, %%caar" :: "a" (p_address) ); /* write caar */ - _CPU_CACR_OR( 0x00000004 ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000008 ); -} - -static inline void _CPU_freeze_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00000002); -} - -static inline void _CPU_unfreeze_inst_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFFFFFD ); -} - -static inline void _CPU_enable_inst_cache ( void ) -{ - _CPU_CACR_OR( 0x00000001 ); -} - -static inline void _CPU_disable_inst_cache ( void ) -{ - _CPU_CACR_AND( 0xFFFFFFFE ); -} - - -#elif ( defined(__mc68040__) || defined (__mc68060__) ) - -#define M68K_INST_CACHE_ALIGNMENT 16 -#define M68K_DATA_CACHE_ALIGNMENT 16 - -/* Cannot be frozen */ -static inline void _CPU_freeze_data_cache ( void ) {} -static inline void _CPU_unfreeze_data_cache ( void ) {} -static inline void _CPU_freeze_inst_cache ( void ) {} -static inline void _CPU_unfreeze_inst_cache ( void ) {} - -static inline void _CPU_flush_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_invalidate_1_data_cache_line ( - const void * d_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); - asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_flush_entire_data_cache ( - void ) -{ - asm volatile ( "cpusha %%dc" :: ); -} - -static inline void _CPU_invalidate_entire_data_cache ( - void ) -{ - asm volatile ( "cinva %%dc" :: ); -} - -static inline void _CPU_enable_data_cache ( - void ) -{ - _CPU_CACR_OR( 0x80000000 ); -} - -static inline void _CPU_disable_data_cache ( - void ) -{ - _CPU_CACR_AND( 0x7FFFFFFF ); -} - -static inline void _CPU_invalidate_1_inst_cache_line ( - const void * i_addr ) -{ - void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); - asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); -} - -static inline void _CPU_invalidate_entire_inst_cache ( - void ) -{ - asm volatile ( "cinva %%ic" :: ); -} - -static inline void _CPU_enable_inst_cache ( - void ) -{ - _CPU_CACR_OR( 0x00008000 ); -} - -static inline void _CPU_disable_inst_cache ( - void ) -{ - _CPU_CACR_AND( 0xFFFF7FFF ); -} -#endif - - -#if defined(M68K_DATA_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT -#endif - -#if defined(M68K_INST_CACHE_ALIGNMENT) -#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT -#endif - - #endif /* !ASM */ #ifdef __cplusplus |