changes remerged after lost in disk crash -- recovered from snapshot, partially recovered working tree, etc

14 files changed, 160 insertions, 105 deletions

diff --git a/c/src/exec/score/cpu/powerpc/README b/c/src/exec/score/cpu/powerpc/README
index 2c0fb9a707..fc0dd9c7d7 100644
--- a/c/src/exec/score/cpu/powerpc/README
+++ b/c/src/exec/score/cpu/powerpc/README
@@ -8,21 +8,9 @@ There are various issues regarding this port:
 
 1) Legal
 
-This port is written by Andrew Bray <andy@i-cubed.demon.co.uk>, and
+This port is written by Andrew Bray <andy@i-cubed.co.uk>, and
 is copyright 1995 i-cubed ltd.
 
-Due to the current lack of a formal release note, this is a limited
-release to OAR, and other specific parties designated by OAR who
-are involved in porting RTEMS to the PowerPC architecture.
-
-This set of release files SHOULD (IMHO) include a cpu specific
-alignment exception handler.  Ours is derived from IBM sample
-code.  I am seeking a release from IBM for this file.  In the
-mean time this file is excluded (but still included in the Makefile
-as a place-holder).
-
-NOTE: IBM released the alignment exception handler under generous enough
-      terms where it could be included in this distribution.
 
 
 2) CPU support.
@@ -74,10 +62,10 @@ caveat:  we used an ELF assembler and linker.  So some attention may be required
 on the assembler files to get them through a traditional (XCOFF) PowerOpen
 assembler.
 
-This port contains support for the other ABIs, but this may prove to be incoplete
+This port contains support for the other ABIs, but this may prove to be incomplete
 as it is untested.
 
 In the long term, the RTEMS PowerPC port should move to the EABI as its primary
 or only port.  This should wait on a true EABI version of GCC.
 
-Andrew Bray 18/8/1995
+Andrew Bray 4/December/1995
diff --git a/c/src/exec/score/cpu/powerpc/cpu.c b/c/src/exec/score/cpu/powerpc/cpu.c
index e0431f868b..77aacc2ed7 100644
--- a/c/src/exec/score/cpu/powerpc/cpu.c
+++ b/c/src/exec/score/cpu/powerpc/cpu.c
@@ -1,7 +1,7 @@
 /*
  *  PowerPC CPU Dependent Source
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -33,14 +33,11 @@
 #include <rtems/score/isr.h>
 #include <rtems/score/context.h>
 #include <rtems/score/thread.h>
-#include <rtems/score/wkspace.h>
 
 /*
  *  These are for testing purposes.
  */
-/*
-#define Testing
-*/
+#undef Testing
 
 #ifdef Testing
 static unsigned32 msr;
@@ -100,10 +97,10 @@ void _CPU_Initialize(
   _CPU_IRQ_info.Signal = &_ISR_Signals_to_thread_executing;
 
   i = (int)&_CPU_IRQ_info;
-  asm volatile("mtsprg3 %0" : "=r" (i) : "0" (i));
+  asm volatile("mtspr 0x113, %0" : "=r" (i) : "0" (i)); /* SPRG 3 */
 
   i = PPC_MSR_INITIAL & ~PPC_MSR_DISABLE_MASK;
-  asm volatile("mtsprg2 %0" : "=r" (i) : "0" (i));
+  asm volatile("mtspr 0x112, %0" : "=r" (i) : "0" (i)); /* SPRG 2 */
 
 #ifdef Testing
   {
@@ -112,11 +109,11 @@ void _CPU_Initialize(
     asm volatile ("mfmsr %0" : "=r" (tmp));
     msr = tmp;
 #ifdef ppc403
-    asm volatile ("mfevpr %0" : "=r" (tmp));
+    asm volatile ("mfspr %0, 0x3d6" : "=r" (tmp)); /* EVPR */
     evpr = tmp;
-    asm volatile ("mfexier %0" : "=r" (tmp));
+    asm volatile ("mfdcr %0, 0x42" : "=r" (tmp)); /* EXIER */
     exier = tmp;
-    asm volatile ("mtevpr %0" :: "r" (0));
+    asm volatile ("mtspr 0x3d6, %0" :: "r" (0)); /* EVPR */
 #endif
   }
 #endif
@@ -130,6 +127,40 @@ void _CPU_Initialize(
   _CPU_Table = *cpu_table;
 }
 
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ *
+ *  COMMENTS FROM Andrew Bray <andy@i-cubed.co.uk>:
+ *
+ *  The PowerPC puts its interrupt enable status in the MSR register
+ *  which also contains things like endianness control.  To be more
+ *  awkward, the layout varies from processor to processor.  This
+ *  is why I adopted a table approach in my interrupt handling.
+ *  Thus the inverse process is slow, because it requires a table
+ *  search.
+ *
+ *  This could fail, and return 4 (an invalid level) if the MSR has been
+ *  set to a value not in the table.  This is also quite an expensive
+ *  operation - I do hope its not too common.
+ *
+ */
+ 
+unsigned32 _CPU_ISR_Get_level( void )
+{
+  unsigned32 level, msr;
+ 
+  asm volatile("mfmsr %0" : "=r" ((msr)));
+ 
+  msr &= PPC_MSR_DISABLE_MASK;
+ 
+  for (level = 0; level < 4; level++)
+    if ((_CPU_msrs[level] & PPC_MSR_DISABLE_MASK) == msr)
+      break;
+ 
+  return level;
+}
+
 /*  _CPU_ISR_install_vector
  *
  *  This kernel routine installs the RTEMS handler for the
@@ -163,11 +194,10 @@ void _CPU_ISR_install_vector(
     *  be used by the _ISR_Handler so the user gets control.
     */
 
-    _ISR_Vector_table[ vector ] = 
-       (new_handler) ? (ISR_Handler_entry) new_handler :
-       ((_CPU_Table.spurious_handler) ? 
-          (ISR_Handler_entry) _CPU_Table.spurious_handler :
-          (ISR_Handler_entry) ppc_spurious);
+    _ISR_Vector_table[ vector ] = new_handler ? (ISR_Handler_entry)new_handler :
+       _CPU_Table.spurious_handler ? 
+          (ISR_Handler_entry)_CPU_Table.spurious_handler :
+          (ISR_Handler_entry)ppc_spurious;
 }
 
 /*PAGE
@@ -196,19 +226,19 @@ static void ppc_spurious(int v, CPU_Interrupt_frame *i)
 	{
 	    register int r = 0;
 
-	    asm volatile("mtexier %0" : "=r" ((r)) : "0" ((r)));
+	    asm volatile("mtdcr 0x42, %0" : "=r" ((r)) : "0" ((r))); /* EXIER */
 	}
     else if (v == PPC_IRQ_PIT)
 	{
 	    register int r = 0x08000000;
 
-	    asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r)));
+	    asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */
 	}
     else if (v == PPC_IRQ_FIT)
 	{
 	    register int r = 0x04000000;
 
-	    asm volatile("mttsr %0" : "=r" ((r)) : "0" ((r)));
+	    asm volatile("mtspr 0x3d8, %0" : "=r" ((r)) : "0" ((r))); /* TSR */
 	}
 #endif
 }
@@ -222,9 +252,9 @@ void _CPU_Fatal_error(unsigned32 _error)
   asm volatile ("mtmsr %0" :: "r" (tmp));
 #ifdef ppc403
   tmp = evpr;
-  asm volatile ("mtevpr %0" :: "r" (tmp));
+  asm volatile ("mtspr 0x3d6, %0" :: "r" (tmp)); /* EVPR */
   tmp = exier;
-  asm volatile ("mtexier %0" :: "r" (tmp));
+  asm volatile ("mtdcr 0x42, %0" :: "r" (tmp)); /* EXIER */
 #endif
 #endif
   asm volatile ("mr 3, %0" : : "r" ((_error)));
diff --git a/c/src/exec/score/cpu/powerpc/cpu.h b/c/src/exec/score/cpu/powerpc/cpu.h
index 8bbc341268..fc2868cccf 100644
--- a/c/src/exec/score/cpu/powerpc/cpu.h
+++ b/c/src/exec/score/cpu/powerpc/cpu.h
@@ -3,7 +3,7 @@
  *  This include file contains information pertaining to the PowerPC
  *  processor.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -495,6 +495,10 @@ EXTERN void               *_CPU_Interrupt_stack_high;
  */
 
 EXTERN struct {
+  unsigned32 *Nest_level;
+  unsigned32 *Disable_level;
+  void *Vector_table;
+  void *Stack;
 #if (PPC_ABI == PPC_ABI_POWEROPEN)
   unsigned32 Dispatch_r2;
 #else
@@ -503,10 +507,6 @@ EXTERN struct {
   unsigned32 Default_r13;
 #endif
 #endif
-  unsigned32 *Nest_level;
-  unsigned32 *Disable_level;
-  void *Vector_table;
-  void *Stack;
   boolean *Switch_necessary;
   boolean *Signal;
 } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
@@ -541,7 +541,7 @@ EXTERN struct {
  *  by RTEMS.
  */
 
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (PPC_INTERRUPT_MAX)
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS  (PPC_INTERRUPT_MAX)
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /*
@@ -570,7 +570,7 @@ EXTERN struct {
  *         be greater or equal to than CPU_ALIGNMENT.
  */
 
-#define CPU_HEAP_ALIGNMENT         (PPC_CACHE_ALIGNMENT)
+#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
 
 /*
  *  This number corresponds to the byte alignment requirement for memory
@@ -584,7 +584,7 @@ EXTERN struct {
  *         be greater or equal to than CPU_ALIGNMENT.
  */
 
-#define CPU_PARTITION_ALIGNMENT    (PPC_CACHE_ALIGNMENT)
+#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
 
 /*
  *  This number corresponds to the byte alignment requirement for the
@@ -604,6 +604,8 @@ EXTERN struct {
  *  level is returned in _level.
  */
 
+#define loc_string(a,b)	a " (" #b ")\n"
+
 #define _CPU_ISR_Disable( _isr_cookie ) \
   { \
     asm volatile ( \
@@ -661,6 +663,8 @@ EXTERN struct {
 	); \
   }
 
+unsigned32 _CPU_ISR_Get_level( void );
+
 /* end of ISR handler macros */
 
 /* Context handler macros */
@@ -817,11 +821,11 @@ EXTERN struct {
  *
  *  RTEMS guarantees that (1) will never happen so it is not a concern.
  *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
- *  _CPU_Priority_bits_index().  These three form a set of routines
+ *  _CPU_Priority_Bits_index().  These three form a set of routines
  *  which must logically operate together.  Bits in the _value are
  *  set and cleared based on masks built by _CPU_Priority_mask().
  *  The basic major and minor values calculated by _Priority_Major()
- *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
+ *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
  *  to properly range between the values returned by the "find first bit"
  *  instruction.  This makes it possible for _Priority_Get_highest() to
  *  calculate the major and directly index into the minor table.
@@ -856,9 +860,6 @@ EXTERN struct {
  *      bit set
  */
 
-#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
-#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
-
 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
   { \
     asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
diff --git a/c/src/exec/score/cpu/powerpc/cpu_asm.s b/c/src/exec/score/cpu/powerpc/cpu_asm.s
index c9ab7a13f5..cf95e25a5c 100644
--- a/c/src/exec/score/cpu/powerpc/cpu_asm.s
+++ b/c/src/exec/score/cpu/powerpc/cpu_asm.s
@@ -1,9 +1,10 @@
-/*  cpu_asm.s	1.0 - 95/08/08
+
+/*  cpu_asm.s	1.1 - 95/12/04
  *
  *  This file contains the assembly code for the PowerPC implementation
  *  of RTEMS.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -671,9 +672,6 @@ PROC (_CPU_Context_restore):
 	blr
 
 /*  Individual interrupt prologues look like this:
- *	mtsprg{0,1} r0
- *	mfsprg2 r0
- *	mtmsr   r0
  * #if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
  * #if (PPC_HAS_FPU)
  *	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
@@ -683,7 +681,6 @@ PROC (_CPU_Context_restore):
  * #else
  *	stwu	r1, -(IP_END)(r1)
  * #endif
- *	mfsprg{0,1} r0
  *	stw	r0, IP_0(r1)
  *
  *	li      r0, vectornum
@@ -700,8 +697,12 @@ PROC (_CPU_Context_restore):
 	PUBLIC_PROC (_ISR_Handler)
 PROC (_ISR_Handler):
 #define LABEL(x)	x
-#define MTSAVE(x)	mtsprg0	x
-#define MFSAVE(x)	mfsprg0	x
+#define MTSAVE(x)	mtspr	sprg0, x
+#define MFSAVE(x)	mfspr	x, sprg0
+#define MTPC(x)		mtspr	srr0, x
+#define MFPC(x)		mfspr	x, srr0
+#define MTMSR(x)	mtspr	srr1, x
+#define MFMSR(x)	mfspr	x, srr1
 	#include	"irq_stub.s"
 	rfi
 
@@ -718,9 +719,17 @@ PROC (_ISR_HandlerC):
 #undef	LABEL
 #undef	MTSAVE
 #undef	MFSAVE
+#undef	MTPC
+#undef	MFPC
+#undef	MTMSR
+#undef	MFMSR
 #define LABEL(x)	x##_C
-#define MTSAVE(x)	mtsprg1	x
-#define MFSAVE(x)	mfsprg1	x
+#define MTSAVE(x)	mtspr	sprg1, x
+#define MFSAVE(x)	mfspr	x, sprg1
+#define MTPC(x)		mtspr	srr2, x
+#define MFPC(x)		mfspr	x, srr2
+#define MTMSR(x)	mtspr	srr3, x
+#define MFMSR(x)	mfspr	x, srr3
 	#include	"irq_stub.s"
 	rfci
 #endif
diff --git a/c/src/exec/score/cpu/powerpc/irq_stub.s b/c/src/exec/score/cpu/powerpc/irq_stub.s
index 1ed443d479..42a63e991f 100644
--- a/c/src/exec/score/cpu/powerpc/irq_stub.s
+++ b/c/src/exec/score/cpu/powerpc/irq_stub.s
@@ -1,9 +1,9 @@
-/*  irq_stub.s	1.0 - 95/08/08
+/*  irq_stub.s	1.1 - 95/12/04
  *
  *  This file contains the interrupt handler assembly code for the PowerPC
  *  implementation of RTEMS.  It is #included from cpu_asm.s.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -45,10 +45,10 @@
 	mfctr	r6
 	mfxer	r7
 	mflr	r8
-	mfsrr0	r9
-	mfsrr1	r10
+	MFPC	(r9)
+	MFMSR	(r10)
 	/* Establish addressing */
-	mfsprg3	r11
+	mfspr	r11, sprg3
 	dcbt	r0, r11
 	stw	r5, IP_CR(r1)
 	stw	r6, IP_CTR(r1)
@@ -72,6 +72,9 @@
    *  #endif
    */
 	/* Switch stacks, here we must prevent ALL interrupts */
+	mfmsr	r5
+	mfspr   r6, sprg2
+	mtmsr	r6
 	cmpwi	r30, 0
 	lwz	r29, Disable_level(r11)
 	subf	r31,r1,r31
@@ -93,6 +96,7 @@ LABEL (nested):
    */
 	addi	r31,r31,1
 	stw	r31, 0(r29)
+	mtmsr	r5
   /*
    *  (*_ISR_Vector_table[ vector ])( vector );
    */
@@ -120,9 +124,11 @@ LABEL (nested):
 	or	r6,r6,r6
 
 	/*	We must re-disable the interrupts */
-	mfsprg3	r11
-	mfsprg2 r0
+	mfspr	r11, sprg3
+	mfspr	r0, sprg2
 	mtmsr   r0
+	lwz	r30, 0(r28)
+	lwz	r31, 0(r29)
 
   /*
    *  if (--Thread_Dispatch_disable,--_ISR_Nest_level)
@@ -134,6 +140,7 @@ LABEL (nested):
 	stw	r30, 0(r28)
 	stw	r31, 0(r29)
 	bne	LABEL (easy_exit)
+	cmpwi	r31, 0
 
 	lwz	r30, Switch_necessary(r11)
 
@@ -143,6 +150,7 @@ LABEL (nested):
    *  #endif
    */
 	lwz	r1,0(r1)
+	bne	LABEL (easy_exit)
 	lwz	r30, 0(r30)
 	lwz	r31, Signal(r11)
 	
@@ -152,6 +160,7 @@ LABEL (nested):
    */
 	cmpwi	r30, 0
 	lwz	r28, 0(r31)
+	li	r6,0
 	bne	LABEL (switch)
   /*  
    *  if ( !_ISR_Signals_to_thread_executing )
@@ -159,28 +168,30 @@ LABEL (nested):
    *  _ISR_Signals_to_thread_executing = 0;
    */
 	cmpwi	r28, 0
-	li	r6,0
 	beq	LABEL (easy_exit)
-	stw	r6, 0(r31)
 
   /*
    * switch:
    *  call _Thread_Dispatch() or prepare to return to _ISR_Dispatch
    */
 LABEL (switch):
+	stw	r6, 0(r31)
+	/* Re-enable interrupts */
+	lwz	r0, IP_MSR(r1)
 #if (PPC_ABI == PPC_ABI_POWEROPEN)
 	lwz	r2, Dispatch_r2(r11)
 #else
 	/* R2 and R13 still hold their values from the last call */
 #endif
-	bl	PROC (_Thread_Dispatch)
+	mtmsr	r0
+	bl	SYM (_Thread_Dispatch)
 	/* NOP marker for debuggers */
 	or	r6,r6,r6
   /*
    *  prepare to get out of interrupt
    */
 	/* Re-disable IRQs */
-	mfsprg2 r0
+	mfspr   r0, sprg2
 	mtmsr   r0
   /*
    *  easy_exit:
@@ -198,8 +209,8 @@ LABEL (easy_exit):
 	mtctr	r6
 	mtxer	r7
 	mtlr	r8
-	mtsrr0	r9
-	mtsrr1	r10
+	MTPC	(r9)
+	MTMSR	(r10)
 	lwz	r0, IP_0(r1)
 	lwz	r2, IP_2(r1)
 	lwz	r3, IP_3(r1)
diff --git a/c/src/exec/score/cpu/powerpc/ppc.h b/c/src/exec/score/cpu/powerpc/ppc.h
index c2960a1910..c05760ed53 100644
--- a/c/src/exec/score/cpu/powerpc/ppc.h
+++ b/c/src/exec/score/cpu/powerpc/ppc.h
@@ -3,7 +3,7 @@
  *  This file contains definitions for the IBM/Motorola PowerPC
  *  family members.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
@@ -92,7 +92,7 @@ extern "C" {
 
 #define PPC_MSR_0		0x00029200
 #define PPC_MSR_1		0x00021200
-#define PPC_MSR_2		0x00001000
+#define PPC_MSR_2		0x00021000
 #define PPC_MSR_3		0x00000000
 
 #elif defined(ppc601)
diff --git a/c/src/exec/score/cpu/powerpc/ppctypes.h b/c/src/exec/score/cpu/powerpc/ppctypes.h
index f6f199cf23..4bbb436bf8 100644
--- a/c/src/exec/score/cpu/powerpc/ppctypes.h
+++ b/c/src/exec/score/cpu/powerpc/ppctypes.h
@@ -3,7 +3,7 @@
  *  This include file contains type definitions pertaining to the PowerPC
  *  processor family.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
diff --git a/c/src/exec/score/cpu/powerpc/rtems.s b/c/src/exec/score/cpu/powerpc/rtems.s
index 25e955d4ea..ae6022d24b 100644
--- a/c/src/exec/score/cpu/powerpc/rtems.s
+++ b/c/src/exec/score/cpu/powerpc/rtems.s
@@ -3,7 +3,7 @@
  *  This file contains the single entry point code for
  *  the PowerPC implementation of RTEMS.
  *
- *  Author:	Andrew Bray <andy@i-cubed.demon.co.uk>
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
  *
diff --git a/c/src/exec/score/macros/rtems/score/tod.inl b/c/src/exec/score/macros/rtems/score/tod.inl
index 9360a588b1..ecab4e6eae 100644
--- a/c/src/exec/score/macros/rtems/score/tod.inl
+++ b/c/src/exec/score/macros/rtems/score/tod.inl
@@ -51,9 +51,8 @@
  *
  */
 
-#define _TOD_Activate( ticks ) \
-   _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, \
-      (ticks), WATCHDOG_ACTIVATE_NOW )
+#define _TOD_Activate( _ticks ) \
+   _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, (_ticks) )
 
 #endif
 /* end of include file */
diff --git a/c/src/exec/score/macros/rtems/score/tqdata.inl b/c/src/exec/score/macros/rtems/score/tqdata.inl
index c0d7ee8e5e..1df3cd5270 100644
--- a/c/src/exec/score/macros/rtems/score/tqdata.inl
+++ b/c/src/exec/score/macros/rtems/score/tqdata.inl
@@ -44,5 +44,17 @@
 #define _Thread_queue_Get_number_waiting( _the_thread_queue ) \
   ( (_the_thread_queue)->count )
 
+/*PAGE
+ *
+ *  _Thread_queue_Enter_critical_section
+ *
+ */
+ 
+#define _Thread_queue_Enter_critical_section( _the_thread_queue ) \
+  do { \
+    (_the_thread_queue)->sync = TRUE; \
+    (_the_thread_queue)->sync_state = THREAD_QUEUE_NOTHING_HAPPENED; \
+  } while ( 0 )
+
 #endif
 /* end of include file */
diff --git a/c/src/exec/score/macros/rtems/score/watchdog.inl b/c/src/exec/score/macros/rtems/score/watchdog.inl
index a8a061b144..d24224f93d 100644
--- a/c/src/exec/score/macros/rtems/score/watchdog.inl
+++ b/c/src/exec/score/macros/rtems/score/watchdog.inl
@@ -84,12 +84,11 @@
  *
  */
 
-#define _Watchdog_Insert_ticks( _the_watchdog, _units, _insert_mode ) \
-  { \
+#define _Watchdog_Insert_ticks( _the_watchdog, _units ) \
+  do { \
     (_the_watchdog)->initial = (_units); \
-    _Watchdog_Insert( &_Watchdog_Ticks_chain, \
-                        (_the_watchdog), (_insert_mode) ); \
-  }
+    _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \
+  } while ( 0 )
 
 /*PAGE
  *
@@ -97,12 +96,11 @@
  *
  */
 
-#define _Watchdog_Insert_seconds( _the_watchdog, _units, _insert_mode ) \
-  { \
+#define _Watchdog_Insert_seconds( _the_watchdog, _units ) \
+  do { \
     (_the_watchdog)->initial = (_units); \
-    _Watchdog_Insert( &_Watchdog_Seconds_chain, \
-                        (_the_watchdog), (_insert_mode) ); \
-  }
+    _Watchdog_Insert( &_Watchdog_Seconds_chain, (_the_watchdog) ); \
+  } while ( 0 )
 
 /*PAGE
  *
@@ -131,8 +129,7 @@
 #define _Watchdog_Reset( _the_watchdog ) \
    { \
      (void) _Watchdog_Remove( (_the_watchdog) ); \
-     _Watchdog_Insert( &_Watchdog_Ticks_chain, \
-                         (_the_watchdog), WATCHDOG_ACTIVATE_NOW ); \
+     _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \
    }
 
 /*PAGE
diff --git a/c/src/exec/score/macros/tod.inl b/c/src/exec/score/macros/tod.inl
index 9360a588b1..ecab4e6eae 100644
--- a/c/src/exec/score/macros/tod.inl
+++ b/c/src/exec/score/macros/tod.inl
@@ -51,9 +51,8 @@
  *
  */
 
-#define _TOD_Activate( ticks ) \
-   _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, \
-      (ticks), WATCHDOG_ACTIVATE_NOW )
+#define _TOD_Activate( _ticks ) \
+   _Watchdog_Insert_ticks( &_TOD_Seconds_watchdog, (_ticks) )
 
 #endif
 /* end of include file */
diff --git a/c/src/exec/score/macros/tqdata.inl b/c/src/exec/score/macros/tqdata.inl
index c0d7ee8e5e..1df3cd5270 100644
--- a/c/src/exec/score/macros/tqdata.inl
+++ b/c/src/exec/score/macros/tqdata.inl
@@ -44,5 +44,17 @@
 #define _Thread_queue_Get_number_waiting( _the_thread_queue ) \
   ( (_the_thread_queue)->count )
 
+/*PAGE
+ *
+ *  _Thread_queue_Enter_critical_section
+ *
+ */
+ 
+#define _Thread_queue_Enter_critical_section( _the_thread_queue ) \
+  do { \
+    (_the_thread_queue)->sync = TRUE; \
+    (_the_thread_queue)->sync_state = THREAD_QUEUE_NOTHING_HAPPENED; \
+  } while ( 0 )
+
 #endif
 /* end of include file */
diff --git a/c/src/exec/score/macros/watchdog.inl b/c/src/exec/score/macros/watchdog.inl
index a8a061b144..d24224f93d 100644
--- a/c/src/exec/score/macros/watchdog.inl
+++ b/c/src/exec/score/macros/watchdog.inl
@@ -84,12 +84,11 @@
  *
  */
 
-#define _Watchdog_Insert_ticks( _the_watchdog, _units, _insert_mode ) \
-  { \
+#define _Watchdog_Insert_ticks( _the_watchdog, _units ) \
+  do { \
     (_the_watchdog)->initial = (_units); \
-    _Watchdog_Insert( &_Watchdog_Ticks_chain, \
-                        (_the_watchdog), (_insert_mode) ); \
-  }
+    _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \
+  } while ( 0 )
 
 /*PAGE
  *
@@ -97,12 +96,11 @@
  *
  */
 
-#define _Watchdog_Insert_seconds( _the_watchdog, _units, _insert_mode ) \
-  { \
+#define _Watchdog_Insert_seconds( _the_watchdog, _units ) \
+  do { \
     (_the_watchdog)->initial = (_units); \
-    _Watchdog_Insert( &_Watchdog_Seconds_chain, \
-                        (_the_watchdog), (_insert_mode) ); \
-  }
+    _Watchdog_Insert( &_Watchdog_Seconds_chain, (_the_watchdog) ); \
+  } while ( 0 )
 
 /*PAGE
  *
@@ -131,8 +129,7 @@
 #define _Watchdog_Reset( _the_watchdog ) \
    { \
      (void) _Watchdog_Remove( (_the_watchdog) ); \
-     _Watchdog_Insert( &_Watchdog_Ticks_chain, \
-                         (_the_watchdog), WATCHDOG_ACTIVATE_NOW ); \
+     _Watchdog_Insert( &_Watchdog_Ticks_chain, (_the_watchdog) ); \
    }
 
 /*PAGE