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authorcvs2git <rtems-devel@rtems.org>1996-01-24 20:38:48 +0000
committercvs2git <rtems-devel@rtems.org>1996-01-24 20:38:48 +0000
commitc5cea43cde3772505263e312ae97c5858d918d8f (patch)
tree4e594f67b38fc8cc2d200fc0c61d65a0a591ea52 /c/src/exec/score/cpu/sparc/cpu.h
parentM==military changed to M=multiprocessor (diff)
downloadrtems-3.5.1.tar.bz2
This commit was manufactured by cvs2svn to create tag 'rtems-3-5-1'.3.5.1
Sprout from master 1996-01-24 20:38:47 UTC Joel Sherrill <joel.sherrill@OARcorp.com> 'M==military changed to M=multiprocessor' Delete: c/build-tools/README c/build-tools/cklength.c c/build-tools/eolstrip.c c/build-tools/packhex.c c/build-tools/unhex.c c/src/exec/libcsupport/include/clockdrv.h c/src/exec/libcsupport/include/console.h c/src/exec/libcsupport/include/iosupp.h c/src/exec/libcsupport/include/ringbuf.h c/src/exec/libcsupport/include/rtems/assoc.h c/src/exec/libcsupport/include/rtems/error.h c/src/exec/libcsupport/include/rtems/libcsupport.h c/src/exec/libcsupport/include/rtems/libio.h c/src/exec/libcsupport/include/spurious.h c/src/exec/libcsupport/include/sys/utsname.h c/src/exec/libcsupport/include/timerdrv.h c/src/exec/libcsupport/include/vmeintr.h c/src/exec/libcsupport/src/README c/src/exec/libcsupport/src/__brk.c c/src/exec/libcsupport/src/__gettod.c c/src/exec/libcsupport/src/__times.c c/src/exec/libcsupport/src/assoc.c c/src/exec/libcsupport/src/error.c c/src/exec/libcsupport/src/hosterr.c c/src/exec/libcsupport/src/libio.c c/src/exec/libcsupport/src/malloc.c c/src/exec/libcsupport/src/newlibc.c c/src/exec/libcsupport/src/no_libc.c c/src/exec/libcsupport/src/unixlibc.c c/src/exec/libcsupport/src/utsname.c c/src/exec/posix/base/aio.h c/src/exec/posix/base/devctl.h c/src/exec/posix/base/intr.h c/src/exec/posix/base/limits.h c/src/exec/posix/base/mqueue.h c/src/exec/posix/base/pthread.h c/src/exec/posix/base/sched.h c/src/exec/posix/base/semaphore.h c/src/exec/posix/base/unistd.h c/src/exec/posix/headers/cancel.h c/src/exec/posix/headers/cond.h c/src/exec/posix/headers/condmp.h c/src/exec/posix/headers/intr.h c/src/exec/posix/headers/key.h c/src/exec/posix/headers/mqueue.h c/src/exec/posix/headers/mqueuemp.h c/src/exec/posix/headers/mutex.h c/src/exec/posix/headers/mutexmp.h c/src/exec/posix/headers/priority.h c/src/exec/posix/headers/pthread.h c/src/exec/posix/headers/pthreadmp.h c/src/exec/posix/headers/semaphore.h c/src/exec/posix/headers/semaphoremp.h c/src/exec/posix/headers/threadsup.h c/src/exec/posix/headers/time.h c/src/exec/posix/include/aio.h c/src/exec/posix/include/devctl.h c/src/exec/posix/include/intr.h c/src/exec/posix/include/limits.h c/src/exec/posix/include/mqueue.h c/src/exec/posix/include/pthread.h c/src/exec/posix/include/rtems/posix/cancel.h c/src/exec/posix/include/rtems/posix/cond.h c/src/exec/posix/include/rtems/posix/condmp.h c/src/exec/posix/include/rtems/posix/intr.h c/src/exec/posix/include/rtems/posix/key.h c/src/exec/posix/include/rtems/posix/mqueue.h c/src/exec/posix/include/rtems/posix/mqueuemp.h c/src/exec/posix/include/rtems/posix/mutex.h c/src/exec/posix/include/rtems/posix/mutexmp.h c/src/exec/posix/include/rtems/posix/priority.h c/src/exec/posix/include/rtems/posix/pthread.h c/src/exec/posix/include/rtems/posix/pthreadmp.h c/src/exec/posix/include/rtems/posix/semaphore.h c/src/exec/posix/include/rtems/posix/semaphoremp.h c/src/exec/posix/include/rtems/posix/threadsup.h c/src/exec/posix/include/rtems/posix/time.h c/src/exec/posix/include/sched.h c/src/exec/posix/include/semaphore.h c/src/exec/posix/include/sys/utsname.h c/src/exec/posix/include/unistd.h c/src/exec/posix/inline/cond.inl c/src/exec/posix/inline/intr.inl c/src/exec/posix/inline/key.inl c/src/exec/posix/inline/mqueue.inl c/src/exec/posix/inline/mutex.inl c/src/exec/posix/inline/priority.inl c/src/exec/posix/inline/pthread.inl c/src/exec/posix/inline/rtems/posix/cond.inl c/src/exec/posix/inline/rtems/posix/intr.inl c/src/exec/posix/inline/rtems/posix/key.inl c/src/exec/posix/inline/rtems/posix/mqueue.inl c/src/exec/posix/inline/rtems/posix/mutex.inl c/src/exec/posix/inline/rtems/posix/priority.inl c/src/exec/posix/inline/rtems/posix/pthread.inl c/src/exec/posix/inline/rtems/posix/semaphore.inl c/src/exec/posix/inline/semaphore.inl c/src/exec/posix/src/aio.c c/src/exec/posix/src/cancel.c c/src/exec/posix/src/cond.c c/src/exec/posix/src/devctl.c c/src/exec/posix/src/intr.c c/src/exec/posix/src/key.c c/src/exec/posix/src/mqueue.c c/src/exec/posix/src/mutex.c c/src/exec/posix/src/psignal.c c/src/exec/posix/src/pthread.c c/src/exec/posix/src/sched.c c/src/exec/posix/src/semaphore.c c/src/exec/posix/src/time.c c/src/exec/posix/src/types.c c/src/exec/posix/src/unistd.c c/src/exec/posix/src/utsname.c c/src/exec/posix/sys/utsname.h c/src/exec/rtems/include/rtems.h c/src/exec/rtems/include/rtems/rtems/asr.h c/src/exec/rtems/include/rtems/rtems/attr.h c/src/exec/rtems/include/rtems/rtems/clock.h c/src/exec/rtems/include/rtems/rtems/dpmem.h c/src/exec/rtems/include/rtems/rtems/event.h c/src/exec/rtems/include/rtems/rtems/eventmp.h c/src/exec/rtems/include/rtems/rtems/eventset.h c/src/exec/rtems/include/rtems/rtems/intr.h c/src/exec/rtems/include/rtems/rtems/message.h c/src/exec/rtems/include/rtems/rtems/modes.h c/src/exec/rtems/include/rtems/rtems/mp.h c/src/exec/rtems/include/rtems/rtems/msgmp.h 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c/src/exec/score/cpu/hppa1.1/cpu_asm.s c/src/exec/score/cpu/hppa1.1/hppa.h c/src/exec/score/cpu/hppa1.1/hppatypes.h c/src/exec/score/cpu/hppa1.1/rtems.s c/src/exec/score/cpu/powerpc/README c/src/exec/score/cpu/powerpc/TODO c/src/exec/score/cpu/powerpc/cpu.c c/src/exec/score/cpu/powerpc/cpu.h c/src/exec/score/cpu/powerpc/cpu_asm.s c/src/exec/score/cpu/powerpc/irq_stub.s c/src/exec/score/cpu/powerpc/ppc.h c/src/exec/score/cpu/powerpc/ppctypes.h c/src/exec/score/cpu/powerpc/rtems.s c/src/exec/score/cpu/sparc/README c/src/exec/score/cpu/sparc/asm.h c/src/exec/score/cpu/sparc/cpu.c c/src/exec/score/cpu/sparc/cpu.h c/src/exec/score/cpu/sparc/cpu_asm.s c/src/exec/score/cpu/sparc/erc32.h c/src/exec/score/cpu/sparc/rtems.s c/src/exec/score/cpu/sparc/sparc.h c/src/exec/score/cpu/sparc/sparctypes.h c/src/exec/score/include/rtems/debug.h c/src/exec/score/include/rtems/score/address.h c/src/exec/score/include/rtems/score/apiext.h c/src/exec/score/include/rtems/score/bitfield.h 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c/src/lib/libcpu/hppa1.1/timer/timer.c c/src/lib/libcpu/powerpc/README c/src/lib/libcpu/powerpc/ppc403/README c/src/lib/libcpu/powerpc/ppc403/clock/clock.c c/src/lib/libcpu/powerpc/ppc403/console/console.c c/src/lib/libcpu/powerpc/ppc403/timer/timer.c c/src/lib/libcpu/powerpc/ppc403/vectors/README c/src/lib/libcpu/powerpc/ppc403/vectors/align_h.s c/src/lib/libcpu/powerpc/ppc403/vectors/vectors.s c/src/lib/libcpu/sparc/include/erc32.h c/src/lib/libcpu/sparc/reg_win/window.s c/src/libchip/shmdr/README c/src/libchip/shmdr/addlq.c c/src/libchip/shmdr/cnvpkt.c c/src/libchip/shmdr/dump.c c/src/libchip/shmdr/fatal.c c/src/libchip/shmdr/getlq.c c/src/libchip/shmdr/getpkt.c c/src/libchip/shmdr/init.c c/src/libchip/shmdr/initlq.c c/src/libchip/shmdr/intr.c c/src/libchip/shmdr/mpci.h c/src/libchip/shmdr/mpisr.c c/src/libchip/shmdr/poll.c c/src/libchip/shmdr/receive.c c/src/libchip/shmdr/retpkt.c c/src/libchip/shmdr/send.c c/src/libchip/shmdr/setckvec.c c/src/libchip/shmdr/shm_driver.h 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testsuites/sptests/sp05/sp05.doc testsuites/sptests/sp05/sp05.scn testsuites/sptests/sp05/system.h testsuites/sptests/sp05/task1.c testsuites/sptests/sp05/task2.c testsuites/sptests/sp05/task3.c testsuites/sptests/sp06/init.c testsuites/sptests/sp06/sp06.doc testsuites/sptests/sp06/sp06.scn testsuites/sptests/sp06/system.h testsuites/sptests/sp06/task1.c testsuites/sptests/sp06/task2.c testsuites/sptests/sp06/task3.c testsuites/sptests/sp07/init.c testsuites/sptests/sp07/sp07.doc testsuites/sptests/sp07/sp07.scn testsuites/sptests/sp07/system.h testsuites/sptests/sp07/task1.c testsuites/sptests/sp07/task2.c testsuites/sptests/sp07/task3.c testsuites/sptests/sp07/task4.c testsuites/sptests/sp07/taskexit.c testsuites/sptests/sp07/tcreate.c testsuites/sptests/sp07/tdelete.c testsuites/sptests/sp07/trestart.c testsuites/sptests/sp07/tstart.c testsuites/sptests/sp08/init.c testsuites/sptests/sp08/sp08.doc testsuites/sptests/sp08/sp08.scn testsuites/sptests/sp08/system.h testsuites/sptests/sp08/task1.c testsuites/sptests/sp09/delay.c testsuites/sptests/sp09/init.c testsuites/sptests/sp09/isr.c testsuites/sptests/sp09/screen01.c testsuites/sptests/sp09/screen02.c testsuites/sptests/sp09/screen03.c testsuites/sptests/sp09/screen04.c testsuites/sptests/sp09/screen05.c testsuites/sptests/sp09/screen06.c testsuites/sptests/sp09/screen07.c testsuites/sptests/sp09/screen08.c testsuites/sptests/sp09/screen09.c testsuites/sptests/sp09/screen10.c testsuites/sptests/sp09/screen11.c testsuites/sptests/sp09/screen12.c testsuites/sptests/sp09/screen13.c testsuites/sptests/sp09/screen14.c testsuites/sptests/sp09/sp09.doc testsuites/sptests/sp09/sp09.scn testsuites/sptests/sp09/system.h testsuites/sptests/sp09/task1.c testsuites/sptests/sp09/task2.c testsuites/sptests/sp09/task3.c testsuites/sptests/sp09/task4.c testsuites/sptests/sp11/init.c testsuites/sptests/sp11/sp11.doc testsuites/sptests/sp11/sp11.scn testsuites/sptests/sp11/system.h testsuites/sptests/sp11/task1.c testsuites/sptests/sp11/task2.c testsuites/sptests/sp11/timer.c testsuites/sptests/sp12/init.c testsuites/sptests/sp12/pridrv.c testsuites/sptests/sp12/pritask.c testsuites/sptests/sp12/sp12.doc testsuites/sptests/sp12/sp12.scn testsuites/sptests/sp12/system.h testsuites/sptests/sp12/task1.c testsuites/sptests/sp12/task2.c testsuites/sptests/sp12/task3.c testsuites/sptests/sp12/task4.c testsuites/sptests/sp12/task5.c testsuites/sptests/sp13/fillbuff.c testsuites/sptests/sp13/init.c testsuites/sptests/sp13/putbuff.c testsuites/sptests/sp13/sp13.doc testsuites/sptests/sp13/sp13.scn testsuites/sptests/sp13/system.h testsuites/sptests/sp13/task1.c testsuites/sptests/sp13/task2.c testsuites/sptests/sp13/task3.c testsuites/sptests/sp14/asr.c testsuites/sptests/sp14/init.c testsuites/sptests/sp14/sp14.doc testsuites/sptests/sp14/sp14.scn testsuites/sptests/sp14/system.h testsuites/sptests/sp14/task1.c testsuites/sptests/sp14/task2.c testsuites/sptests/sp15/init.c testsuites/sptests/sp15/sp15.doc testsuites/sptests/sp15/sp15.scn testsuites/sptests/sp15/system.h testsuites/sptests/sp15/task1.c testsuites/sptests/sp16/init.c testsuites/sptests/sp16/sp16.doc testsuites/sptests/sp16/sp16.scn testsuites/sptests/sp16/system.h testsuites/sptests/sp16/task1.c testsuites/sptests/sp16/task2.c testsuites/sptests/sp16/task3.c testsuites/sptests/sp16/task4.c testsuites/sptests/sp16/task5.c testsuites/sptests/sp17/asr.c testsuites/sptests/sp17/init.c testsuites/sptests/sp17/sp17.doc testsuites/sptests/sp17/sp17.scn testsuites/sptests/sp17/system.h testsuites/sptests/sp17/task1.c testsuites/sptests/sp17/task2.c testsuites/sptests/sp19/first.c testsuites/sptests/sp19/fptask.c testsuites/sptests/sp19/fptest.h testsuites/sptests/sp19/init.c testsuites/sptests/sp19/inttest.h testsuites/sptests/sp19/sp19.doc testsuites/sptests/sp19/sp19.scn testsuites/sptests/sp19/system.h testsuites/sptests/sp19/task1.c testsuites/sptests/sp20/getall.c testsuites/sptests/sp20/init.c testsuites/sptests/sp20/sp20.doc testsuites/sptests/sp20/sp20.scn testsuites/sptests/sp20/system.h testsuites/sptests/sp20/task1.c testsuites/sptests/sp21/init.c testsuites/sptests/sp21/sp21.doc testsuites/sptests/sp21/sp21.scn testsuites/sptests/sp21/system.h testsuites/sptests/sp21/task1.c testsuites/sptests/sp22/delay.c testsuites/sptests/sp22/init.c testsuites/sptests/sp22/prtime.c testsuites/sptests/sp22/sp22.doc testsuites/sptests/sp22/sp22.scn testsuites/sptests/sp22/system.h testsuites/sptests/sp22/task1.c testsuites/sptests/sp23/init.c testsuites/sptests/sp23/sp23.doc testsuites/sptests/sp23/sp23.scn testsuites/sptests/sp23/system.h testsuites/sptests/sp23/task1.c testsuites/sptests/sp24/init.c testsuites/sptests/sp24/resume.c testsuites/sptests/sp24/sp24.doc testsuites/sptests/sp24/sp24.scn testsuites/sptests/sp24/system.h testsuites/sptests/sp24/task1.c testsuites/sptests/sp25/init.c testsuites/sptests/sp25/sp25.doc testsuites/sptests/sp25/sp25.scn testsuites/sptests/sp25/system.h testsuites/sptests/sp25/task1.c testsuites/sptests/spfatal/fatal.c testsuites/sptests/spfatal/init.c testsuites/sptests/spfatal/puterr.c testsuites/sptests/spfatal/spfatal.doc testsuites/sptests/spfatal/spfatal.scn testsuites/sptests/spfatal/system.h testsuites/sptests/spfatal/task1.c testsuites/sptests/spsize/getint.c testsuites/sptests/spsize/init.c testsuites/sptests/spsize/size.c testsuites/sptests/spsize/system.h testsuites/support/include/tmacros.h testsuites/tmtests/README testsuites/tmtests/include/timesys.h testsuites/tmtests/tm01/system.h testsuites/tmtests/tm01/task1.c testsuites/tmtests/tm01/tm01.doc testsuites/tmtests/tm02/system.h testsuites/tmtests/tm02/task1.c testsuites/tmtests/tm02/tm02.doc testsuites/tmtests/tm03/system.h testsuites/tmtests/tm03/task1.c testsuites/tmtests/tm03/tm03.doc testsuites/tmtests/tm04/system.h testsuites/tmtests/tm04/task1.c testsuites/tmtests/tm04/tm04.doc testsuites/tmtests/tm05/system.h testsuites/tmtests/tm05/task1.c testsuites/tmtests/tm05/tm05.doc testsuites/tmtests/tm06/system.h testsuites/tmtests/tm06/task1.c testsuites/tmtests/tm06/tm06.doc testsuites/tmtests/tm07/system.h testsuites/tmtests/tm07/task1.c testsuites/tmtests/tm07/tm07.doc testsuites/tmtests/tm08/system.h testsuites/tmtests/tm08/task1.c testsuites/tmtests/tm08/tm08.doc testsuites/tmtests/tm09/system.h testsuites/tmtests/tm09/task1.c testsuites/tmtests/tm09/tm09.doc testsuites/tmtests/tm10/system.h testsuites/tmtests/tm10/task1.c testsuites/tmtests/tm10/tm10.doc testsuites/tmtests/tm11/system.h testsuites/tmtests/tm11/task1.c testsuites/tmtests/tm11/tm11.doc testsuites/tmtests/tm12/system.h testsuites/tmtests/tm12/task1.c testsuites/tmtests/tm12/tm12.doc testsuites/tmtests/tm13/system.h testsuites/tmtests/tm13/task1.c testsuites/tmtests/tm13/tm13.doc testsuites/tmtests/tm14/system.h testsuites/tmtests/tm14/task1.c testsuites/tmtests/tm14/tm14.doc testsuites/tmtests/tm15/system.h testsuites/tmtests/tm15/task1.c testsuites/tmtests/tm15/tm15.doc testsuites/tmtests/tm16/system.h testsuites/tmtests/tm16/task1.c testsuites/tmtests/tm16/tm16.doc testsuites/tmtests/tm17/system.h testsuites/tmtests/tm17/task1.c testsuites/tmtests/tm17/tm17.doc testsuites/tmtests/tm18/system.h testsuites/tmtests/tm18/task1.c testsuites/tmtests/tm18/tm18.doc testsuites/tmtests/tm19/system.h testsuites/tmtests/tm19/task1.c testsuites/tmtests/tm19/tm19.doc testsuites/tmtests/tm20/system.h testsuites/tmtests/tm20/task1.c testsuites/tmtests/tm20/tm20.doc testsuites/tmtests/tm21/system.h testsuites/tmtests/tm21/task1.c testsuites/tmtests/tm21/tm21.doc testsuites/tmtests/tm22/system.h testsuites/tmtests/tm22/task1.c testsuites/tmtests/tm22/tm22.doc testsuites/tmtests/tm23/system.h testsuites/tmtests/tm23/task1.c testsuites/tmtests/tm23/tm23.doc testsuites/tmtests/tm24/system.h testsuites/tmtests/tm24/task1.c testsuites/tmtests/tm24/tm24.doc testsuites/tmtests/tm25/system.h testsuites/tmtests/tm25/task1.c testsuites/tmtests/tm25/tm25.doc testsuites/tmtests/tm26/fptest.h testsuites/tmtests/tm26/system.h testsuites/tmtests/tm26/task1.c testsuites/tmtests/tm26/tm26.doc testsuites/tmtests/tm27/system.h testsuites/tmtests/tm27/task1.c testsuites/tmtests/tm27/tm27.doc testsuites/tmtests/tm28/system.h testsuites/tmtests/tm28/task1.c testsuites/tmtests/tm28/tm28.doc testsuites/tmtests/tm29/system.h testsuites/tmtests/tm29/task1.c testsuites/tmtests/tm29/tm29.doc testsuites/tmtests/tmck/system.h testsuites/tmtests/tmck/task1.c testsuites/tmtests/tmck/tmck.doc testsuites/tmtests/tmoverhd/dumrtems.h testsuites/tmtests/tmoverhd/empty.c testsuites/tmtests/tmoverhd/system.h testsuites/tmtests/tmoverhd/testtask.c testsuites/tmtests/tmoverhd/tmoverhd.doc tools/build/README tools/build/cklength.c tools/build/eolstrip.c tools/build/os/msdos/README tools/build/os/msdos/cklength.uue tools/build/os/msdos/fixtimer.c tools/build/os/msdos/fixtimer.uue tools/build/os/msdos/ifc.c tools/build/os/msdos/ifc_exe.uue tools/build/packhex.c tools/build/scripts/README tools/build/src/cklength.c tools/build/src/eolstrip.c tools/build/src/packhex.c tools/build/src/unhex.c tools/build/unhex.c tools/cpu/hppa1.1/genoffsets.c tools/cpu/unix/gensize.c tools/update/310_to_320_list tools/update/README
Diffstat (limited to 'c/src/exec/score/cpu/sparc/cpu.h')
-rw-r--r--c/src/exec/score/cpu/sparc/cpu.h993
1 files changed, 0 insertions, 993 deletions
diff --git a/c/src/exec/score/cpu/sparc/cpu.h b/c/src/exec/score/cpu/sparc/cpu.h
deleted file mode 100644
index b6bcb91738..0000000000
--- a/c/src/exec/score/cpu/sparc/cpu.h
+++ /dev/null
@@ -1,993 +0,0 @@
-/* cpu.h
- *
- * This include file contains information pertaining to the port of
- * the executive to the SPARC processor.
- *
- * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994.
- * On-Line Applications Research Corporation (OAR).
- * All rights assigned to U.S. Government, 1994.
- *
- * This material may be reproduced by or for the U.S. Government pursuant
- * to the copyright license under the clause at DFARS 252.227-7013. This
- * notice must appear in all copies of this file and its derivatives.
- *
- * Ported to ERC32 implementation of the SPARC by On-Line Applications
- * Research Corporation (OAR) under contract to the European Space
- * Agency (ESA).
- *
- * ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
- * European Space Agency.
- *
- * $Id$
- */
-
-#ifndef __CPU_h
-#define __CPU_h
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <rtems/score/sparc.h> /* pick up machine definitions */
-#ifndef ASM
-#include <rtems/score/sparctypes.h>
-#endif
-
-/* conditional compilation parameters */
-
-/*
- * Should the calls to _Thread_Enable_dispatch be inlined?
- *
- * If TRUE, then they are inlined.
- * If FALSE, then a subroutine call is made.
- */
-
-#define CPU_INLINE_ENABLE_DISPATCH TRUE
-
-/*
- * Should the body of the search loops in _Thread_queue_Enqueue_priority
- * be unrolled one time? In unrolled each iteration of the loop examines
- * two "nodes" on the chain being searched. Otherwise, only one node
- * is examined per iteration.
- *
- * If TRUE, then the loops are unrolled.
- * If FALSE, then the loops are not unrolled.
- *
- * This parameter could go either way on the SPARC. The interrupt flash
- * code is relatively lengthy given the requirements for nops following
- * writes to the psr. But if the clock speed were high enough, this would
- * not represent a great deal of time.
- */
-
-#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
-
-/*
- * Does the executive manage a dedicated interrupt stack in software?
- *
- * If TRUE, then a stack is allocated in _Interrupt_Manager_initialization.
- * If FALSE, nothing is done.
- *
- * The SPARC does not have a dedicated HW interrupt stack and one has
- * been implemented in SW.
- */
-
-#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
-
-/*
- * Does this CPU have hardware support for a dedicated interrupt stack?
- *
- * If TRUE, then it must be installed during initialization.
- * If FALSE, then no installation is performed.
- *
- * The SPARC does not have a dedicated HW interrupt stack.
- */
-
-#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
-
-/*
- * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
- *
- * If TRUE, then the memory is allocated during initialization.
- * If FALSE, then the memory is allocated during initialization.
- */
-
-#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
-
-/*
- * Does the CPU have hardware floating point?
- *
- * If TRUE, then the FLOATING_POINT task attribute is supported.
- * If FALSE, then the FLOATING_POINT task attribute is ignored.
- */
-
-#if ( SPARC_HAS_FPU == 1 )
-#define CPU_HARDWARE_FP TRUE
-#else
-#define CPU_HARDWARE_FP FALSE
-#endif
-
-/*
- * Are all tasks FLOATING_POINT tasks implicitly?
- *
- * If TRUE, then the FLOATING_POINT task attribute is assumed.
- * If FALSE, then the FLOATING_POINT task attribute is followed.
- */
-
-#define CPU_ALL_TASKS_ARE_FP FALSE
-
-/*
- * Should the IDLE task have a floating point context?
- *
- * If TRUE, then the IDLE task is created as a FLOATING_POINT task
- * and it has a floating point context which is switched in and out.
- * If FALSE, then the IDLE task does not have a floating point context.
- */
-
-#define CPU_IDLE_TASK_IS_FP FALSE
-
-/*
- * Should the saving of the floating point registers be deferred
- * until a context switch is made to another different floating point
- * task?
- *
- * If TRUE, then the floating point context will not be stored until
- * necessary. It will remain in the floating point registers and not
- * disturned until another floating point task is switched to.
- *
- * If FALSE, then the floating point context is saved when a floating
- * point task is switched out and restored when the next floating point
- * task is restored. The state of the floating point registers between
- * those two operations is not specified.
- */
-
-#define CPU_USE_DEFERRED_FP_SWITCH TRUE
-
-/*
- * Does this port provide a CPU dependent IDLE task implementation?
- *
- * If TRUE, then the routine _CPU_Internal_threads_Idle_thread_body
- * must be provided and is the default IDLE thread body instead of
- * _Internal_threads_Idle_thread_body.
- *
- * If FALSE, then use the generic IDLE thread body if the BSP does
- * not provide one.
- */
-
-#if (SPARC_HAS_LOW_POWER_MODE == 1)
-#define CPU_PROVIDES_IDLE_THREAD_BODY TRUE
-#else
-#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
-#endif
-
-/*
- * Does the stack grow up (toward higher addresses) or down
- * (toward lower addresses)?
- *
- * If TRUE, then the grows upward.
- * If FALSE, then the grows toward smaller addresses.
- *
- * The stack grows to lower addresses on the SPARC.
- */
-
-#define CPU_STACK_GROWS_UP FALSE
-
-/*
- * The following is the variable attribute used to force alignment
- * of critical data structures. On some processors it may make
- * sense to have these aligned on tighter boundaries than
- * the minimum requirements of the compiler in order to have as
- * much of the critical data area as possible in a cache line.
- *
- * The SPARC does not appear to have particularly strict alignment
- * requirements. This value was chosen to take advantages of caches.
- */
-
-#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
-
-/*
- * The following defines the number of bits actually used in the
- * interrupt field of the task mode. How those bits map to the
- * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
- *
- * The SPARC has 16 interrupt levels in the PIL field of the PSR.
- */
-
-#define CPU_MODES_INTERRUPT_MASK 0x0000000F
-
-/*
- * This structure represents the organization of the minimum stack frame
- * for the SPARC. More framing information is required in certain situaions
- * such as when there are a large number of out parameters or when the callee
- * must save floating point registers.
- */
-
-#ifndef ASM
-
-typedef struct {
- unsigned32 l0;
- unsigned32 l1;
- unsigned32 l2;
- unsigned32 l3;
- unsigned32 l4;
- unsigned32 l5;
- unsigned32 l6;
- unsigned32 l7;
- unsigned32 i0;
- unsigned32 i1;
- unsigned32 i2;
- unsigned32 i3;
- unsigned32 i4;
- unsigned32 i5;
- unsigned32 i6_fp;
- unsigned32 i7;
- void *structure_return_address;
- /*
- * The following are for the callee to save the register arguments in
- * should this be necessary.
- */
- unsigned32 saved_arg0;
- unsigned32 saved_arg1;
- unsigned32 saved_arg2;
- unsigned32 saved_arg3;
- unsigned32 saved_arg4;
- unsigned32 saved_arg5;
- unsigned32 pad0;
-} CPU_Minimum_stack_frame;
-
-#endif /* ASM */
-
-#define CPU_STACK_FRAME_L0_OFFSET 0x00
-#define CPU_STACK_FRAME_L1_OFFSET 0x04
-#define CPU_STACK_FRAME_L2_OFFSET 0x08
-#define CPU_STACK_FRAME_L3_OFFSET 0x0c
-#define CPU_STACK_FRAME_L4_OFFSET 0x10
-#define CPU_STACK_FRAME_L5_OFFSET 0x14
-#define CPU_STACK_FRAME_L6_OFFSET 0x18
-#define CPU_STACK_FRAME_L7_OFFSET 0x1c
-#define CPU_STACK_FRAME_I0_OFFSET 0x20
-#define CPU_STACK_FRAME_I1_OFFSET 0x24
-#define CPU_STACK_FRAME_I2_OFFSET 0x28
-#define CPU_STACK_FRAME_I3_OFFSET 0x2c
-#define CPU_STACK_FRAME_I4_OFFSET 0x30
-#define CPU_STACK_FRAME_I5_OFFSET 0x34
-#define CPU_STACK_FRAME_I6_FP_OFFSET 0x38
-#define CPU_STACK_FRAME_I7_OFFSET 0x3c
-#define CPU_STRUCTURE_RETURN_ADDRESS_OFFSET 0x40
-#define CPU_STACK_FRAME_SAVED_ARG0_OFFSET 0x44
-#define CPU_STACK_FRAME_SAVED_ARG1_OFFSET 0x48
-#define CPU_STACK_FRAME_SAVED_ARG2_OFFSET 0x4c
-#define CPU_STACK_FRAME_SAVED_ARG3_OFFSET 0x50
-#define CPU_STACK_FRAME_SAVED_ARG4_OFFSET 0x54
-#define CPU_STACK_FRAME_SAVED_ARG5_OFFSET 0x58
-#define CPU_STACK_FRAME_PAD0_OFFSET 0x5c
-
-#define CPU_MINIMUM_STACK_FRAME_SIZE 0x60
-
-/*
- * Contexts
- *
- * Generally there are 2 types of context to save.
- * 1. Interrupt registers to save
- * 2. Task level registers to save
- *
- * This means we have the following 3 context items:
- * 1. task level context stuff:: Context_Control
- * 2. floating point task stuff:: Context_Control_fp
- * 3. special interrupt level context :: Context_Control_interrupt
- *
- * On the SPARC, we are relatively conservative in that we save most
- * of the CPU state in the context area. The ET (enable trap) bit and
- * the CWP (current window pointer) fields of the PSR are considered
- * system wide resources and are not maintained on a per-thread basis.
- */
-
-#ifndef ASM
-
-typedef struct {
- /*
- * Using a double g0_g1 will put everything in this structure on a
- * double word boundary which allows us to use double word loads
- * and stores safely in the context switch.
- */
- double g0_g1;
- unsigned32 g2;
- unsigned32 g3;
- unsigned32 g4;
- unsigned32 g5;
- unsigned32 g6;
- unsigned32 g7;
-
- unsigned32 l0;
- unsigned32 l1;
- unsigned32 l2;
- unsigned32 l3;
- unsigned32 l4;
- unsigned32 l5;
- unsigned32 l6;
- unsigned32 l7;
-
- unsigned32 i0;
- unsigned32 i1;
- unsigned32 i2;
- unsigned32 i3;
- unsigned32 i4;
- unsigned32 i5;
- unsigned32 i6_fp;
- unsigned32 i7;
-
- unsigned32 o0;
- unsigned32 o1;
- unsigned32 o2;
- unsigned32 o3;
- unsigned32 o4;
- unsigned32 o5;
- unsigned32 o6_sp;
- unsigned32 o7;
-
- unsigned32 psr;
-} Context_Control;
-
-#endif /* ASM */
-
-/*
- * Offsets of fields with Context_Control for assembly routines.
- */
-
-#define G0_OFFSET 0x00
-#define G1_OFFSET 0x04
-#define G2_OFFSET 0x08
-#define G3_OFFSET 0x0C
-#define G4_OFFSET 0x10
-#define G5_OFFSET 0x14
-#define G6_OFFSET 0x18
-#define G7_OFFSET 0x1C
-
-#define L0_OFFSET 0x20
-#define L1_OFFSET 0x24
-#define L2_OFFSET 0x28
-#define L3_OFFSET 0x2C
-#define L4_OFFSET 0x30
-#define L5_OFFSET 0x34
-#define L6_OFFSET 0x38
-#define L7_OFFSET 0x3C
-
-#define I0_OFFSET 0x40
-#define I1_OFFSET 0x44
-#define I2_OFFSET 0x48
-#define I3_OFFSET 0x4C
-#define I4_OFFSET 0x50
-#define I5_OFFSET 0x54
-#define I6_FP_OFFSET 0x58
-#define I7_OFFSET 0x5C
-
-#define O0_OFFSET 0x60
-#define O1_OFFSET 0x64
-#define O2_OFFSET 0x68
-#define O3_OFFSET 0x6C
-#define O4_OFFSET 0x70
-#define O5_OFFSET 0x74
-#define O6_SP_OFFSET 0x78
-#define O7_OFFSET 0x7C
-
-#define PSR_OFFSET 0x80
-
-#define CONTEXT_CONTROL_SIZE 0x84
-
-/*
- * The floating point context area.
- */
-
-#ifndef ASM
-
-typedef struct {
- double f0_f1;
- double f2_f3;
- double f4_f5;
- double f6_f7;
- double f8_f9;
- double f10_f11;
- double f12_f13;
- double f14_f15;
- double f16_f17;
- double f18_f19;
- double f20_f21;
- double f22_f23;
- double f24_f25;
- double f26_f27;
- double f28_f29;
- double f30_f31;
- unsigned32 fsr;
-} Context_Control_fp;
-
-#endif /* ASM */
-
-/*
- * Offsets of fields with Context_Control_fp for assembly routines.
- */
-
-#define FO_F1_OFFSET 0x00
-#define F2_F3_OFFSET 0x08
-#define F4_F5_OFFSET 0x10
-#define F6_F7_OFFSET 0x18
-#define F8_F9_OFFSET 0x20
-#define F1O_F11_OFFSET 0x28
-#define F12_F13_OFFSET 0x30
-#define F14_F15_OFFSET 0x38
-#define F16_F17_OFFSET 0x40
-#define F18_F19_OFFSET 0x48
-#define F2O_F21_OFFSET 0x50
-#define F22_F23_OFFSET 0x58
-#define F24_F25_OFFSET 0x60
-#define F26_F27_OFFSET 0x68
-#define F28_F29_OFFSET 0x70
-#define F3O_F31_OFFSET 0x78
-#define FSR_OFFSET 0x80
-
-#define CONTEXT_CONTROL_FP_SIZE 0x84
-
-#ifndef ASM
-
-/*
- * Context saved on stack for an interrupt.
- *
- * NOTE: The PSR, PC, and NPC are only saved in this structure for the
- * benefit of the user's handler.
- */
-
-typedef struct {
- CPU_Minimum_stack_frame Stack_frame;
- unsigned32 psr;
- unsigned32 pc;
- unsigned32 npc;
- unsigned32 g1;
- unsigned32 g2;
- unsigned32 g3;
- unsigned32 g4;
- unsigned32 g5;
- unsigned32 g6;
- unsigned32 g7;
- unsigned32 i0;
- unsigned32 i1;
- unsigned32 i2;
- unsigned32 i3;
- unsigned32 i4;
- unsigned32 i5;
- unsigned32 i6_fp;
- unsigned32 i7;
- unsigned32 y;
- unsigned32 pad0_offset;
-} CPU_Interrupt_frame;
-
-#endif /* ASM */
-
-/*
- * Offsets of fields with CPU_Interrupt_frame for assembly routines.
- */
-
-#define ISF_STACK_FRAME_OFFSET 0x00
-#define ISF_PSR_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x00
-#define ISF_PC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x04
-#define ISF_NPC_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x08
-#define ISF_G1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x0c
-#define ISF_G2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x10
-#define ISF_G3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x14
-#define ISF_G4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x18
-#define ISF_G5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x1c
-#define ISF_G6_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x20
-#define ISF_G7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x24
-#define ISF_I0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x28
-#define ISF_I1_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x2c
-#define ISF_I2_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x30
-#define ISF_I3_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x34
-#define ISF_I4_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x38
-#define ISF_I5_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x3c
-#define ISF_I6_FP_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x40
-#define ISF_I7_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x44
-#define ISF_Y_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x48
-#define ISF_PAD0_OFFSET CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
-
-#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
-#ifndef ASM
-
-/*
- * The following table contains the information required to configure
- * the processor specific parameters.
- *
- * NOTE: The interrupt_stack_size field is required if
- * CPU_ALLOCATE_INTERRUPT_STACK is defined as TRUE.
- *
- * The pretasking_hook, predriver_hook, and postdriver_hook,
- * and the do_zero_of_workspace fields are required on ALL CPUs.
- */
-
-typedef struct {
- void (*pretasking_hook)( void );
- void (*predriver_hook)( void );
- void (*postdriver_hook)( void );
- void (*idle_task)( void );
- boolean do_zero_of_workspace;
- unsigned32 interrupt_stack_size;
- unsigned32 extra_system_initialization_stack;
-} rtems_cpu_table;
-
-/*
- * This variable is contains the initialize context for the FP unit.
- * It is filled in by _CPU_Initialize and copied into the task's FP
- * context area during _CPU_Context_Initialize.
- */
-
-EXTERN Context_Control_fp _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
-
-/*
- * This stack is allocated by the Interrupt Manager and the switch
- * is performed in _ISR_Handler. These variables contain pointers
- * to the lowest and highest addresses in the chunk of memory allocated
- * for the interrupt stack. Since it is unknown whether the stack
- * grows up or down (in general), this give the CPU dependent
- * code the option of picking the version it wants to use. Thus
- * both must be present if either is.
- *
- * The SPARC supports a software based interrupt stack and these
- * are required.
- */
-
-EXTERN void *_CPU_Interrupt_stack_low;
-EXTERN void *_CPU_Interrupt_stack_high;
-
-#if defined(erc32)
-
-/*
- * ERC32 Specific Variables
- */
-
-EXTERN unsigned32 _ERC32_MEC_Timer_Control_Mirror;
-
-#endif
-
-/*
- * The following type defines an entry in the SPARC's trap table.
- *
- * NOTE: The instructions chosen are RTEMS dependent although one is
- * obligated to use two of the four instructions to perform a
- * long jump. The other instructions load one register with the
- * trap type (a.k.a. vector) and another with the psr.
- */
-
-typedef struct {
- unsigned32 mov_psr_l0; /* mov %psr, %l0 */
- unsigned32 sethi_of_handler_to_l4; /* sethi %hi(_handler), %l4 */
- unsigned32 jmp_to_low_of_handler_plus_l4; /* jmp %l4 + %lo(_handler) */
- unsigned32 mov_vector_l3; /* mov _vector, %l3 */
-} CPU_Trap_table_entry;
-
-/*
- * This is the set of opcodes for the instructions loaded into a trap
- * table entry. The routine which installs a handler is responsible
- * for filling in the fields for the _handler address and the _vector
- * trap type.
- *
- * The constants following this structure are masks for the fields which
- * must be filled in when the handler is installed.
- */
-
-extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
-
-/*
- * This is the executive's trap table which is installed into the TBR
- * register.
- *
- * NOTE: Unfortunately, this must be aligned on a 4096 byte boundary.
- * The GNU tools as of binutils 2.5.2 and gcc 2.7.0 would not
- * align an entity to anything greater than a 512 byte boundary.
- *
- * Because of this, we pull a little bit of a trick. We allocate
- * enough memory so we can grab an address on a 4096 byte boundary
- * from this area.
- */
-
-#define SPARC_TRAP_TABLE_ALIGNMENT 4096
-
-EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ]
- __attribute__ ((aligned (SPARC_TRAP_TABLE_ALIGNMENT)));
-
-
-/*
- * The size of the floating point context area.
- */
-
-#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
-
-#endif
-
-/*
- * Amount of extra stack (above minimum stack size) required by
- * system initialization thread. Remember that in a multiprocessor
- * system the system intialization thread becomes the MP server thread.
- */
-
-#define CPU_SYSTEM_INITIALIZATION_THREAD_EXTRA_STACK 1024
-
-/*
- * This defines the number of entries in the ISR_Vector_table managed
- * by the executive.
- *
- * On the SPARC, there are really only 256 vectors. However, the executive
- * has no easy, fast, reliable way to determine which traps are synchronous
- * and which are asynchronous. By default, synchronous traps return to the
- * instruction which caused the interrupt. So if you install a software
- * trap handler as an executive interrupt handler (which is desirable since
- * RTEMS takes care of window and register issues), then the executive needs
- * to know that the return address is to the trap rather than the instruction
- * following the trap.
- *
- * So vectors 0 through 255 are treated as regular asynchronous traps which
- * provide the "correct" return address. Vectors 256 through 512 are assumed
- * by the executive to be synchronous and to require that the return address
- * be fudged.
- *
- * If you use this mechanism to install a trap handler which must reexecute
- * the instruction which caused the trap, then it should be installed as
- * an asynchronous trap. This will avoid the executive changing the return
- * address.
- */
-
-#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256
-#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
-
-#define SPARC_SYNCHRONOUS_TRAP_BIT_MASK 0x100
-#define SPARC_ASYNCHRONOUS_TRAP( _trap ) (_trap)
-#define SPARC_SYNCHRONOUS_TRAP( _trap ) ((_trap) + 256 )
-
-#define SPARC_REAL_TRAP_NUMBER( _trap ) ((_trap) % 256)
-
-/*
- * Should be large enough to run all tests. This insures
- * that a "reasonable" small application should not have any problems.
- *
- * This appears to be a fairly generous number for the SPARC since
- * represents a call depth of about 20 routines based on the minimum
- * stack frame.
- */
-
-#define CPU_STACK_MINIMUM_SIZE (1024*2 + 512)
-
-/*
- * CPU's worst alignment requirement for data types on a byte boundary. This
- * alignment does not take into account the requirements for the stack.
- *
- * On the SPARC, this is required for double word loads and stores.
- */
-
-#define CPU_ALIGNMENT 8
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * heap handler. This alignment requirement may be stricter than that
- * for the data types alignment specified by CPU_ALIGNMENT. It is
- * common for the heap to follow the same alignment requirement as
- * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap,
- * then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * This number corresponds to the byte alignment requirement for memory
- * buffers allocated by the partition manager. This alignment requirement
- * may be stricter than that for the data types alignment specified by
- * CPU_ALIGNMENT. It is common for the partition to follow the same
- * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict
- * enough for the partition, then this should be set to CPU_ALIGNMENT.
- *
- * NOTE: This does not have to be a power of 2. It does have to
- * be greater or equal to than CPU_ALIGNMENT.
- */
-
-#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
-
-/*
- * This number corresponds to the byte alignment requirement for the
- * stack. This alignment requirement may be stricter than that for the
- * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT
- * is strict enough for the stack, then this should be set to 0.
- *
- * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
- *
- * The alignment restrictions for the SPARC are not that strict but this
- * should unsure that the stack is always sufficiently alignment that the
- * window overflow, underflow, and flush routines can use double word loads
- * and stores.
- */
-
-#define CPU_STACK_ALIGNMENT 16
-
-#ifndef ASM
-
-/* ISR handler macros */
-
-/*
- * Disable all interrupts for a critical section. The previous
- * level is returned in _level.
- */
-
-#define _CPU_ISR_Disable( _level ) \
- sparc_disable_interrupts( _level )
-
-/*
- * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- * This indicates the end of a critical section. The parameter
- * _level is not modified.
- */
-
-#define _CPU_ISR_Enable( _level ) \
- sparc_enable_interrupts( _level )
-
-/*
- * This temporarily restores the interrupt to _level before immediately
- * disabling them again. This is used to divide long critical
- * sections into two or more parts. The parameter _level is not
- * modified.
- */
-
-#define _CPU_ISR_Flash( _level ) \
- sparc_flash_interrupts( _level )
-
-/*
- * Map interrupt level in task mode onto the hardware that the CPU
- * actually provides. Currently, interrupt levels which do not
- * map onto the CPU in a straight fashion are undefined.
- */
-
-#define _CPU_ISR_Set_level( _newlevel ) \
- sparc_set_interrupt_level( _newlevel )
-
-unsigned32 _CPU_ISR_Get_level( void );
-
-/* end of ISR handler macros */
-
-/* Context handler macros */
-
-/*
- * Initialize the context to a state suitable for starting a
- * task after a context restore operation. Generally, this
- * involves:
- *
- * - setting a starting address
- * - preparing the stack
- * - preparing the stack and frame pointers
- * - setting the proper interrupt level in the context
- * - initializing the floating point context
- *
- * NOTE: Implemented as a subroutine for the SPARC port.
- */
-
-void _CPU_Context_Initialize(
- Context_Control *the_context,
- unsigned32 *stack_base,
- unsigned32 size,
- unsigned32 new_level,
- void *entry_point,
- boolean is_fp
-);
-
-/*
- * This routine is responsible for somehow restarting the currently
- * executing task.
- *
- * On the SPARC, this is is relatively painless but requires a small
- * amount of wrapper code before using the regular restore code in
- * of the context switch.
- */
-
-#define _CPU_Context_Restart_self( _the_context ) \
- _CPU_Context_restore( (_the_context) );
-
-/*
- * The FP context area for the SPARC is a simple structure and nothing
- * special is required to find the "starting load point"
- */
-
-#define _CPU_Context_Fp_start( _base, _offset ) \
- ( (void *) (_base) + (_offset) )
-
-/*
- * This routine initializes the FP context area passed to it to.
- *
- * The SPARC allows us to use the simple initialization model
- * in which an "initial" FP context was saved into _CPU_Null_fp_context
- * at CPU initialization and it is simply copied into the destination
- * context.
- */
-
-#define _CPU_Context_Initialize_fp( _destination ) \
- do { \
- *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
- } while (0)
-
-/* end of Context handler macros */
-
-/* Fatal Error manager macros */
-
-/*
- * This routine copies _error into a known place -- typically a stack
- * location or a register, optionally disables interrupts, and
- * halts/stops the CPU.
- */
-
-#define _CPU_Fatal_halt( _error ) \
- do { \
- unsigned32 level; \
- \
- sparc_disable_interrupts( level ); \
- asm volatile ( "mov %0, %%g1 " : "=r" (level) : "0" (level) ); \
- while (1); /* loop forever */ \
- } while (0)
-
-/* end of Fatal Error manager macros */
-
-/* Bitfield handler macros */
-
-/*
- * The SPARC port uses the generic C algorithm for bitfield scan if the
- * CPU model does not have a scan instruction.
- */
-
-#if ( SPARC_HAS_BITSCAN == 0 )
-#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
-#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
-#else
-#error "scan instruction not currently supported by RTEMS!!"
-#endif
-
-/* end of Bitfield handler macros */
-
-/* Priority handler handler macros */
-
-/*
- * The SPARC port uses the generic C algorithm for bitfield scan if the
- * CPU model does not have a scan instruction.
- */
-
-#if ( SPARC_HAS_BITSCAN == 1 )
-#error "scan instruction not currently supported by RTEMS!!"
-#endif
-
-/* end of Priority handler macros */
-
-/* functions */
-
-/*
- * _CPU_Initialize
- *
- * This routine performs CPU dependent initialization.
- */
-
-void _CPU_Initialize(
- rtems_cpu_table *cpu_table,
- void (*thread_dispatch)
-);
-
-/*
- * _CPU_ISR_install_raw_handler
- *
- * This routine installs new_handler to be directly called from the trap
- * table.
- */
-
-void _CPU_ISR_install_raw_handler(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-/*
- * _CPU_ISR_install_vector
- *
- * This routine installs an interrupt vector.
- */
-
-void _CPU_ISR_install_vector(
- unsigned32 vector,
- proc_ptr new_handler,
- proc_ptr *old_handler
-);
-
-#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
-
-/*
- * _CPU_Internal_threads_Idle_thread_body
- *
- * Some SPARC implementations have low power, sleep, or idle modes. This
- * tries to take advantage of those models.
- */
-
-void _CPU_Internal_threads_Idle_thread_body( void );
-
-#endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
-
-/*
- * _CPU_Context_switch
- *
- * This routine switches from the run context to the heir context.
- */
-
-void _CPU_Context_switch(
- Context_Control *run,
- Context_Control *heir
-);
-
-/*
- * _CPU_Context_restore
- *
- * This routine is generallu used only to restart self in an
- * efficient manner.
- */
-
-void _CPU_Context_restore(
- Context_Control *new_context
-);
-
-/*
- * _CPU_Context_save_fp
- *
- * This routine saves the floating point context passed to it.
- */
-
-void _CPU_Context_save_fp(
- void **fp_context_ptr
-);
-
-/*
- * _CPU_Context_restore_fp
- *
- * This routine restores the floating point context passed to it.
- */
-
-void _CPU_Context_restore_fp(
- void **fp_context_ptr
-);
-
-/*
- * CPU_swap_u32
- *
- * The following routine swaps the endian format of an unsigned int.
- * It must be static because it is referenced indirectly.
- *
- * This version will work on any processor, but if you come across a better
- * way for the SPARC PLEASE use it. The most common way to swap a 32-bit
- * entity as shown below is not any more efficient on the SPARC.
- *
- * swap least significant two bytes with 16-bit rotate
- * swap upper and lower 16-bits
- * swap most significant two bytes with 16-bit rotate
- *
- * It is not obvious how the SPARC can do significantly better than the
- * generic code. gcc 2.7.0 only generates about 12 instructions for the
- * following code at optimization level four (i.e. -O4).
- */
-
-static inline unsigned int CPU_swap_u32(
- unsigned int value
-)
-{
- unsigned32 byte1, byte2, byte3, byte4, swapped;
-
- byte4 = (value >> 24) & 0xff;
- byte3 = (value >> 16) & 0xff;
- byte2 = (value >> 8) & 0xff;
- byte1 = value & 0xff;
-
- swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
- return( swapped );
-}
-
-#endif ASM
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-05 18:06:04 +0000