Patch from John Cotton <john.cotton@nrc.ca>, Charles-Antoine Gauthier

<charles.gauthier@iit.nrc.ca>, and Darlene A. Stewart
<Darlene.Stewart@nrc.ca> to add support for a number of very
significant things:

  + BSPs for many variations on the Motorola MBX8xx board series
  + Cache Manager including initial support for m68040
    and PowerPC
  + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use
    same code base.
  + Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860.

1 files changed, 0 insertions, 61 deletions

diff --git a/c/src/exec/score/cpu/powerpc/old_exception_processing/ppccache.c b/c/src/exec/score/cpu/powerpc/old_exception_processing/ppccache.c
deleted file mode 100644
index ecfb4b96ca..0000000000
--- a/c/src/exec/score/cpu/powerpc/old_exception_processing/ppccache.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- *  PowerPC Cache enable routines
- *
- *  $Id$
- */
-
-#include <rtems/system.h>
-
-#define PPC_Get_HID0( _value ) \
-  do { \
-      _value = 0;        /* to avoid warnings */ \
-      asm volatile( \
-          "mfspr %0, 0x3f0;"     /* get HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-#define PPC_Set_HID0( _value ) \
-  do { \
-      asm volatile( \
-          "isync;" \
-          "mtspr 0x3f0, %0;"     /* load HID0 */ \
-          "isync" \
-          : "=r" (_value) \
-          : "0" (_value) \
-      ); \
-  } while (0)
-
-
-void powerpc_instruction_cache_enable ()
-{
-  unsigned32 value;
-
-  /*
-   * Enable the instruction cache
-   */
-
-  PPC_Get_HID0( value );
-
-  value |= 0x00008000;       /* Set ICE bit */
-
-  PPC_Set_HID0( value );
-}
-
-void powerpc_data_cache_enable ()
-{
-  unsigned32 value;
-
-  /*
-   * enable data cache
-   */
-
-  PPC_Get_HID0( value );
-
-  value |= 0x00004000;        /* set DCE bit */
-
-  PPC_Set_HID0( value );
-}
-