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| author | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:31:19 +0000 |
|---|---|---|
| committer | Joel Sherrill <joel.sherrill@OARcorp.com> | 1999-12-02 14:31:19 +0000 |
| commit | acc25eec35e186abc118b9ca4f097e22fc6b4846 (patch) | |
| tree | 7fa75871c51372e70cbd9cb50b0a2fab55cfa750 /c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl | |
| parent | Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>. (diff) | |
| download | rtems-acc25eec35e186abc118b9ca4f097e22fc6b4846.tar.bz2 | |
Merged of mcp750 and mvme2307 BSP by Eric Valette <valette@crf.canon.fr>.
As part of this effort, the mpc750 libcpu code is now shared with the
ppc6xx.
Diffstat (limited to 'c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl')
| -rw-r--r-- | c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl b/c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl new file mode 100644 index 0000000000..68f8116fe9 --- /dev/null +++ b/c/src/exec/score/cpu/powerpc/new_exception_processing/c_isr.inl @@ -0,0 +1,9 @@ +RTEMS_INLINE_ROUTINE boolean _ISR_Is_in_progress( void ) +{ + register unsigned int isr_nesting_level; + /* + * Move from special purpose register 0 (mfspr SPRG0, r3) + */ + asm volatile ("mfspr %0, 272" : "=r" (isr_nesting_level)); + return isr_nesting_level; +} |